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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adp3810/adp3811 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996 secondary side, off-line battery charger controllers functional block diagram adp3810/ adp3811 v sense v cs comp out v cc v ref gnd v ctrl 1.5m w 80k w v ref uvlo gm gm1 uvlo uvlo r1 r2 adp3810 only gm2 v ref features programmable charge current high precision battery voltage limit precision 2.000 v reference low voltage drop current sense: 300 mv full scale full operation in shorted and open battery conditions drives diode-side of optocoupler wide operating supply range: 2.7 v to 16 v undervoltage lockout so-8 package adp3810 internal precision voltage divider for battery sense four final battery voltage options available: 4.2 v, 8.4 v, 12.6 v, 16.8 v adp3811 adjustable final battery voltage applications battery charger controller for: liion batteries (adp3810) nicad, nimh batteries (adp3811) general description the adp3810 and adp3811 combine a programmable current limit with a battery voltage limit to provide a constant current, constant voltage battery charger controller. in secondary side, off-line applications, the output directly drives the diode side of an optocoupler to give isolated feedback control of a primary side pwm. the circuitry includes two gain (g m ) stages, a preci- sion 2.0 v reference, a control input buffer, an undervoltage lock out (uvlo) comparator, an output buffer and an over- voltage comparator. the current limit amplifier senses the voltage drop across an external sense resistor to control the average current for charg- ing a battery. the voltage drop can be adjusted from 25 mv to 300 mv, giving a charging current limit from 100 ma to 1.2 amps with a 0.25 w sense resistor. an external dc voltage on the v ctrl input sets the voltage drop. because this input is high impedance, a filtered pwm output can be used to set the voltage. as the battery voltage approaches its voltage limit, the voltage sense amplifier takes over to maintain a constant battery volt- age. the two amplifiers essentially operate in an or fash- ion. either the current is limited, or the voltage is limited. the adp3810 has internal thin-film resistors that are trimmed to provide a precise final voltage for liion batteries. four volt- age options are available, corresponding to 1-4 liion cells as follows: 4.2 v, 8.4 v, 12.6 v and 16.8 v. the adp3811 omits these resistors allowing any battery volt- age to be programmed with external resistors.
adp3810/adp3811Cspecifications C2C rev. 0 (C40 8 c t a +85 8 c, v cc = 10.0 v, unless otherwise noted) adp3810 parameter conditions symbol min typ max units current sense 1 full-scale current sense voltage v ctrl = 1.2 v C315 C300 C285 mv minimum current sense voltage 0.0 v v ctrl 0.1 v C32 C25 C18 mv current programming input range v ctrl 0.0 1.2 v gain (v out /v cs )r l = 1 k w a vcs 74 86 db control input bias current v ctrl pin i bctrl 10 40 na voltage sense accuracy 2 adp3810 C1.0 +1.0 % input resistanceadp3810 4.2 v option r in 210k w input resistanceadp3810 8.4 v option r in 420k w input resistanceadp3810 12.6 v option r in 630k w input resistanceadp3810 16.8 v option r in 840k w offset voltageadp3811 v os C2.5 +2.5 mv bias currentadp3811 i b 110 na gain (v out /v sense ) 3 r l = 1 k w a vbat 60 74 db reference output voltage c l = 0.1 m f 4 v ref 2.000 v accuracy adp3810 C1.0 +1.0 % adp3811 C1.8 +1.8 % load regulation i load = 0 ma to 5 ma C0.25 +0.25 % line regulation v cc = 2.7 v to 16 v 0.004 0.02 %/v output voltage noise 0.1 hz to 10 hz e n 35 m v p-p load current (sourcing) i l 510 ma output output current v cc = 2.7 v i out 46 ma saturation voltage i out = 4 ma, v cc Cv out v sat 0.1 0.4 v gain (v out /v comp )r l = 1 k w a vout 6 v/v undervoltage lockout trip point-on 2.65 2.7 v trip point-off 2.5 2.6 v power supply operating range 2.7 16 v quiescent current v cc 3 2.7 v i q 1.5 3 ma turn-off current v cc 2.5 v 0.5 1 ma overvoltage comparator threshold adp3810 percent above full scale 5 v ov %6% adp3811 percent above full scale 5 v ov %6% response time i out from 0 ma to 2 ma t r 8 m s notes 1 20 k w resistor from current sense voltage to v cs pin. 2 applies to 4.2 v, 8.4 v, 12.6 v and 16.8 v options. includes all error from offset voltage, bias current, resistor divider and voltage reference. 3 does not include attenuation of input resistor divider for adp3810. 4 0.1 m f load capacitor required for reference operation. 5 full scale is the programmed final battery voltage: 4.2 v, 8.4 v, 12.6 v or 16.8 v for the adp3810 or 2.0 v at v sense for the adp3811. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods. specifications subject to change without notice.
adp3810/adp3811 C3C rev. 0 absolute maximum ratings supply voltage, v cc . . . . . . . . . . . . . . . . . . . C0.4 v to 18 v v ctrl , v cs input range . . . . . . . . . . . . . . . . . . C0.4 v to v cc v sense input range (adp3811) . . . . . . . . . . . . C0.4 v to v cc v sense input range (adp3810) . . . . . . . . . . . C0.4 v to 20 v maximum power dissipation . . . . . . . . . . . . . . . . . . 500 mw operating temperature range . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . . C65 c to 150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c ordering guide temperature package battery model range option voltage adp3810ar-4.2 C40 c to +85 c so-8 4.2 v adp3810ar-8.4 C40 c to +85 c so-8 8.4 v adp3810ar-12.6 C40 c to +85 c so-8 12.6 v adp3810ar-16.8 C40 c to +85 c so-8 16.8 v adp3811ar C40 c to +85 c so-8 adjustable warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adp3810/adp3811 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin description mnemonic function v sense battery voltage sense input. v cs current sense input. v ref reference output. nominally 2.0 v. comp external compensation pin. out optocoupler current output drive. v ctrl dc control input to set current limit, 0 v to 1.2 v. v cc positive supply. gnd ground pin. pin configuration 1 2 3 4 8 7 6 5 top view (not to scale) adp3810 adp3811 v sense v cs comp out v cc v ref gnd v ctrl adp3810/ adp3811 v sense v cs comp out v cc v ref v ctrl 1.5m w 80k w v ref gm1 uvlo uvlo r1 adp3810 only gm2 v ref 100? r2 r1 adp3811 only r2 0.1? 2.0v 0.1? 200 w 1.2v gm3 r3 battery v bat v rcs r cs gnd i out v in return c c r c i charge dc/dc converter gnd out in ctrl uvlo buffer figure 1. simplified battery charger
adp3810/adp3811 C4C rev. 0 temperature ? c reference voltage ?volts 2.002 1.994 ?0 ?5 100 0255075 2.000 1.998 1.996 2.004 2 typical parts v cc = +10v i l = 100? c l = 0.1? figure 2. reference output voltage vs. temperature for two typical parts frequency ?hz psrr ?db ?0 ?0 ?0 100 1k 1m 10k 100k ?0 ?0 ?0 ?0 v cc = +10v i l = 100? c l = 0.1? figure 5. reference psrr vs. frequency temperature ? c current sense voltage ?mv ?94 ?96 ?04 ?0 ?5 100 0255075 ?98 ?00 ?02 v cc = +10v r3 = 20k w figure 8. full-scale current sense voltage vs. temperature load current ?ma dropout voltage ?mv 250 200 0 03 18 6 9 12 15 150 100 50 v cc = +10v c l = 0.1? figure 3. reference drop-out volt age (v cc Cv ref ) vs. load current frequency ?hz reference noise density ?nv/ ? hz 3000 2500 0 1 10 10k 100 1k 1500 1000 500 2000 v cc = +10v i l = 100? c l = 0.1? figure 6. reference noise density vs. frequency supply voltage, v cc ?volts current sense voltage ?mv ?94 ?96 ?04 24 16 6 8 10 12 14 ?98 ?00 ?02 v cc = +10v r3 = 20k w figure 9. full-scale current sense voltage vs. v cc temperature ? c reference dropout voltage ?volts 0.12 0.04 ?0 ?5 100 0255075 0.10 0.08 0.06 0.14 v cc = +10v i l = 5ma c l = 0.1? figure 4. reference dropout voltage vs. temperature control voltage, v ctrl ?volts charge current ?amps 1.6 1.4 0 0 0.2 1.4 0.4 0.6 0.8 1.0 1.2 1.0 0.2 0.8 0.6 0.4 1.2 r cs = 0.25 w r3 = 20k w figure 7. charge current vs. control voltage frequency ?hz open-loop gain ?db 100 80 ?0 40 ?0 ?0 60 20 0 10 1m 10k 0 225 135 180 45 90 100 1k c comp = 0.01? t a = +25 c v cc = +10v 100k phase shift ?degrees gain phase figure 10. gm1 open-loop gain and phase vs. frequency Ctypical performance characteristics
adp3810/adp3811 C5C rev. 0 frequency ?hz open-loop gain ?db 100 80 ?0 40 ?0 ?0 60 20 0 10 1m 10k 0 225 135 180 45 90 100 1k c comp = 0.01? t a = +25 c v cc = +10v 100k phase shift ?degrees gain phase figure 11. gm2 open-loop gain and phase vs. frequency temperature ? c gm2 offset ?mv 1.0 0.5 ?.5 ?0 ?5 100 0255075 0 ?.5 ?.0 v cc = +10v figure 14. adp3811 gm2 offset vs. temperature supply voltage, v cc ?volts v sense bias current ?na 2.5 2.0 0 03 18 6 9 12 15 1.5 1.0 0.5 t a = +25 c figure 17. adp3811 v sense bias current vs. v cc temperature ? c voltage sense accuracy ?% 1.0 0.5 ?.5 ?0 ?5 100 0 255075 0 ?.5 ?.0 v cc = +10v figure 12. adp3810 voltage sense accuracy vs. temperature supply voltage, v cc ?volts gm2 offset ?mv 1.0 0.5 ?.5 03 18 6 9 12 15 0 ?.5 ?.0 t a = +25 c figure 15. adp3811, gm2 offset vs. v cc v ov% ?% quantity ?parts 120 60 0 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 100 80 40 20 v cc = +10v t a = +25 c figure 18. overvoltage comparator distribution (v ov% ) supply voltage, v cc ?volts 1.0 0.5 ?.5 03 18 6 9 12 15 0 ?.5 ?.0 voltage sense accuracy ?% t a = +25 c figure 13. adp3810 voltage sense accuracy vs. v cc temperature ? c v sense bias current ?na 2.5 2.0 0 ?0 ?5 100 0255075 1.5 1.0 0.5 v cc = +10v figure 16. adp3811 v sense bias current vs. temperature temperature ? c v ov% ?% 12 10 2 ?0 ?5 100 0255075 8 6 4 v cc = +10v figure 19. overvoltage comparator threshold (v ov%) vs. temperature
adp3810/adp3811 C6C rev. 0 output gain (v out /v comp ) ?v/v quantity ?parts 240 120 0 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 200 160 80 40 v cc = +10v t a = +25 c r l = 1k w figure 20. output gain (v out /v comp ) distribution applications section functional description the adp3810 and adp3811 are designed for charging nicad, nimh and liion batteries. both parts provide accurate voltage sense and current sense circuitry to control the charge current and final battery voltage. figure 1 shows a simplified battery charging circuit with the adp3810/adp3811 controlling an external dc-dc converter. the converter can be one of many different types such as a buck converter, flyback converter or a linear regulator. in all cases, the adp3810/adp3811 maintains accurate control of the current and voltage loops, enabling the use of a low cost, industry standard dc-dc converter without compromising system performance. detailed realizations of complete circuits including the dc-dc converter are included later in this data sheet. the adp3810 and adp3811 contain the following blocks (shown in figure 1): ? two gm type error amplifiers control the current loop (gm1) and the voltage loop (gm2). ? a common comp node is shared by both gm amplifiers such that an rc network at this node helps compensate both control loops. ? a precision 2.0 v reference is used internally and is available externally for use by other circuitry. the 0.1 m f bypass ca- pacitor shown is required for stability. ? a current limited buffer stage (gm3) provides a current out- put, i out , to control an external dc-dc converter. this out- put can directly drive an optocoupler in isolated converter applicatio ns. the dc-dc converter must have a control scheme such that higher i out results in lower duty cycle. if this is not the case, a simple, single transistor inverter can be used for control phase inversion. ? an amplifier buffers the charge current programming volt- age, v ctrl , to provide a high impedance input. ? an uvlo circuit shuts down the gm amplifiers and the output when the supply voltage (v cc ) falls below 2.7 v. this protects the charging system from indeterminate operation. ? a transient overshoot comparator quickly increases i out when the voltage on the + input of gm2 rises over 120 mv above v ref . this clamp shuts down the dc-dc converter to quickly recover from overvoltage transients and protect ex- ternal circuitry. description of battery charging operation the ic based system shown in figure 1 charges a battery with a dc current supplied by a dc-dc converter, which is most likely a switching type supply but could also be a linear supply where feasible. the value of the charge current is controlled by the feedback loop comprised of r cs , r3, gm1, the external dc-dc converter and a dc voltage at the v ctrl input. the actual charge current is set by the voltage, v ctrl , and is dependent upon the choice for the values of r cs and r3 according to the formula below: i charge = 1 r cs r 3 80 k w v ctrl typical values are r cs = 0.25 w and r3 = 20 k w , which result in a charge current of 1.0 a for a control voltage of 1.0 v. the 80 k w resistor is internal to the ic, and it is trimmed to its ab- solute value. the positive input of gm1 is referenced to ground, forcing the v cs pin to a virtual ground. the resistor r cs converts the charge current into the voltage at v rcs , and it is this voltage that gm1 is regulating. the voltage at v rcs is equal to C(r3/80 k w ) v ctrl . when v ctrl equals 1.0 v, v rcs equals C250 mv. if v rcs falls below its pro- grammed level (i.e., the charge current increases), the negative input of gm1 goes slightly below ground. this causes the out- put of gm1 to source more current and drive the comp node high, which forces the current, i out , to increase. a higher i out decreases the drive to the dc-dc converter, reducing the charg- ing current and balancing the feedback loop. as the battery approaches its final charge voltage, the voltage loop takes over. the system becomes a voltage source, floating the battery at constant voltage thereby preventing overcharging. the constant voltage feature also protects the circuitry that is actually powered by the battery from overvoltage if the battery is removed. the voltage loop is comprised of r1, r2, gm2 and the dc-dc converter. the final battery voltage is simply set by the ratio of r1 and r2 according to the following equation (v ref = 2.000 v): v bat = 2.000 v r 1 r 2 + 1 ? ? ? ? if the battery voltage rises above its programmed voltage, v sense is pulled above v ref . this causes gm2 to source more current, raising the comp node voltage and i out . as with the v cc ?volts v out /v comp ?v/v 8 7 3 03 18 6 9 12 15 6 5 4 r l = 1k w v out = +1.0v t a = ?0 c t a = +25 c t a = +85 c figure 21. output gain (v out /v comp ) vs. v cc temperature ? c 0.25 0.20 0 ?0 ?5 100 0255075 0.15 0.10 0.05 output saturation voltage, v sat ?volts v cc = +10v i load = 5ma figure 22. v sat vs. temperature
adp3810/adp3811 C7C rev. 0 current loop, the higher i out reduces the duty cycle of the dc-dc converter and causes the battery voltage to fall, balancing the feedback loop. each gm stage is designed to be asymmetrical so that each am- plifier can only source current. the outputs are tied together at the comp node and loaded with an internal constant current sink of approximately 100 m a. whichever amplifier sources more current controls the voltage at the comp node and there- fore controls the feedback. this scheme is a realization of an analog or function where gm1 or gm2 has control of the dc-dc converter and the charging circuitry. whenever the cir- cuit is in full current limiting or full voltage limiting, the respec- tive gm stage sources an identical amount of current to the fixed current sink. the other gm stage sources zero current and is out of the loop. in the transition region, both gm stages source some of the current to comprise the full amount of the current sink. the high gains of gm1 and gm2 ensure a smooth but sharp transition from current control to voltage con- trol. figure 24 shows a graph of the transition from current to voltage mode, that was measured on the circuit in figure 23 as detailed below. notice that the cu rrent stays at its full pro- grammed level until the battery is within 200 mv of the final pro- grammed voltage (10 v in this case), which maintains fast charging through almost all of the battery voltage range. this improves the speed of charging compared to a scheme that re- duces the current at lower battery voltages. the second element in a battery charging system is some form of a dc-dc converter. to achieve high efficiency, the dc-dc con- verter can be an isolated off-line switching power supply, or it can be an isolated or nonisolated buck or other type of switch- ing power supply. for lower efficiency requirements, a linear regulator fed from a wall adapter can be used. in the above dis- cussion, the current, i out , controls the duty cycle of a switching supply; but in the case of the linear regulator, i out controls the pass transistor drive. examples of these topologies are shown later in this data sheet. if an off-line supply such as a flyback converter is used, and isolation between the control logic and the adp3810/adp3811 is required, an optocoupler can be in- serted between the adp3810/adp3811 output and the control input of the primary side pwm. charge termination if the system is charging a liion battery, the main criteria to de- termine charge termination is the absolute battery voltage. the adp3810, with its accurate reference and internal resistors, ac- complishes this task. the adp3810s guaranteed accuracy specification of 1% of the final battery voltage ensures that a liion battery will not be overcharged. this is especially impor- tant with liion batteries because overcharging can lead to cata- strophic failure. it is also important to insure that the battery be charged to a voltage equal to its optimal final voltage (typically 4.2 v per cell). stopping at less than 1% of full-scale results in a batt ery that has not been charged to its full mah capacity, reducing the batterys run time and the end equipments operat- ing time. the adp3810/adp3811 does not include circuitry to detect charge termination criteria such as C d v/ d t or d t/ d t, which are common for nicad and nimh batteries. if such charge termi- nation schemes are required, a low cost microcontroller can be added to the system to monitor the battery voltage and tempera- ture. a pwm output from the microcontroller can s ubsequently program the v ctrl input to set the charge current. the high impedance of v ctrl enables the inclusion of an rc filter to in- tegrate a pwm output into a dc control voltage. compensation the voltage and current loops have significantly different natu- ral and crossover frequencies in a battery charger application, so the two loops most likely need different pole/zero feedback com- pensation. figure 1 shows a single rc network from the comp node to ground. this is primarily for low frequency compensation (f c < 100 hz) of the voltage loop. since the comp node is shared by both gm stages, this compensation also affects the current loop. the internal 200 w resistor does change the zero location of the compensation for the current loop with respect to the voltage loop. to provide a separate higher frequency compensation (f c ~ 1 khzC10 khz), a second series rc may be needed. a detailed calculation of the com- pensation values is given later in this data sheet. adp3810 and adp3811 differences the main difference between the adp3810 and the adp3811 is illustrated in figure 1. the resistors r1 and r2 are external for the adp3811 and internal for the adp3810. the adp3810 is specifically designed for liion battery charging, and thus, the internal resistors are precision thin-film resistors laser trimmed for liion cell voltages. four different final voltage options are available in the adp3810: 4.2 v, 8.4 v, 12.6 v, and 16.8 v. for slightly different voltages to accommodate different liion chemistries, please contact the factory. the adp3811 d oes not in- clude the internal resistors, allowing the designer to choose any final battery voltage by appropriately selecting the external resis- tors. because the adp3810 is specifically for liion batteries, the reference is trimmed to a tighter accuracy specification of 1% instead of 2% for the adp3811. v ctrl input and charge current programming range the voltage on the v ctrl input determines the charge current level. this input is buffered by an internal single supply ampli- fier (labeled buffer) to allow easy programmability of v ctrl . for example, for a fixed charge current, v ctrl can be set by a resistor divider from the reference output. if a microcontroller is setting the charge current, a simple rc filter on v ctrl enables the voltage to be set by a pwm output from the micro. of course, a digital-to-analog converter could also be used, but the high impedance input makes a pwm output the economical choice. the bias current of v ctrl is typically 25 na, which flows out of the pin. the guaranteed input voltage range of the buffer is from 0.0 v to 1.2 v. when v ctrl is in the range of 0.0 v to 0.1 v, the out- put of the internal amplifier is fixed at 0.1 v. this corresponds to a charge current of 100 ma for r cs = 0.25 w , r3 = 20 k w . the graph of charge current versus v ctrl in figure 7 shows this relationship. figure 1 shows a diode in series with the buffers output and a 1.5 m w resistor from v ref to this output. the diode prevents the amplifier from sinking current, so for small input voltages the buffer has an open output. the 1.5 m w resistor forms a divider with the internal 80 k w resistor to fix the output at 0.1 v, i.e., about 10% of the maximum current. this corresponds to the typical trickle charge current level for nicad batteries. when v ctrl rises above 0.1 v, the buffer sources current and the output follows the input. the total range of v ctrl from 0.0 v. to 1.2 v results in a charge current range from 100 ma to 1.2 a (for r cs = 0.25 w , r3 = 20 k w ). larger
adp3810/adp3811 C8C rev. 0 charge current levels can be obtained by either reducing the value of r cs or increasing the value of r3. the main penalty of increasing r3 is lower efficiency due to the larger voltage drop across r cs , and the penalty of decreasing r cs is lower accuracy (but higher efficiency) as discussed below. v ref output the internal band gap reference is not only used internally for the voltage and current loops, but it is also available externally if an accurate voltage is needed. the reference employs a pnp output transistor for low dropout operation. figure 3 shows a typical graph of dropout voltage versus load current. the refer- ence is guaranteed to source 5 ma with a dropout voltage of 400 mv or less. the 0.1 m f capacitor on the reference pin is in- tegral in the compensation of the reference and is therefore re- quired for stable operation. if desired, a larger value of capacitance can also be used for the application, but a smaller value should not be used. this capacitor should be located close to the v ref pin. additional reference performance graphs are shown in fig- ures 2 through 6. output stage the output stage performs two important functions. it is a buffer for the compensation node, and as such, it has a high im- pedance input. it is also a gm stage. the out pin is a current output to enable the direct drive of an optocoupler for isolated applications. the gain from the comp node to the out pin is approximately 5 ma/v. with a load resistor of 1 k w , the voltage gain is equal to five as specified in the data sheet. a different load resistor results in a gain equal to r l (5 ma/v). figures 20 and 21 show how the gain varies from part to part and versus the supply voltage, respectively. the guaranteed output current is 5 ma, which is much more than the typical 1 ma to 2 ma re- quired in most applications. current loop accuracy considerations the accuracy of the current loop is dependent on several factors such as the offset of gm1, the offset of the v ctrl buffer, the ra- tio of the internal 80 k w compared to the external 20 k w resis- tor, and the accuracy of r cs . the specification for current loop accuracy states that the full-scale current sense voltage, v rcs , of C300 mv is guaranteed to be within 15 mv of this value. this assumes an exact 20 k w resistor for r3. any errors in this resis- tor will result in further errors in the charge current value. for example, a 5% error in resistor value will add a 5% error to the charge current. the same is true for r cs , the current sense resis- tor. thus, 1% or better resistors are re commended. as mentioned above, decreasing the value of r cs increases the charge current. since it is v rcs that is specified, the actual value of r cs is not accounted for in the specification. an example where r cs = 0.1 w illu strates its impact on the accuracy of the charge current. the range of v rcs is from C25 mv 5 mv to C300 mv 15 mv. this results in a charge current range from 250 ma 50 ma to 3 a 150 ma, as opposed to a charge cur- rent range of 100 ma 20 ma to 1.2 a 60 ma for r cs = 0.25 w . thus, not only is the minimum current changed, but the absolute variation around the set point is increased (although the percentage variation is the same). voltage loop accuracy considerations the accuracy of the voltage loop is dependent on the offset of gm2, the accuracy of the reference voltage, the bias current of gm2 through r1 and r2, and the ratio of r1/r2. for the de- manding application of charging liion batteries, the accuracy of the adp3810 is specified with respect to the final battery volt- age. this is tested in a full feedback loop so that the single ac- curacy specification given in the specification table accounts for all of the errors mentioned above. for the adp3811, the resis- tors are external, so the final voltage accuracy needs to be deter- mined by the designer. certainly, the tolerance of the resistors has a large impact on the final voltage accuracy, and 1% or bet- ter is recommended. supply range the supply range is specified from 2.7 v to 16 v. however, a final battery voltage option for the adp3810 is 16.8 v. the 16.8 v is divided down by the thin film resistors to 2.0 v inter- nally. t hus, the input to gm2 never sees much more than 2.0 v, which is well below the v cc voltage limit. in fact, v cc can be fixed to 2.7 v and the adp3810 will still control the charging of a 16.8 v battery stack. the adp3811, with external resistors, can charge batteries to voltages well in excess of its supply volt- age. however, if the final battery voltage is above 16 v, v cc cannot be supplied directly from the battery as it is in figure 1. alternative circuits must be employed as will be discussed later. decoupling capacitors should be located close to the supply pin. the actual value of the capacitors depends on the application, but at the very least a 0.1 m f capacitor should be used. off-line, isolated, flyback battery charger the adp3810 and adp3811 are ideal for use in isolated charg- ers. because the output stage can directly drive an optocoupler, feedback of the control signal across an isolation barrier is a simple task. figure 23 shows a complete flyback battery charger with isolation provided by the flyback transformer and the optocoupler. the essential operation of the circuit is not much different from the simplified circuit described in figure 1. the gm1 loop controls the charge current, and the gm2 loop con- trols the final battery voltage. the dc-dc converter block is comprised of a primary side pwm circuit and flyback trans- former, and the control signal passes through the optocoupler. the circuit in figure 23 incorporates all of the features neces- sary to assure long battery life with rapid charging capability. by using the adp3810 for charging liion batteries, or the adp3811 for n icad and nimh batteries, component count is minimized, reducing system cost and complexity. with the cir- cuit as presented or with its many possible variations, designers no longer need to compromise charging performance and bat- tery life to achieve a cost effective system. primary side considerations a typical current-mode flyback pwm controller was chosen for the primary control circuit for several reasons. first and most importantly, it is capable of operating from very small duty cycles to near the maximum designed duty cycle. this makes it a good choice for a wide input ac supply voltage variation re- quirement, which is usually between 70 vC270 v ac for world wide applications. add to that the additional requirement of 0% to 100% current control, and the pwm duty cycle must have a wide range. this charger achieves these ranges while maintaining stable feedback loops. the detailed operation and design of the primary side pwm is widely described in the technical literature and is not detailed here. however, the following explanation should make clear the reasons for the primary side component choices. the pwm fre- quency is set to around 100 khz as a reasonable compromise
adp3810/adp3811 C9C rev. 0 between inductive and capacitive component sizes, switching losses and cost. the primary pwm-ic circuit derives its starting v cc through a 100 k w resistor directly from the rectified ac input. after start- up, a conventional bootstrapped sourcing circuit from an auxil- iary flyback winding wouldnt work, since the flyback voltage would be reduced below the minimum v cc level specified for the 3845 under a shorted or discharged ba ttery condition. there- fore, a voltage doubler circuit was developed (as shown in fig- ure 23) that provides the minimum required v cc for the ic across the specified ac voltage range even with a shorted battery. while the signal from the adp3810/adp3811 controls the av- erage charge current, the primary side should have a cycle by cycle limit of the switching current. this current limit has to be designed so that, with a failed or malfunctioning secondary cir- cuit or optocoupler, the primary power circuit components (the fet and transformer) wont be overstressed. in addition, dur- ing start-up or for a shorted battery, v cc to the adp3810/ adp3811 wont be present. thus, the primary side current limit is the only control of the charge current. as the secondary side v cc rises above 2.7 v, the adp3810/adp3811 takes over and controls the average current. the primary side current limit is set by the 1.6 w current sense resistor connected between the power nmos transistor, irfbc30, and ground. the current drive of the adp3810/adp3811s output stage di- rectly connects to the photodiode of an optocoupler with no ad- ditional circuitry. with 5 ma of output current, the output stage can drive a variety of optocouplers. an moc8103 is shown as an example. the current of the photo-transistor flows through the 3.3 k w feedback resistor, r fb , setting the voltage at the 3845s comp pin, thus controlling the pwm duty cycle. the controlled switching regulator should be designed as shown so that more led current from the optocoupler reduces the duty cycle of the converter. approximately 1 ma should be the 9.1 w 3w 1a l n ac 120/220v 22nf 1n4148 13v 330pf 330 w 10k w 10 w 1k w 1.6 w 470pf 47? c f 1nf r f 3.3k w 3.3k w 100k w irfbc30 50?/450v tx1** 10nf 1n4148 100 w 22? c f1 1mf r3 20k w * murd320 r cs 0.25 w * c c2 0.2? r c2 300 w r4 1.2k w 3.3v 0.1? 3.3k w 2.2nf opto coupler moc8103 c f2 220? 0.1? 0.1? r1 80.6k w * r2 20k w * r c1 10k w c c1 1? v cs v cc v ref v sense out comp gnd v ctrl 0.1? adp3810/adp3811 v out battery charge current control voltage maximum v out = +10v charge current 0.1a to 1a * 1% tolerance ** tx1 f = 120khz l pr = 750? l sec = 7.5? v cc output comp v fb i sense v ref rt/ct gnd pwm 3845 figure 23. adp3810/adp3811 controlling an off-line, flyback battery charger maximum current needed to reduce the duty cycle to zero. the difference between the 5 ma drive and the 1 ma requirement leaves ample margin for variations in the optocoupler gain. secondary side considerations for the lowest cost, a current-mode flyback converter topology is used. only a single diode is needed for rectification (murd320 in figure 23), and no filter inductor is required. the diode also prevents the battery from back driving the charger when input power is disconnected. a 1 mf capacitor filters the transformer current, providing an average dc current to charge the battery. the resistor, r cs , senses the average cur- rent which is controlled via the v cs input. in this case, the charging current has high ripple due to the flyback architecture, so a low-pass filter (r3 and c c2 ) on the current sense signal is needed. this filter has an extra inverted zero due to r c2 to im- prove the phase margin of the loop. the 1 mf capacitor is con- nected between v out and the 0.25 w sense resistor. to provide additional decoupling to ground, a 220 m f capacitor is also con- nected to v out . output ripple voltage is not critical, so the out- put capacitor was selected for lowest cost instead of lowest ripple. most of the ripple current is shunted by the parallel bat- tery, if connected. if needed, high frequency ringing caused by circuit parasitics can be damped with a small rc snubber across the rectifier. the v cc source to the adp3810/adp3811 can come from a di- rect connection to the battery as long as the battery voltage re- mains below the specified 16 v operating range. if the battery voltage is less then 2.7 v (e.g., with a shorted battery, or a bat- tery discharged below its minimum voltage), the adp3810/ adp3811 will be in undervoltage lock out (uvlo) and will not drive the optocoupler. in this condition, the primary pwm circuit will run at its designed current limit. the v cc of the adp3810/adp3811 can be boosted using the circuit shown in figure 23. this circuit keeps v cc above 2.7 v as long as the
adp3810/adp3811 C10C rev. 0 battery voltage is at least 1.5 v with a programmed charge cur- rent of 0.1 a. for a higher programmed charge current, the battery voltage can drop below 1.5 v, and v cc is still maintained above 2.7 v. this is because of the additional energy in the flyback transformer, which transfers more energy through the 10 nf capacitor to v cc . the 22 m f bypass capacitor on v cc stores the energy transferred through the 10 nf capacitor. secondary side component calculations design criteria: charging a 6 cell nicad battery. max individual cell voltage: v cellmax = 1.67 v max battery stack voltage: v omax = 6 1.67 v = 10 v max charge current: i omax = 1 a max control voltage: v ctrl = 1 v (for i omax = 1 a) r s fixed value: r s = 20 k w pick a value for r1: r1 = 80.6 k w the voltage limit of 10 v is approximately 10% above the maxi- mum fully charged voltage when C d v/ d t termination is used. this limit gives a second level of protection without interfering with C d v/ d t charge termination. component value calculations: current sense resistor: r cs = v ctrl /(4 i omax ) = 1/(4 1) = 0.25 w, 1%, 0.5 w battery divider, r2: r2 = v ref r1/(v omax Cv ref ) r2 = 2 80.6 k w /(10 vC2 v) = 20.15 k w , pick 20.0 k w the final voltage and charge current accuracy is dependent upon the resistor tolerances. choose appropriate tolerances for the desired accuracy. one percent accuracy is recommended. charger performance summary the charger circuit properly executes the charging algorithm ex- hibiting stable operation regardless of battery conditions, includ- ing an open circuit load. the circuit can charge to other battery voltages by modifying only the battery voltage sense divider. as would be expected, circuit efficiency is best at high battery volt- ages. replacing the output blocking rectifier diode with a schottky would improve efficiency if the schottkys leakage could be tolerated, and its reverse voltage rating met the appli- cation requirement. v out 1.0 0.3 0.0 211 3 i limit 45678910 0.9 0.4 0.2 0.1 0.8 0.6 0.7 0.5 v ctrl = 0.125v v ctrl = 0.25v v ctrl = 0.5v v ctrl = 1.0v figure 24. charge current vs. battery voltage at four set- tings for the flyback charger in figure 23 the battery charge current vs. battery voltage characteristics for four different charge current settings are given in figure 24. the high gain of the internal amplifiers ensures the sharp transi- tion between current mode and voltage mode regardless of the charge current setting. the fact that the current remains at full charging until the battery is very close to its final voltage ensures fast charging times. the transient performance for various turn-on and turn-off con- ditions is detailed in figures 25, 26 and 27. figure 25 shows the output voltage when power is applied with no battery con- nected. as shown, the output voltage quickly rises and over- shoots its set voltage. the internal comparator responds to this and clamps the voltage giving a quick recovery. without the in- ternal comparator, an external zener would be required to clamp the voltage to the led anode. figure 26 shows the battery cur- rent when connecting and disconnecting a battery. the actual trace shown is the voltage across r cs , which is negative for cur- rent flowing into the battery. there is an overshoot when the battery is connected, but the loop quickly takes control and lim- its the average current to the programmed 0.75 a. when the battery is removed, the current quickly returns to zero. the solid band on the scope is due to the current rising and falling with the switching of the pwm. the time scale is too slow to show the detail of this. figure 27 shows the output voltage when a battery stack charged to 6 v is connected and then dis- connected. as expected, when the battery is connected, the voltage immediately goes to 6 v. when the battery is discon- nected, the voltage returns to the programmed float voltage of 10 v. again, a small overshoot is present that is clamped by the internal comparator. 10 0% 100 90 0.1sec/div 2v/div t a = +25 8 c no battery v in = 220v ac 10v 0v figure 25. flyback charger output voltage transient at power turn on, no battery attached 10 0% 100 90 20msec/div 0.2v/div 0.0v ?00mv t a = +25 8 c v ctrl = 0.775v v in = 220v ac figure 26. charge current transient response to battery connect/disconnect
adp3810/adp3811 C11C rev. 0 10 0% 100 90 50msec/div 2v/div 10v 6v t a = +25 8 c v in = 220v ac v ctrl = 1v 0v figure 27. output voltage transient response to battery connect/disconnect nonisolated topologies buck switching regulators the adp3810/adp3811 and the adp1148 can be combined to create a high efficiency buck regulator battery charger as shown in figure 28. the adp1148 is a high efficiency, synchro- nous, step-down regulator that controls two external mosfets as shown. similar to the previous flyback circuit, the adp3810 controls the average charge current and the final battery voltage, and the adp1148 controls the cycle by cycle current. the fol- lowing discussion explains the functionality of the circuit but does not go into detail on the adp1148. for more information, the adp1148 data sheet details the operation of the device and gives formulas for choosing the external components. the resistor r sense sets the cycle by cycle current limit to 1.5 a, which is far enough above the 1 a average current of the adp3810 loop to avoid interfering but still provides a safe maximum current to protect the external components. the adp3810 uses a 0.25 w resistor, r cs , to sense the battery cur- rent. as before, a 20 k w resistor is needed between r cs and the v cs input of the adp3810. the rc network from v cs to ground perf orms the dual function of filtering and compensation. the voltage loop directly senses the battery voltage. since the adp3810 is used in this circuit instead of the adp3811, v sense is connected directly to the battery. the internal resistors set the battery voltage to 8.4 v in this case. of course, other voltage options could be used, or the adp3811 could be substituted with external resistors for a user set voltage. notice the two grounds in the circuit. one ground is for the high current re- turn to the v in source and the other ground for the adp3810 circuitry. r cs separates the two grounds, and it is important to keep them separate as shown. the adjustable version of the adp1148 is used in this circuit in- stead of a fixed output version. the output voltage is fed back into the v fb pin, which is set to regulate at v bat max + 0.5 v. doing so provides a secondary, higher voltage limit without interfering with normal circuit operation. the control output of the adp3810 is connected through a 560 w resistor to the sense+ input of the adp1148. the current, i out , adjusts the dc level on the sense+ pin, which is added to the current ramp across r sense . higher i out increases the voltage on sense+ and reduces the duty cycle of the 1148, giving nega- tive feedback. the circuit as shown can quickly and safely charge liion batter- ies while maintaining high efficiency. the efficiency of the adp1148 is only degraded slightly by the addition of the adp3810 and external circuitry. the 1.5 ma of supply current lowers the overall efficiency by approximately 1%C2% for maxi- mum output current. the 0.25 w sense resistor further lowers the efficiency due to the i 2 r cs power loss at high output cur- rents. see the efficiency discussion in the adp1148 data sheet for more information. linear regulator a third charging circuit is shown in figure 29. in this case, the switc hing supply is replaced with a linear regulator. the adp3811 drives the gate of an n-channel mosfet using an external 2n3904. as before, the adp3811 senses the charge current through a 0.25 w resistor. when the current increases above the limit, the internal gm amplifier causes the output to go high. this puts more voltage across r8, increasing the current in q1. as the current increases, the gate of m1 is pulled lower, reduc- ing the gate to source voltage and decreasing the charge current to complete the feedback loop. because the adp3811 has a current output, an external 1 k w resistor is needed from the out pin to ground in order to convert the current to a voltage. 20k w 100 w r c1 2k w r sense ** 50 m w c in 100? c c1 1? 0.1? c t 68pf 0.1? c c2 220nf * coiltronics ctx-68-4 ** krl sl-1-c1-0r068j 0.1? v cc v sense +v in gnd v cs v ref v ctrl comp out adp3810 v ctrl (0v to 1v) ref & ctrl rtn r c2 560 w shutdown v fb p drive v in sense+ sense n drive s gnd p gnd c t 1000pf n ch irf7403 p ch irf7204 0v = normal >1.5v = shutdown 560 w l* 62? c out 220? 100 w battery v bat 1? v ref v in rtn adp1148 d1 10bq040 r cs 0.25 w 75k w 10 k w figure 28. high efficiency buck battery charger
adp3810/adp3811 C12C rev. 0 the trade-off between using a linear regulator as shown versus using a flyback or buck type of charger is efficiency versus sim- plicity. the linear charger in figure 29 is very simple, and it uses a minimal amount of external components. however, the efficiency is poor, especially when there is a large delta between the input output voltages. the power loss in the pass transistor is equal to (v in Cv bat ) i charge . since the circuit is powered from a wall adapter, efficiency may not be a big concern, but the heat dissipated in the pass transistor could be excessive. an important specification for this circuit is the dropout voltage, which is the difference between the input and output voltage at full charge current. there must be enough voltage to keep the n-channel mosfet on. in this case, the dropout voltage is approximately 2.2 v for a 0.5 a output current. two alternative irf7205 v in adp3811 out 2n3904 v bat 10k w 1k w adp3811 v ref 2n5058 v in adp3811 out 2n3904 v bat 10k w 250 w 2n3904 1k w a. p-channel mosfet b. npn darlington figure 30. alternative pass transistor for linear regulator realizations of the pass element are shown in figure 30. in case (a), the pass transistor is a p-channel mosfet. this provides a lower dropout voltage so that v bat can be within a few hun- dred millivolts of v in . in case (b), a darlington configuration of two npn transistors is used. the dropout voltage of this circuit is approximately 2 v for a 0.5 a charge current. stabilization of feedback loops the adp3810/adp3811 uses two transconductance error am- plifiers with merged output stages to create a shared compen- sation point (comp) for both the current and voltage loops as explained previously. since the voltage and current loops have significantly different natural crossover frequencies in a battery charger application, the two loops need different inverted zero feedback loop compensations that can be accomplished by two series rc networks. one provides the needed low freq uency (typical f c < 100 hz) compensation to the voltage loop, and the other provides a separate high frequency (f c ~ 1 khzC10 khz) compensation to the current loop. in addition, the current loop input requires a ripple reduction filter on the v cs pin to filter out switching noise. instead of placing both rc networks on the comp pin, the current loop network is placed between v cs and ground as shown in figure 23 (c c2 and r c2) . thus, it performs two functions, ripple reduction and loop compensation. loop stability criteria for battery charger applications 1. the voltage loop has to be stable when the battery is removed or floating. 2. the current loop has to be stable when the battery is being charged within its specified charge current range. 3. both loops have to be stable within the specified input source voltage range. flyback charger compensation figure 31 shows a simplified form of a battery charger system based on the off-line flyback converter presented in figure 23. with some modifications (no optocoupler, for example), this model can also be used for converters such as a buck converter (figure 28) or a linear regulator (figure 29). gm1 and gm2 are the internal gm amplifiers of the adp3810/adp3811, and gm3 is the buffered output stage that drives the optocoupler. the primary side in figure 23 is represented here by the power stage, which is modeled as gm4, a linear voltage controlled current source model of the flyback transformer and switch. the voltage error amplifier block is the internal error ampli- fier of the 3845 pwm-ic (r f = 3.3 k w in figure 23), and it is followed by an internal resistor divider. the optocoupler is modeled as a current controlled current source as shown. its output current develops a voltage, v x , across r f . the gain val- ues of all the blocks are defined below. this linear model makes the calculation of compensation values a manageable task. it also has the great benefit of allowing the simul ation of the ac response using a circuit simulator, such as pspice or microcap. for computer modeling, the gm 0.25 w * irf7201 20k w * r c1 200 w c c1 1? 0.1? 0.1? c c2 220nf 0.1? v cc v sense +v in gnd v cs v ref v ctrl comp out adp3811 v ctrl v ctrl & v ref rtn r c2 560 w 2n3904 v bat 10k w 220? 1k w battery 1? v ref v in rtn r1 80.6k w r2 20k w r8 1k w 250 w v bat = 2.0v ( + 1 ) r1 r2 figure 29. adp3811 controlling a linear battery charger
adp3810/adp3811 C13C rev. 0 of these stages is the value of gm times the load resistance. at the comp pin, the internal load resistance, r5, is typically 400 k w . the optocoupler gain is the typical value taken from the moc8103 data sheet. the voltage error amplifier gain is due to the resistor divider internal to the 3845 only. v x is the out- put of the internal amplifier, as labeled in figure 31. the actual op amp is assumed to have sufficient open-loop gain and band- width compared to the system bandwidth; as a result, it can be considered an ideal transimpedance amplifier. the pole created by the 1 nf capacitor in parallel with r f is high enough in fre- quency to not affect the compensation. the power stage gain equation is linearized based on primary side current mode control with the flyback transformer operat- ing with discontinuous inductor current. d i omax is the maxi- mum change in output current, which is equal to i omax Ci omin . since the mi nimum current is 0.0 a, d i omax = i omax = 1 a. the maximum change in control voltage is set by internal circuitry within the 3845 to d v c = 1 v. the load resistor, r load , is dif- ferent for the voltage and current loop cases. for the voltage loop without the battery, the effective load is r4, but for the current loop, the effective load is r cs . in the current loop, the voltage limit has not been reached, so the maximum output voltage is equal to the maximum output current times the load resistor. thus, the entire expression under the square root re- duces to 1.0. substituting these values into the general equation for the power stage yields the specific gain values shown for gm4. when calculating the loop gain for the voltage loop and the cur- rent loop, there are two main differences. first, gm2 applies only to the voltage loop, and gm1 applies only to the current loop. use the appropriate gm input stage for the particular loop calculations. second, there are three battery conditions to consider. for the current loop, the battery is present and un- charged. thus, the battery is modeled as a very large capaci- tance (greater than 1 farad). for the voltage loop, the battery is amplifi ers are represented by voltage controlled current sources, the optocoupler by a current controlled current source, and the error amplifier by a voltage controlled voltage source. design criteria charging a 6 cell nicad battery. max battery stack voltage: v omax = 6 1.67 v = 10 v max charge current: i omax = 1 a r s fixed value: r s = 20 k w pick a value for r1: r1 = 80.6 k w calculated current sense resistor: r cs = 0.25 w calculated voltage sense divider: r2 = 20 k w output filter cap: c f1 = 1 mf (esr = 0.1 w ) 2nd filter cap: c f2 = 200 m f (esr = 0.2 w ) gain of each block adp3810/adp3811 v cs input: gm1 = 8.3 ma/v adp3810/adp3811 v sense input: gm2 = 2.1 ma/v adp3810/adp3811 output buffer: gm3 = 6 ma/v optocoupler: itx oc = 0.36 ma/ma voltage error amplifier: a v2 = d v c /v x = 0.333 power stage (general): gm4 = d i omax d v c ? ? ? ? v omax i omax r load power stage (voltage loop): gm4 = 0.091 a/v power stage (current loop): gm4 = 1.0 a/v the gains for the adp3810/adp3811 gm amplifiers are based on typical measurements of the ics open-loop gain, and they are expressed in units of milliamps per volt. the dc voltage gain opto coupler itx oc = 0.36ma/ma c f 1nf r f 3.3k w c f1 1nf r3 20k w r cs 0.25 w c c2 0.2? r c2 300 w r1 80.6k w r4 1.2k w r c1 battery v sense v cs comp v ctrl 1.0v 80k w v fb gm3 6ma/v gm1 8.3ma/v 2.0v gm2 2.1ma/v adp3810/ adp3811 comp r5 400k w out r6 200 w +5v r voltage error amplifier a v2 = 0.33v/v v x d v c r2 20k w gm4 power stage c f2 220? c c1 2r v bat figure 31. block diagram of the linearized feedback model
adp3810/adp3811 C14C rev. 0 either present or absent. if the battery is present, its large ca- pacitance creates a very low frequency dominant pole, giving a single pole system. the more demanding case is when the bat- tery is removed. now the output pole is dependent upon the filter capacitors, c f1 and c f2 . this pole is higher in frequency, and more care must be taken to stabilize the loop response. all three cases are described in detail below. the following calculations for compensation components help to realize stable voltage and current loops. in practical designs, checking the stability using a network analyzer or a feedback loop analyzer is always recommended. the calculated compo- nent values serve as good starting values for a measurement- based optimization. the component values shown in figure 23 are slightly different from the calculated values based on this optimization procedure. to simplify the analysis further, the loop gain is split into two components: the gain from the battery to the adp3810/ adp3811s comp pin and the gain from the comp pin back to the battery. because the compensation of each loop depends upon the rc network on the comp pin, it is a convenient choice for dividing the loop calculations. definitions: modulator gain: g mod = gain in db from the comp pin to v bat . error amplifier: g ea = gain in db from v bat to the comp pin. loop gain: g loop = g mod + g ea . modulator pole: f pm , the pole present at the output of the modulator. modulator zero: f zm , the zero due to the esr, r f1 , of the filter cap, c f1 . voltage loop compensation, no battery step 1. calculate the dc loop gain (g loop ), f pm , and f zm : g mod = 20 log gm 3 itx oc r f a v 2 gm 4 r 4 [] g mod = 20 log 6 ma / v 0.36 3.3 k w 0.333 0.091 a / v 1. 2 k w ? ? = 48.3 db g ea = 20 log r 2 r 1 + r 2 gm 2 r 5 ? ? g ea = 20 log 20 k w 80 k w+ 20 k w 2.1 ma / v 400 k w ? ? = 48.5 db g loop = 44.5 db + 48.3 db = 96.8 db f pm = 1 2 p r 4 c f 1 + c f 2 () = 1 2 p 1. 2 k w 1. 2 2 mf () = 0.11 hz f zm = 1 2 p r f 1 c f 1 = 1 2 p 0.1 w 1. 0 mf = 1. 6 khz in reality, the interaction of c f1 and c f2 and their esrs create an additional pole/zero pair, but because the value of r f1 (esr of c f1 ) and r f2 (esr of c f2 ) are similar, they tend to cancel each other out. furthermore, the loop crossover is an order of magnitude lower in frequency, so the additional pole and zero have little effect on the loop response. step 2. pick the voltage and current loop crossover frequen- cies, f cv and f ci : to avoid interference between the voltage loop and the current loop, use f cv < 1/10 of f ci , the current loop crossover. the cur- rent loop crossover f ci is chosen to be ~ 1.9 khz to provide a fast current limiting response time, so pick f cv ~ 100 hz. step 3. calculate g mod at f cv : the modulator gain of 46.7 db is the dc gain. the modulator pole reduces this gain above f pm . g mod (100 hz ) = g mod ( dc ) - 20 log 1 + f cv f pm ? ? ? ? 2 g mod (100 hz ) = 48.3 db - 20 log 1 + 100 0.11 ? ? ? ? 2 =- 10.9 db step 4. calculate gain loss of g ea at f cv : to have the feedback loop gain cross over 0 db at f cv = 100 hz, g ea (100 hz) should be +10.9 db. thus, the total gain loss of g ea needed at crossover is: g loss = g ea ( dc ) C g ea (100 hz ) = 48.5 db C 10.9 db = 37.6 db step 5. determine f p needed to achieve g loss : to achieve this g loss we need to add a pole, which is located at the comp pin. gm2 has practically no parasitic loss in gain at 100 hz. its first parasitic pole occurs at approximately 500 khz as shown in figure 11. thus, the entire gain loss must be realized with an external compensation capacitor, c c1 , that sets the pole, f p1 . f p 1 = f cv 10 g loss 10 ? ? ? ? - 1 = 1. 3 hz step 6. calculate c c1 based upon f p : c c 1 = 1 2 p r 5 f p 1 ? 0. 3 m f step 7. calculate the loop phase margin, f m : the loop phase margin is a combination of the phase of the modulator pole and zero and the error amplifier pole. f m = 180 - arc tan f cv f p 1 ? ? ? ? - arc tan f cv f pm ? ? ? ? + arc tan f cv f zm ? ? ? ? ? 0 step 8. calculate r c1 to stabilize the loop: the sum of phase losses of the modulator and error amplifier re- sults in a loop phase of 0 , which is unacceptable for loop stabil- ity. to stabilize the feedback loop, we have to add a phase boosting zero to the error amplifier by inserting a resistor (r c1 ) in series with the capacitor c c1 . if the desired phase margin is f m = 60 degrees, the frequency of the zero can be calculated: f z 1 = f cv /tan f m = 57 hz from this, the r c1 resistor is calculated: r c 1 = 1 2 p f z 1 c c 1 ? 10 k w
adp3810/adp3811 C15C rev. 0 step 9. iterate c c1 : because f z1 is very close to f cv , it will increase the error ampli- fier gain in a nonnegligible amount at the 0 db point. the in- crease in gain is calculated as: 20 log 1 + f z 1 f cv ? ? ? ? 2 = 7.1 db now, the total error amplifier gain loss required is: g loss = 37.6 db + 7.1 db = 44.7 db with this, the new f p1 can be calculated from the equation in step 5. f p 1 = 0.58 hz finally, c c1 is recalculated using the equation in step 6. c c 1 = 1 2 p 400 k w 0.58 hz ? 0.7 m f following these steps gives a cookbook method for calculating the compensation components for the voltage loop. as men- tioned above, these components can be optimized in the actual circuit. the results of a pspice 1 analysis of the loop is shown in figure 32. the open loop gain of the loop is 108 db as calcu- lated. the crossover frequency is 100 hz with a phase margin of 52 . the graph shows the phase leveling off at 90 . in reality the phase will continue to fall as higher frequency parasitic poles take effect. 1 pspice is a trademark of microsim corporation. frequency ?hz ?00 phase ?degrees 0.01 100k 0.1 1 10 100 200 100 0 0 180 90 gain ?db 1k 0db crossover phase margin = 52 figure 32. voltage loop gain/phase plots voltage loop compensation, battery present when the battery has finished charging and is still connected to the charging circuitry, the system is said to be floating the bat- tery. the loop is maintaining a constant output voltage equal to the battery voltage, and the output current has dropped to nearly zero. this case is actually the easiest to compensate be- cause the batterys capacitance creates a very low frequency dominant pole, giving a single pole response. for example, if the battery is modeled as a 10 farad capacitor, the dominant pole will be 1/(2 p 1.2 k w 10 f) = 0.013 mhz. this very low fre- quency pole causes the system to cross over 0 db at less than 10 hz, giving a stable single pole system. the compensation components have little effect on this response, so no further calculations are needed for this case. current loop compensation now that the voltage loop compensation is complete, it is time to add the compensation for the current loop. the definitions for modulator gain and error amplifier gain are the same as be- fore; but now, the controlling error amplifier is gm1 in figure 31, as opposed to gm2, for the voltage loop. otherwise, the calculations are very similar. step 10. calculate the dc loop gain (g loop ), f pm , and f zm : g mod = 20 log gm 3 itx oc r f a v 2 gm 4 r cs [] g mod = 20 log 6 ma / v 0. 36 3. 3 k w 0.333 1. 0 a / v 0.25 w ? ? =- 4.5 db g ea = 20 log gm 1 r 5 [] = 20 log 8. 3 ma / v 400 k w [] = 70.4 db g loop = C6.1 db + 70.4 db = 64.3 db f pm = 1 2 p r cs + r f 1 () c f 1 = 1 2 p 0.35 w 1 mf = 450 hz f zm = 1 2 p r f 1 c f 1 = 1 2 p 0.1 w 1 mf = 1. 6 khz step 11. pick the current loop crossover frequency, f ci : from step 2 in the voltage loop calculations, f ci ~ 1.9 khz. step 12. calculate g mod at f ci : the modulator gain of C4.5 db is the dc gain. the modulator pole reduces this gain above f pm . g mod = 1. 9 khz () = g mod dc () - 20 log 1 + f ci f pm ? ? ? ? 2 + 20 log 1 + f ci f zm ? ? ? ? 2 g mod = 1. 9 khz () =- 4.5 db - 12.7 db + 3. 8 db = 13.4 db if the 1 mf capacitor has a much higher esr, e.g., 1 w , the modulator zero, f zm , will be lower in frequency than the modu- lator pole, f pm . this causes the loop gain and bandwidth to in- crease and could cause instability. one possible solution to this scenario is to use a much higher value (47 nf) for the c f = 1 nf capacitor. the pole of this capacitor would then be in the 1 khz range and would reduce the loop gain. if the esr is much less than 0.1 w , the bandwidth of the loop will decrease slightly. step 13. calculate gain loss of g ea at f ci : the gain loss of g ea in the current loop is a combination of the loss due to c c1 , r c1 and the additional loss from c c2 , r c2 . to calculate the contribution of gain roll-off needed from c c2 , r c2 , the effective gain of g ea must first be calculated. since the gain is calculated at 1.9 khz, the impedance of c c1 is 120 w . thus, the gain becomes: g ea 1. 9 khz () = 20 log gm 1 r 6 + r c 1 + 120 w () [] g ea 1. 9 khz () = 20 log 8.3 ma / v 10320 w () [] = 38.9 db g loss = g ea (1.9 khz ) C g mod (1.9 khz ) = 38.9 db C 13.4 db = 25.5 db
adp3810/adp3811 C16C rev. 0 c2203C12C10/96 printed in u.s.a. step 14. calculate value of r c2 to realize g loss : assuming that c c2 is a short, r c2 forms a resistor divider with r3, reducing the loop gain. to calculate r c2 , simply set the resis- tor ratio to give an attenuation of 25.5 db, wh ich is a loss of 1/20. r c 2 = r 3 20 - 1 = 1 k w to provide some margin in the circuit for gain fluctuations in the various stages, the final value of r c2 was adjusted down to 300 w . step 15. calculate the value of c c2 : to maintain high dc gain, a capacitor, c c2 , is connected in se- ries with r c2 . the zero provided by this rc network should be close to f ci to provide a phase boost at crossover: f z 2 ? 1. 9 khz c c 2 = 1 2 p f z 2 r c 2 = 1 2 p 1. 9 khz 300 w ? 200 nf the pole frequency due to c c2 and r3 can now be calculated as: f p 2 = 1 2 p c c 2 r 3 = 40 hz step 16. check the current loop phase margin: f m = 180 - arc tan f ci f p 2 ? ? ? ? + arc tan f ci f z 2 ? ? ? ? - arc tan f ci f pm ? ? ? ? + arc tan f ci f zm ? ? ? ? + arc tan f ci f p 1 ? ? ? ? + arc tan f ci f z 3 ? ? ? ? f m ? 115 the above formula subtracts the phase of each pole and adds the phase of each zero. the poles and zeros come in pairs, f p2 /f z2 calculated in step 15 from c c2 /r c2 ; f pm /f zm calculated in step 10 due to the output filter cap; and f p1 /f z3 due to c c1 /r c1 . f p1 is the same pole that was calculated in step 9, and f z3 needs to be recalculated with the addition of the internal 200 w resistor as follows: f z 3 = 1 2 p c c 1 r c 1 + r 6 () = 78 hz the final phase margin of 115 is more than adequate for a stable c urrent loop. in reality, higher order parasitic poles reduce the p hase margin to significantly less than 115 for a 1.9 khz crossover. the same was not the case for the voltage loop be- cause the cross over frequency of 100 hz was well below the parasitic poles. a pspice analysis of the resulting loop gain and phase for the values calculated is shown in figure 33. frequency ?hz ?0 phase ?degrees 0.01 100k 0.1 1 10 100 10k 100 50 0 0 180 100 gain ?db 1k 0db crossover phase margin = 105 figure 33. current loop gain/phase plots 8-lead small outline ic (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 outline dimensions dimensions shown in inches and (mm).

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