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| 1/35 august 2001 AN1385 application note psd913f2 / 68hc11 design guide contents n physical connections n first design example - iap with no memory paging C memory map C psdsoft express design entry n second design example - iap with memory paging C memory map C psdsoft express design entry n third design example - advanced iap with paging & swapping C memory map n conclusion n references easy flash? psd9xxf devices are members of a family of flash-based peripherals for use with embedded microcontrol- lers (mcus). these programmable system devices (psds) consist of memory, logic, and i/o. when coupled with a low- cost, rom-less 68hc11 mcu, the psd forms a complete em- bedded flash system that is 100% in-system-programmable (isp). there are many features in the psd silicon and in the psdsoft express development software that make isp easy for you, regardless of how much experience you have in embed- ded flash design. this document offers three flash 68hc11 designs using a psd913f2 device. the first is a simple system to get up and running quickly for basic applications, or to check out your pro- totype 68hc11 hardware. the second design illustrates the use memory paging. the third covers enhanced features of psd in-system-programming, including memory paging and segment swapping. you can start with the first design, and mi- grate to the second and third as your functional requirements grow. there are other members of the psd9xxf family, in- cluding the psd913f1 and the psd934f2. the psd913f1 contains some eeprom, and the psd934f2 has a larger flash memory and a larger sram than the psd913f2. see the psd9xxf data sheet for details. this application note is applicable to these other psd9xxf family members, with only slight variations. in-system programming and in-application re-programming our industry uses the term in-system programming, or isp, in a general sense. isp is applicable to programmable logic, as well as programmable non-volatile memory (nvm). however, an additional term will be used in this document: in-application re-programming (iap). there are subtle yet significant differ- ences between isp and iap when microcontrollers are in- volved. isp of memory means that the mcu is off line and not involved while memory is being programmed. iap of memory means that the mcu participates in programming memory, which is important for systems that must be online while updat- ing firmware. often, isp is well suited for manufacturing, while iap is appropriate for field updates. psd9xxf devices provide both isp and iap for your system. keep in mind that iap can only program the memory sections of the psd, not the config-
AN1385 - application note 2/35 uration and programmable logic portions of the psd. isp can program all areas of the psd. the generic problem with iap typically, a host computer downloads firmware into an embedded flash system through a communication channel that is serviced by the mcu. this channel is usually a uart, but any communication channel that the 68hc11 supports will do (modem, spi, can, j1850, etc.). the 68hc11 must execute the code that controls the iap process from an independent memory array that is not being erased or programmed. oth- erwise, boot code and flash programming algorithms (iap loader code) will be unavailable to the 68hc11. it is absolutely necessary to use an alternate memory array (an independent memory that is not being pro- grammed) to store the iap loader code. a system designer must choose the type of alternate memory to store iap loader code (rom, sram, flash, or eeprom); each type has advantages and disadvantages. this alternate memory may reside external to the mcu or reside on-board the mcu. a top-level view of an embedded isp/iap flash memory system with external memory is shown in figure 1 . figure 1. embedded flash memory system capable of iap (5 devices) a common solution for iap, some 68hc11 designers will use the fixed boot-loader feature of the 68hc11 uart to download executable code into sram (either the small on-board 68hc11 sram or an external sram chip) then 68hc11 execution jumps to that sram to execute the remainder of the download process for program- ming the main flash memory. this can be a cumbersome and error prone exercise using relocatable code in volatile memory, which is difficult to debug and is vulnerable to power outages. additionally, this method restricts the designer to use a uart to implement iap. a better, integrated solution figure 2 shows a two-chip solution using an easy flash psd913f2. this system has ample main flash memory, a second smaller alternate flash memory to hold the iap loader code and general data, and more sram. all three of these memories can operate independently and concurrently; meaning the mcu can operate from one memory while erasing/writing the other. this system also has programmable logic, expanded i/o, and design security. the two-chip solution is 100% programmable in the factory or in the field. ai04445 embedded system system i/o cpld 68hc11 host computer communication channel main flash memory 128 kbytes alternate memory for iap loader code system sram 2 kbytes 3/35 AN1385 - application note figure 2. embedded flash memory system capable of iap and isp (2 devices) by design, the iap method just described requires mcu participation to exercise a communication chan- nel to implement a download to the main flash memory. the psd9xxf also offers an alternative method (isp) to program the psd using a built-in ieee-1149.1 jtag interface requiring no mcu participation. this means that a completely blank psd can be soldered into place and the entire chip can be pro- grammed in-system using st's flashlink jtag cable and psdsoft express development software. no 68hc11 firmware needs to be written, just plug in the flashlink? cable to your pc parallel port and begin programming memory, logic, and configuration. this is a powerful feature of the psd9xxf that allows im- mediate development of application code in your lab, smart manufacturing techniques, and easy field up- dates. the flashlink cable and psdsoft express are available from our website. psdsoft express is free. let's take a quick look inside the easy flash psd913f2, as shown in figure 3. there are three indepen- dent memory arrays that are selected on a segment basis when the proper mcu address is decoded in the decode pld. the page register participates in memory decoding, which greatly simplifies memory paging. the mcu address, data, and control signals have access to most areas of the chip. the gpld has 19 combinatorial logic outputs for external device chip-selects or general logic. there are 27 i/o pins. a power management scheme can selectively shut down parts of the chip and tailor special power saving mechanisms on-the-fly. the security feature can block access to all areas of the chip from a device pro- grammer/reader. finally, the self-contained jtag-isp controller allows programming of all areas of the- chip. ai04446 embedded system system i/o jtag isp 68hc11 host computer communication channel 128 kbyte flash 32 kbyte flash 2 kbyte sram programmable logic i/o psd913f2 AN1385 - application note 4/35 figure 3. top level block diagram of psd913f2 ai04447 jtag controller gpld 19 combinatorial logicoutputs 128 kbyte primary flash 8 segments decode pld 2 kbyte sram 32 kbyte second flash 4 segments page reg power mngt mcu address / data pld bus i/o bus i/o port a mcu address / data / control bus psd913f2 mcu control device security i/o port b i/o port c i/o port d 5/35 AN1385 - application note ai04448 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 extal xtal irq xi rq pd0/rxd pd1/txd pd2/miso pd3/mosi pa3/ic4/oc5 pa4/oc4 pa7/oc1 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 cntl0 cntl1 cntl2 pd0 r/w e as r/w e as reset reset\ reset 68hc11/u1 psd/u2 spi port uart port1 12 mhz pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 2 x 16 lcd module data bus address chip select 29 28 27 23 22 21 7 6 5 4 2 52 51 3 pc0 pc1 pc3 pc4 pc5 20 19 18 14 13 17 pc2 jtag-isp connector pc6 pc7 system_reset ad7-ad0 v cc v cc spare hc11 i/o pa5/oc3 pa6/oc2 pa0/ic3 pa1/ic2 pa2/ic1 pd4/sck pd5/ss xi rq\ irq\ mod a mod b 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 47 50 49 10 laout0 25 24 mcuio0 mcuio0 mcuio0 mcuio0 cslcd mcu i/o signals r/w control 12 11 tms tck tstat terr\ tdi tdo pd1 9 pd2 8 psd913f2-15j (52 pin plcc) cslcd 48 physical connections connect your 68hc11 to the psd, as shown in figure 4. a 52-pin plcc package is used in this example. these same connections can be used for all three design examples in this document. all members of the psd9xx family share the same pinout. this example design uses an lcd module, an external chip-select for the lcd, four miscellaneous mcu controlled i/o signals, and a six-pin jtag-isp interface. there are 15 unused psd i/o pins shown (should use pullups to v cc with 100k w resistor or tie to gnd if not used in your design). figure 4. - physical connections, 68hc11 and psd913f2 AN1385 - application note 6/35 first design example - iap with no memory paging the first design example will outline the steps to get a flash memory 68hc11 system up and running quickly. no memory paging is used. you will see a memory map and the necessary design entry in the psdsoft express software development environment. a psd913f2 is used in this example, but the other members of the easy flash family may be used instead, with minor changes. see the psd9xxf data sheet for a comparison of family members memory map we are using a psd913f2, which provides 128 kbytes of main flash memory, 32 kbytes of secondary flash memory, and 2 kbytes sram. however, for this first simple example we will only use 32 kbytes of main flash memory, 16 kbytes of secondary flash memory, and 2 kbytes of sram. see the 68hc11 memory map in figure 5. figure 5. memory map for first design - iap with no memory paging note: 1. 68hc11 boots from the reset vector stored here. 2. iap loader code gets programmed here by jtag-isp or a convetional programmer tool. the nomenclature fs0, fs1, csboot0, csboot1, rs0, and csiop in figure 5 refer to the individual internal memory segments of the psd. the main psd flash memory has a total of eight 16 kbyte segments (fs0- fs7). the secondary psd flash memory has a total of four 8 kbyte segments (csboot0-csboot3). the 2 kbyte psd sram has a single segment (rs0). the internal psd control registers lie in a 256-byte address space named csiop. there is also an external memory chip-select in this example, cslcd, that is used for the lcd module. these psd memory elements are placed at the desired locations within the system memory map by pointing and clicking choices within psdsoft express software. with the memory arrangement of figure 5, the 68hc11 may perform iap by executing from the secondary ffffh ai04449 csicd, ext chip sel for lcd rs0, 2k bytes psd sram 68hc11 regs/ram csiop, psd control regs a000h - a7ffh csboot1 8k bytes secondary flash csboot0 8k bytes secondary flash nothing mapped fs1 16k bytes main flash fs0 16k bytes main flash nothing mapped e000h dfffh c000h bfffh a800h 8300h - 83ffh 9fffh 8400h 8200h - 82ffh 8000h 7fffh 4000h 3fffh 0000h (note 1) (note 2) 7/35 AN1385 - application note flash memory segments (csboot0 and csboot1) while erasing and programming the main flash memory segments (fs0 and fs1). the secondary flash memory is initially programmed though jtag-isp or other programming devices with firmware containing the following: C 68hc11 reset vector and initialization routines C 68hc11 interrupt vectors and service routines C i/o management routines C iap loader code. at power-on or after reset, the 68hc11 boots from secondary flash memory, runs a checksum of the main flash memory, programs and verifies main flash memory via the uart if necessary, then execution jumps to main flash memory. note: the memory map of figure 5 requires that the placement of internal 68hc11 registers and ram be relocated from their default base address 0000 hex to a new base address, 8000 hex. this will make your system compatible with memory paging should you decide to add paging later. there is a special register inside the 68hc11 (the init register) that facilitates this move. the init register must be written with the value of 88 hex within the first 64 mcu oscillator clocks after power up. see the 68hc11 reference manual from motorola for details on the init register. psdsoft express design entry highlights of design entry will be given here. the steps are simple and navigation through psdsoft ex- press is easy. invoke psdsoft express and follow along if you wish. invoke psdsoft express and set up your project C start psdsoft express. C create a new project. C select your project folder and name the project (in this example, name the project 'simple11' in the folder psdexpress\my_project). C select an mcu (in this example, we're using a motorola 68hc11d0, so chose 68hc(l)11dx). C select a psd913f2 and a 52-pin plcc package. this is what the screen should look like after you've made the selections: AN1385 - application note 8/35 click ok. now you will be asked if you want to use the design assistant or a pre-defined template. choose design assistant. this exercise in the design assistant will help you become familiar with the design flow. in the future, you may choose to use a template, which will make many of the choices for you, based on your selection of mcu and psd. always reference the main flow diagram shown below to help you navigate through the design process. clicking on individual boxes within the flow diagram will invoke a process. a box shadowed in red identifies the next process that needs to be completed. psdsoft express will automatically invoke the next required process only the first time though a design. when you reenter an existing design, you must choose the next process that you wish to enter from the design flow diagram. if you invoke a process that invalidates other processes downstream, the gray boxes indicate which processes must be invoked again, and the red shadow indicates which process to invoke first. 9/35 AN1385 - application note psd pin definition next you will see the pin definition screen which allows you to define each psd pin function on a point and click basis. notice that all of the psd pins that connect to the 68hc11 are already defined for you. you only have to define the remaining pins. for this example, we'll configure the psd to use: C one pin on port a to drive a single demultiplexed mcu address line out to an lcd module. C four pins on port b as general purpose mcu i/o C one pin on port b as a chip-select output for the lcd module. C six pins on port c as jtag interface signals for isp click on pa0, type in signal name of "laout0", click on 'latched address out' in the 'other' category, then 'add' or 'update'. this will produce a demultiplexed 68hc11 address line output from the psd on pin pa0 that should be routed to the lcd module on the circuit board as shown in the schematic of figure 4. this is what the screen should now look like: AN1385 - application note 10/35 now click pb0, name the signal "mcuio0", click 'mcu i/o mode' in the 'other' category, and click 'add' or 'update'. repeat for pins pb1, pb2, and pb3, giving names mcuio1, mcuio2, and mcuio3 respectively. this creates four i/o pins on port b that can be set, cleared, and read by the 68hc11 accessing psd control registers at runtime. these psd control registers reside at various address offsets from the base address designated "csiop". in a later section you will see how to place csiop within your system memory map. the screen should now look like this: 11/35 AN1385 - application note next click pin pb7, name it "cslcd", choose 'external chip-select - active-hi'. then click 'add' or 'update'. this designates pin pb7 as a chip-select output for the lcd module. the screen should have the following look: AN1385 - application note 12/35 finally, set up six pins on port c for jtag-isp. four standard jtag pins are defined by default (tms, tck, tdi, tdo). for this example, add two more jtag signals, tstat and terr, to speed the isp process (see ap- plication note an1153 to learn why it is faster with six pins). to do this, click on pin pc3, choose 'dedicated jtag - tstat' then click 'add' or 'update'. the signal name is automatically filled in. also, the signal terr on pin pc4 is automatically added since tstat and terr must be used as a pair. the screen should now look like this: that's all there is to it. click 'view' to see a summary, click 'next>>' to exit pin definition. 13/35 AN1385 - application note system memory map: psd page register and chip-select definitions now that the psd pins are defined, you will need to define the system memory map. this is accomplished by defining all the chip-selects in the system (both internal to the psd and external chip-selects), and also defining the function of the psd page register. the three memories inside the psd are individually selected segment-by-segment when mcu addresses are presented to the decode pld (dpld). each internal psd memory segment has its own individual chip-select name. for example, the main psd flash memory has eight individual chip-selects (one for each sector) named fs0 - fs7. see the psd9xxf data sheet for details. each psd memory segment must be defined in psdsoft express if it is to be accessed by the mcu. for this example, we must define the internal psd memory segment chip-selects: fs0, fs1, csboot0, csboot1, rs0, and csiop to match the memory map of figure 5. the external chip-select for the lcd mod- ule, cslcd, must also be defined, as shown in figure 5. in many 68hc11 system designs, memory paging is used to address more than 64 kbytes of address space. however, for this simple design, no paging is used, so no psd page register bits need to be de- fined. you should see the following page register definition screen appear. simply click 'next >>' since we are not using memory paging in this first design example. AN1385 - application note 14/35 now define the internal and external chip-selects. start with the internal chip-select for the psd sram, which is "rs0". then enter start and stop mcu addresses to match the memory map of figure 5. additional signal qualifiers (68hc11 control signals e, r/w, as) are not needed for internal psd memory chip-selects as this is taken care of in silicon. your screen should match the one shown below: rs0: next, define the chip-select for the internal psd control registers by clicking on "csiop" in the left side of the screen. enter the address range as shown: csiop: continue to define internal psd memory chip-selects for the main flash memory segments fs0 and fs1, and then the secondary flash memory segments csboot0 and csboot1. use figure 5 as a guide for ad- dress ranges. again, no signal qualifiers are needed for internal psd memory chip-selects. this is what the screen should look like for each chip-select: 15/35 AN1385 - application note fs0: fs1: csboot0: csboot1: AN1385 - application note 16/35 finally, define the external chip-select for the lcd module, "cslcd'. this chip-select is different for two reasons. first, it is an external chip-select that does not activate any memory element inside the psd be- cause the signal "cslcd" is output on a psd i/o pin. and second, this chip-select requires a qualifier, mean- ing that this logic signal is true only for a given mcu address range and only when another signal is active. in this case "cslcd" is true only when the mcu presents an address in the range of 8300 to 83ff hex and when the 68hc11 control signal "e" is true. notice that the signal "e" is in the list of available signal qualifiers. be sure to qualify "cslcd" with the signal "e" as shown below, then click 'done': cslcd1: 17/35 AN1385 - application note additional psd configuration now you should see the main flow diagram again. click on the box 'additional psd configuration'. this is where you may choose to set the security bit to prevent a device programmer from examining or copying the contents of the psd. you can also click through the other sheets on this screen to set the jtag user- code value and set sector protection on psd non-volatile memory segments. c code generation you can take advantage of the low-level c code drivers that are generated by psdsoft express for ac- cessing memory elements within the psd by clicking on the 'c code generation' box in the design flow window. ansi c code functions and headers are generated for you to paste into your 68hc11 c compiler environment. just tailor the code to meet your system needs and compile. c code generation can be per- formed anytime after a project is opened. to generate ansi c functions and headers, simply specify the folder(s) in which you want the header files and c source file to be written, and name the c source file. select the categories of functions that you would like to include, then click "generate". three files will be written to your specified folder(s): n AN1385 - application note 18/35 firmware file name, psdsoft express will extract firmware from that file only between the specified start and stop addresses, and ignore firmware outside of the start and stop addresses. click on 'merge mcu firmware' in the main flow diagram. first you will notice that psdsoft express will "fit" your psd configuration to the silicon architecture of the psd. after the fitting process is complete, you'll see this screen: in the left column are the individual psd memory segment chip-selects (fs0, fs1, etc). the next column shows the logic equations for selection of each internal psd memory segment. these equations reflect the choices that you made while defining psd internal chip-select equations in an earlier step. in the mid- dle of the screen are hexadecimal start and stop addresses that psdsoft express has filled in for you based on your chip-select equations. on the right are fields to enter (browse) the mcu firmware files. 19/35 AN1385 - application note select 'intel hex record' for 'record type' as shown. now scroll down to the bottom until you see csboot0. use the 'browse' button and select the firmware file, psdexpress\examples\isp_hc11.hex. now do the same for csboot1. the screen should look like this: this specification places firmware in secondary psd flash memory segments csboot0 and csboot1. ps- dsoft express will extract any firmware that lies inside the file isp_hc11.hex between mcu addresses c000 and dfff and place it in psd memory segment csboot0. it will also extract any firmware that lies inside the file isp_hc11.hex between mcu addresses e000 and efff and place it in psd memory seg- ment csboot1. click ok to generate the composite object file, simple11.obj. note: the file isp_hc11.hex will run on the dk68hc11 development board from st, and display some messages on the lcd screen to indicate a successful isp session. for your own prototype project, create a simple firmware file that configures your system hardware and performs rudimentary tasks to check out your new hardware. in this design example, there are 16 kbytes available in secondary flash memory segments csboot0 and csboot1, which is more than enough for this simple boot and test code. after your new hardware is proven, you can add more code to the boot area to for advanced tasks, including iap of main psd flash memory. AN1385 - application note 20/35 programming the psd the simple11.obj file can be programmed into the psd by one of three ways: C the st flashlink jtag cable, which connects to the pc parallel port. C the st psdpro device programmer, which also uses the pc parallel port. C third-party programmers, from stag, needhams, and others. see our web site at www.wafes- cale.com for compatible third-party programmers. programming with flashlink connect the flashlink jtag-isp cable to your pc parallel port. click the 'jtag-isp' box in the design flow window. you should see the following screen: this window enables you to perform jtag-isp operations and also offers a loop back test for your flashlink cable. if this is your first use, test your flashlink cable and pc parallel port by clicking the 'hw setup' button, then click 'looptest' button and follow the directions. now let's define our jtag-isp environment. for this example project, psdsoft express should have filled in the folder and filename of the object file to program, the psd device, and the jtag-isp operation, as shown in the screen above. for this design example, we have chosen to use all six jtag-isp pins (in- stead of four). be sure to indicate "6 pins" as shown above to achieve minimum jtag-isp programming times (refer to application note an1153 for details on six pins vs. four) to begin programming, connect the jtag cable to the target system, power-up the target system, and click 'execute' on the jtag screen. the log window at the bottom of the jtag screen shows the progress. programming should just take a few seconds. there are optional choices available when the 'properties.." button is clicked. one choice includes setting 21/35 AN1385 - application note the state of all non-jtag psd i/o pins during jtag-isp operations (make them inputs or outputs). the default state of all non-jtag psd i/o pins is "input", which is fine for this design example. the other choice allows you to specify a usercode value to compare before any jtag-isp operation starts. this is typically used in a manufacturing environment (see on-screen description for details). after jtag-isp operations are completed, you can save the jtag setup for this programming session to a file for later use. to do so, click on the 'save' button. to restore the setup of a different previous session, click the 'browse..' button. programming with psdpro connect the psdpro device programmer to your pc parallel port per the installation instructions. click on the 'conventional programmer' box in the design flow window. you will see this: if this is the first use of the psdpro, you'll need to designate the psdpro as the device connected to your parallel port. to do this, click the "set h" icon button at the top of the "conventional programming" screen and choose the psdpro. then click on the 'h test' icon to perform a test of the psdpro and the pc par- allel port. after testing, place a psd913f2 into the socket of the psdpro and click on the 'program' icon (the simple11.obj file is automatically loaded when this process is invoked). the messaging of psdsoft will inform you when programming is complete. note: this window is also helpful even if you do not have a psdpro device programmer. use this window to see where the "merge mcu firmware" utility has placed 68hc11 firmware within physical memory of the psd. for this design example, click on the secondary psd flash memory icon "fb" in the tool bar, then scroll to the end of segment csboot1 to see the 68hc11 reset vector at absolute mcu addresses fffeh and ffffh, which translates to direct physical addresses 23ffeh and 23fffh respectively. to see how all of your 68hc11 absolute addresses translated into direct physical psd memory addresses, see the report that psdsoft generates under 'reports' from the main toolbar, then select 'address trans- lation report'. within the report, the 'start' and 'stop' addresses are the absolute mcu system addresses that you have specified. the addresses shown in square brackets are the direct physical addresses used by a device programmer to access the memory elements of the psd in a linear fashion (a special device programming mode that the mcu cannot access). AN1385 - application note 22/35 second design example - iap with memory paging the second design example builds upon the first by adding memory paging which allows the 68hc11 to access all of the memory resident on the psd913f2. the physical connections between the 68hc11 and psd913f2 do not change, but the memory map, psd page register definition, and some psd chip-select equations do change. a psd913f2 is still used in this example, but the other members of the easy flash family may be used instead with minor changes. see the psd9xxf data sheet for a comparison of family members. memory map the psd913f2 provides 128 kbytes of main flash memory, 32 kbytes of secondary flash memory, and 2 kbytes sram. we'll use all of the main flash memory, all of the sram, and one half of the secondary flash memory (16 kbytes) to hold the iap bootloader code, 68hc11 interrupt vectors, and common firm- ware functions. we'll allocate the remaining 16 kbytes of secondary flash memory for general data stor- age. since the 68hc11 cannot address more than 64 kbytes of address space directly, we will use paging (or banking) to take full advantage of the 162 kbytes of total memory on the psd913f2. the psd has a built- in page register for this purpose. many mcu cross-compilers support paging today. examine the memory map in figure 6. at power on or reset, the 68hc11 boots from secondary flash memory, runs a checksum of the main flash memory, programs and verifies main psd flash memory (iap) via the uart if necessary, then execution jumps to main flash memory. the 68hc11 can access all of flash memory now since it is paged across four memory pages. notice that the memory map is divided into two areas. the upper memory (8000 to ffff) is a common area, meaning the mcu will have access to this region regardless of what memory page is active. this common area holds the following: C 68hc11 reset vector and initialization routines C 68hc11 interrupt vectors and service routines C i/o and memory page management routines C sram variables and sram stack C iap loader code C anything else that must be accessible no matter what memory page is selected. the lower half of memory (0000 to 7fff) is the region that will be "paged" or "banked". this paged area of 32 kbytes allows the 68hc11 to address large amounts of memory. we'll place all 128 kbytes of main psd flash memory across four 32k-byte pages (memory pages 0 through 3). the remaining half of the secondary psd flash memory will be placed on memory page 4 and used for general data. to make this division of the memory map possible (that is, common upper half, paged lower half), the 68hc11 initialization firmware must move the internal 68hc11 sram and 68hc11 registers from their default location of 0000 hex, to the new location of 8000 hex, as shown in figure 6. there is a special register within the 68hc11 (the init register) that facilitates this move. the init register must be written with the value 88 hex within the first 64 mcu oscillator clocks after power up. see the 68hc11 reference manual from motorola. this move is necessary to "clean-up" the memory map, meaning that the entire region from 0000 - 7fff is now free to use for paging, once these internal mcu locations are moved up and out of the way to 8000 hex. also note that the common area (non-paged) had to be located in the upper half of memory (8000h - ffff) because the 68hc11 boots from high memory (fffe). keep in mindthat all of the psd page register bits are zero at power-up and after a system reset. 23/35 AN1385 - application note figure 6. memory map for second design - iap with memory paging note: 1. 68hc11 boots from the reset vector stored here. 2. iap loader code gets programmed here by jtag-isp or a convetional programmer tool. ffffh ai04450 cs_lcd, ext chip sel for lcd rs0, 2k bytes sram 68hc11 regs/ram csiop, psd control regs csboot1 8k bytes secondary flash csboot0 8k bytes secondary flash nothing mapped fs1 16k bytes main flash fs0 16k bytes main flash nothing mapped c000h a800h 8300h - 83ffh a000h - a7ffh 8400h 8200h - 82ffh 8000h - 81ffh 7fffh 4000h 3fffh 0000h (note 1) (note 2) page 0 bfffh 9fffh paged region common region (any page) fs3 16k bytes main flash fs2 16k bytes main flash page 1 fs5 16k bytes main flash fs4 16k bytes main flash page 2 fs7 16k bytes main flash fs6 16k bytes main flash page 3 8000h 8000h 8000h 0000h 0000h 0000h csboot3 8k bytes secondary flash csboot2 8k bytes secondary flash page 4 0000h 4000h AN1385 - application note 24/35 psdsoft express design entry to implement the memory map with paging techniques shown in figure 6, invoke psdsoft express, open the project "simple11" from the first design example. now pull down the menu 'project' from the top of the screen, and select 'save as'. for this second design example, save the first project under the new name "page11". now click on the pin definition box in the design flow diagram. click ok to get to the page reg- ister definition screen since no pin assignment needs to be changed for this second design. there are a total of five memory pages used in figure 6, so you will need to define three psd page register bits for paging (23 = 8), as two psd page register bits are not enough (22 = 4). to do so, click on pgr0, pgr1, and pgr2 as shown below. click 'next >>'. the chip-select equations for psd sram (rs0), psd control registers (csiop), and the external lcd mod- ule (cslcd) do not change from the first design example. only chip-selects for main psd flash memory and some of the secondary psd flash memory need to be changed for this second design because they are affected by paging. 25/35 AN1385 - application note define the internal psd memory chip-select signals to implement the memory map of figure 66. the fol- lowing illustrates how the chip-selects will look when you enter their definitions: fs0: fs1: fs2: fs3: continue defining fs4 and fs5 on memory page 2, and fs6 and fs7 on memory page 3 per the memory map in figure 6. the chip-selects for csboot0 and csboot1 did not change from the first design example because no page number was specified in their definition. this means they will appear to the 68hc11 on any memory page, as indicated in figure 6. AN1385 - application note 26/35 next, define chip-selects as shown below for the secondary psd flash memory csboot2 and csboot3 to match figure 6: csboot2: csboot1: click 'done' after defining all chip-selects. you should now see the main flow diagram. click the 'merge mcu firmware' box in the design flow diagram. you will see an informational dialog box pop up that indicates memory paging is used and that the firmware file(s) you specify should be set up to handle paging. click ok, since for this design example the firmware that would run the iap process is not paged. it resides in csboot0 and csboot1 of the psd and is active on all pages (independent of what mem- ory page is selected). click the "more info" button in step 1 of the merge firmware screen if your future 68hc11 system design will execute code from different pages, and that code will be programmed into the psd with a device pro- grammer (for example, you specify filename(s) in this screen that go to psd memory segments that are 27/35 AN1385 - application note paged). now specify the name of the 68hc11 firmware file to place into the secondary flash memory segments csboot0 and csboot1. this can be any firmware file that you create to implement iap with paging. no firm- ware filename needs to be designated for the main psd flash memory segments (fs0 - fs7) since they will be programmed by the 68hc11 during iap. click ok in the merging screen to create a composite object file for programming. you are now ready to program the psd913f2. see the section entitled programming the psd on page 20. AN1385 - application note 28/35 third design example - advanced iap with paging & swapping the third design example adds enhanced iap features. the physical connections between the 68hc11 and psd913f2 do not change, but the memory map, psd page register definition, and some psd chip- select definitions do change. the focus of this enhanced design is to get the most use out of the 64 kbyte address space that the 68hc11 can access directly. this means swapping the iap loader code out of the memory map after iap is complete, and replacing it with application code, leaving the maximum amount of address space available for the application. swapping out the iap loader code not only frees up ad- dress space for application code, it also allows the software designer the option of having two sets of in- terrupt vectors and associated service routines; one set during iap, and a different set after iap during the normal application. in addition, this swapping technique allows the iap loader code itself to be download- ed in the field if necessary while the 68hc11 operates out of main psd flash memory. memory map the memory map has two basic configurations: boot-up/iap and normal application. see figures 7 and 8. memory map configuration at boot-up or reset figure 7. memory map for third design at boot-up or reset note: 1. 68hc11 boots from the reset vector stored here. 2. iap loader code gets programmed here by jtag-isp or a convetional programmer tool. figure 7 shows the memory map at system power-on or at system reset. the swap bit is defined as one of the eight internal psd page register bits. the swap bit is an example of how the page register bits can ffffh ai04451 cs_lcd, ext chip sel for lcd rs0, 2k bytes sram 68hc11 regs/ram csiop, psd control regs csboot1 8k bytes secondary flash csboot0 8k bytes secondary flash nothing mapped fs1 16k bytes main flash fs0 16k bytes main flash nothing mapped c000h a800h 8300h - 83ffh a000h - a7ffh 8400h 8200h - 82ffh 8000h - 81ffh 7fffh 4000h 3fffh 0000h (note 1) (note 2) page 0 bfffh 9fffh paged region common region (any page) fs3 16k bytes main flash fs2 16k bytes main flash page 1 fs5 16k bytes main flash fs4 16k bytes main flash page 2 fs7 16k bytes main flash fs6 16k bytes main flash page 3 8000h 8000h 8000h 0000h 0000h 0000h csboot3 8k bytes secondary flash csboot2 8k bytes secondary flash page 4 0000h 4000h swap bit = 0 (default). mcu boots from csboot0/csboot1. mcu runs checksum of main flash. mcu downloads main flash if needed. mcu sets swap bit = 1. 29/35 AN1385 - application note be implemented for uses other than memory paging. here's what the 68hc11 does upon power-up or re- set: C boot from secondary flash memory (csboot0/csboot1) at address fffeh C perform a checksum of main flash memory C download main flash memory from host computer if needed (iap) and validate contents C set the swap bit to logic one. note that all psd page register bits are cleared to zero at power-up and a reset. memory map configuration after iap and during normal application setting the swap bit in the psd page register swaps the location of the secondary flash memory seg- ments csboot0/csboot1 (which were in the mcu boot area) with a segment of main flash memory, fs7, as shown in figure 8. (note: fs7 is 16 kbytes and csboot1 & 2 are 8 kbytes each - thus the 2:1 ratio). this swapping action is implemented by qualifying the chip-selects for csboot0, csboot1, and fs7 with the psd page register bit named swap. figure 8. - memory map, enhanced design, normal operation figure 8 shows the memory map after iap is complete and after the 68hc11 has set the swap bit to logic one. at this point, the 68hc11 can download new iap loader code to secondary flash memory segments csboot0/csboot1 if needed. another one of the eight psd page register bits is used for logic in this design, ffffh ai04452 cs_lcd, ext chip sel for lcd rs0, 2k bytes sram 68hc11 regs/ram csiop, psd control regs nothing mapped fs1 16k bytes main flash fs0 16k bytes main flash nothing mapped c000h a800h 8300h - 83ffh a000h - a7ffh 8400h 8200h - 82ffh 8000h - 81ffh 7fffh 4000h 3fffh 0000h page 0 bfffh 9fffh paged region common region (any page) fs3 16k bytes main flash fs2 16k bytes main flash page 1 fs5 16k bytes main flash fs4 16k bytes main flash page 2 fs6 16k bytes main flash page 3 8000h 8000h 8000h 0000h 0000h 0000h csboot3 8k bytes secondary flash csboot2 8k bytes secondary flash page 4 0000h 4000h - swap bit = 1. - now the mcu boot area (c000h-ffffh)is occupied by main flash memory instead of secondary flash memory. - mcu can download new iap loader code into csboot0/csboot1 if desired after setting the unlock bit = 1. - mcu can use csboot2/csboot3 for general data storage. fs7 16k bytes main flash csboot1 8k bytes 2nd flash if unlock = 1 csboot1 8k bytes 2nd flash if unlock = 1 swap AN1385 - application note 30/35 named 'unlock'. the 68hc11 must first set the unlock bit to logic one before updating iap loader code. in this final configuration, the 68hc11 has available: * 16 kbytes of main flash memory in the common area (c000h-ffffh) * 112 kbytes of main flash memory across four pages of lower memory (0000h-7fffh) * 2 kbytes of sram in addition to the sram that resides on the 68hc11 * 16 kbytes of secondary flash memory for general data storage on memory page 4 * 16 kbytes of secondary flash memory for iap loader code. each time this 68hc11 system gets reset or goes through a power-on cycle, the psd presents the mem- ory map of figure 7 to the mcu, and the boot sequence is repeated. note: when the 68hc11 is executing code from the secondary psd flash memory (csboot0 and csboot1), and then it sets the swap bit, it is very important that the 68hc11 firmware linker has set up "syn- chronized" code in the segment of main psd flash memory (fs7) that replaces the secondary psd flash memory. this is necessary to create seamless mcu operation during the actual swap of memory since the 68hc11 is completely unaware that there is a swap going on. it just continues to fetch opcodes and operands during the memory swap. this requires that the operands and opcodes in main psd flash mem- ory that follow the mcu instructions that actually set the swap bit in the secondary psd flash memory, are continuos. this means that the remainder of the instructions to complete setting the swap bit is present in main psd flash memory so there is continuos operation throughout the memory swapping process. psdsoft express design entry to implement the advanced memory maps of figures 7 and 8, invoke psdsoft express, open the project "page11" from the second design example. now pull down the menu 'project' from the top of the screen, and select 'save as'. for this third design example, save the second project under the new name "advanc11". now click on the 'pin definition' box in the design flow diagram. click "ok" to get to the 'page register definition' screen since no pin assignment needs to be changed for this third design. 31/35 AN1385 - application note you will need to define two additional psd page register bits to be used for logic instead. the three page register bits that were used for memory paging in the second design example stay just as they are. define page register bits for logic, as shown below, labeling one bit "swap" and the other bit "unlock": click 'next >>'. the chip-select equations for psd sram (rs0), psd control registers (csiop), and the external lcd mod- ule (cslcd), and most of the internal psd memory segments do not change from the second design exam- ple. only three chip-selects need to change for the third design because they are affected by memory swapping.: main psd flash memory segment fs7, and two secondary psd flash memory segments csboot0 and csboot1. AN1385 - application note 32/35 these three internal memory chip-selects must be qualified with the page register bit "swap", as shown below. the secondary psd memory segments, csboot0 and csboot1, must be additionally qualified by "unlock" to prevent the mcu from inadvertently writing to iap boot and loader code. also notice the new page number assignments. the following illustrates how the chip-selects will look when you enter their definition: fs7: 33/35 AN1385 - application note csboot0: csboot1: notice that these psd physical memory segments can appear in more that one mcu address space de- pending on the memory page and the "swap" and "unlock" qualifiers. now the memory maps of figures 7 and 8 have been implemented. click 'done' and should see the main flow diagram. click the "merge mcu firmware" box in the design flow diagram. you will see an informational dialog box pop up that indicates memory paging is used and that the firmware file(s) you specify should be set up to handle paging. click ok, since for this design example the firmware that would run the iap process ex- ample is not paged. when the mcu is executing iap code, it resides in csboot0 and csboot1 of the psd and is active on all pages (independent of what memory page is selected). click the "more info" button in step 1 of the merge firmware screen if your future 68hc11 system design will execute code from different pages, and that code will be programmed into the psd with a device pro- grammer (for example, you specify filename(s) in this screen that go to psd memory segments that are paged). now specify the name of the 68hc11 firmware file to place into the secondary flash memory segments csboot0 and csboot1. this can be any firmware file that you create to implement iap with paging and swapping. no firmware filename needs to be designated for the main psd flash memory segments (fs0 AN1385 - application note 34/35 - fs7) since they will be programmed by the 68hc11 during iap. click "ok" in the merging screen to create a composite object file for programming. you are now ready to program your psd913f2. see the section entitled programming the psd on page 20. conclusion these examples are just three of an endless number of ways to configure the easy flash psd for your system. concurrent memories with a built-in programmable decoder at the segment level offer excellent flexibility. also, as you have seen with the swap and unlock bits, the page register bits do not have to be used just for paging through memory. the ability to enhance your system does not require any physical connection changes, as everything is configured internal to the psd. and finally, the jtag channel can be used for isp anytime, and anywhere, with no participation from the mcu. all of these features are cross-checked under the psdsoft express development environment to minimize your effort to design a flash memory 68hc11 system capable of isp and iap. references 1. psd9xxf family data sheet 2. application note an1153 for detailed use of the jtag channel 35/35 AN1385 - application note for current information on psd products, please consult our pages on the world wide web: www.st.com/psd if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.psd@st.com (for application support) ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com |
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