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1 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory data sheet: ACD82112 12 ports 10/100 fast ethernet switch rev.1.3.4. i last update: march 20, 1999 subject to chnage acd confidential material for acd authorized customer use only. no reproduction or redistribution without acds prior permission. please check acds website for update information before starting a design web site: http://www.acdcorp.com or contact acd at: email: support@acdcorp.com tel: 408-433-9898 fax: 408-545-0930 advanced communication devices
2 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory table of contents page 1 general description 3 2 main features 3 3 system block diagram 3 4system description 4 5 functional description 4 6 interface description 11 7 register description 16 8 pin description 25 9 timing description 28 10 electrical specifications 34 11 packaging 35 appendix a1 address resolution logic 36 (the built-in arl) section
3 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory buffer queue manager lookup engine (2k mac addr.) led controller bist handler arl acd80800 (11k mac addr.) (optional) mib acd80900 (optional) arl interface sram mac-0 mac-1 mac-10 mac-11 sram interface mib interface pmd/ phy-0 pmd/ phy-1 pmd/ phy-10 pmd/ phy-11 mx dmx buffer buffer buffer buffer buffer buffer buffer fifo fifo fifo fifo fifo fifo fifo fifo ACD82112 3. system block diagram 1. general description the ACD82112 is a single chip implementation of a 12 port 10/100 ethernet switch system intended for ieee 802.3 and 802.3u compatible networks. the device in- cludes 12 independent 10/100 macs. each mac inter- faces with an external pmd/phy device through a stan- dard mii interface. speed can be automatically config- ured through the mdio or the optional cpu uart. each port can operate at either 10mbps or 100mbps, in half- duplex or full-duplex mode. the core logic of the ACD82112, implemented with patent pending basiq (bandwidth assured switching with intelligent queu- ing) technology, can simultaneously process 12 asyn- chronous 10/100mbps traffics. the queue manager in- side the ACD82112 provides the capability of routing traffic with the same order of sequence, without any packet loss. a complete 12 port 10/100 switch can be built with the use of the ACD82112, 10/100 phy and sram. the mac addresses space can be expanded from the built- in 2k to 11k by using acds external arl ( address resolution logic) , the acd80800. advanced network management features can be supported with the use of acds mib (management information base, acd80900) chip. 2. main features 12 - 10/100 mbps, auto-sensing ports with mii in- terface full / half duplex operation 2.4 gbps aggregated throughput true non-blocking switch architecture shared buffer with starvation control algorithm built-in storage of 2,048 mac addresses automatic source address learning optional back-pressure (half duplex) flow control 802.3x pause frame (full duplex) flow control store-and-forward switch mode port based vlan support uart type cpu management interface supports up to 11k addresses with external arl controller, the acd80800 rmon and snmp support with external mib con- troller, the acd80900 status leds: link, speed, full/half duplex, trans- mit, receive, collision and frame error reversible mii option for cpu and expansion port interface, with hardware based flow control wire speed forwarding rate 388-pin pbga package (including 36 thermal ground pins at the center) 3.3v power, 3.3v i/o with 5v tolerance
4 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory preamble sfd da sa type/len data fcs 4. system description the ACD82112 is a single chip implementation of a 12- port fast ethernet switch. together with external sram devices and transceiver devices, it can be used to build a complete 10/100 mbps fast ethernet switch. each individual port can be either auto-sensing or manually selected to run at 10 mbps or 100 mbps speed rates and under full or half-duplex mode. the ACD82112 ethernet switch contains three major functional blocks: the media access controller (mac), the queue manager, and the lookup engine. there are 12 independent macs within the ACD82112. the mac controls the receiving, transmitting, and de- ferring process of each individual port, in accordance to the ieee 802.3 and 802.3u standards. the mac logic also provides framing, fcs checking, error handling, status indication and flow control functions. each mac interfaces with an external transceiver through a stan- dard mii interface. the device utilizes acds proprietary basiq (band- width assured switching with intelligent queuing) tech- nology. it is a technology to efficiently enforce the first- in-first-out rule of ethernet bridge-type devices. the technology enables a true non-blocking frame switch- ing operation at wire speeds for a high throughput and high port density ethernet switch. the on-chip lookup engine implements a 2,048 entries mac address lookup table. it maps each destination address into a corresponding port. each mac address is automatically learned by the lookup engine after an error-free frame is received. therefore, the ACD82112 alone can be used to build a complete fast ethernet switch with up to 2,048 host connections . (for detailed information about the built-in arl, please re- fer to the acd80800 data sheet.) for workgroup or backbone switches, the ACD82112 can support more mac addresses per port through the use of an external arl chip, the acd80800. the ACD82112 has a glueless arl interface that allows a supporting chip (acd80800) to provide up to 11k mac addresses per switch. system designers can also use this arl interface to implement a vendor-specific ad- dress resolution algorithm. the ACD82112 provides management support through its mib (management information base) interface. the mib interface can be used to monitor all traffic activities of the switch system. the supporting chip (the acd80900) provides a full set of statistical counters to support both snmp and rmon network management functions. system designers can also use the mib in- terface to implement vendor-specific network manage- ment functionality. among the 12 mii interfaces, 5 of them can be config- ured as reversed mii, to connect directly with stand- alone mac controller devices. a mac in the ACD82112 can be viewed logically as a phy device if it is config- ured as the reversed mii interface. reversed mii is in- tended for a cpu network interface, or an expansion port interface. the system cpu can access various registers inside the ACD82112 through a serial cpu management in- terface. the cpu can configure the switch by writing into the appropriate registers, or retrieve the status of the switch by reading the corresponding registers. the cpu can also access the registers of external trans- ceiver (phy) devices through the cpu management interface. 5. functional description the mac controller performs transmit, receive, and de- fer functions, in accordance to the 802.3 and 802.3u specification. the mac logic also handles frame detec- tion, frame generation, error detection, error handling, status indication and flow control functions. under full- duplex mode, the flow control is implemented in compli- ance with ieee 802.3x standard. frame format the ACD82112 assumes that the received data packet will have the following format: where, preamble is a repetitive pattern of 1010. of any length with nibble alignment. the sfd (start frame delimiter) is defined as an octet pattern of 10101011. the da (destination address) is a 48-bit field that speci- fies the mac address of the destined dte. if the first bit of da is 1, the ACD82112 will treat the frame as a broadcast/multicast frame and will forward the frame to all ports within the source ports vlan except the source port itself or bpdu address.
5 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory the sa (source address) is a 48-bit field that contains the mac address of the source dte that is transmitting the frame to the ACD82112. after a frame is received with no error, the sa is learned as the ports mac ad- dress. the type/len field is a 2-byte field that specifies the type (dix ethernet frame) or length (ieee 802.3 frame) of the frame. the ACD82112 does not process this in- formation. the data is the encapsulated information within the ethernet packet. the ACD82112 does not process any of the data information in this field. the fcs (frame check sequence) is a 32-bit field of crc (cyclic redundancy check) value based on the destination address, the source address, the type/length and the data field. the ACD82112 will verify the fcs field for each frame. the procedure for computing fcs is described in the section fcs calculation. start of frame detection when a ports mac is idle, assertion of the rxdv in the mii interface will cause the port to go into the re- ceive state. the mii presents the received data in 4-bit nibbles that are synchronous to the receive clock (25mhz or 2.5mhz). the ACD82112 will convert this data into a serial bit stream, and attempt to detect the occurrence of the sfd (10101011) pattern. all data prior to the detection of sfd are discarded. once sfd is detected, the following frame data are forwarded and stored in the buffer of the switch. frame reception under normal operating conditions, the ACD82112 ex- pects a received frame to have a minimum inter frame gap (ifg). the minimum ifg required by the device is 64 bt. in the event the ACD82112 receives a packet with ifg less than 64 bt, the ACD82112 does not guarantee to be able to receive the frame. the packet will be dropped if the ACD82112 cannot receive the frame. the device will check all received frames for errors such as symbol error, fcs error, short event, runt, long event, jabber, etc. frames with any kind of error will not be forwarded to any port. preamble bit processing the preamble bit in the header of each frame will be used to synchronize the mac logic with the incoming bit stream. the minimum length of the preamble is 0 bits and there is no limitation on the maximum length of pre- amble. after the receive data valid signal rxdv is as- serted by the external phy device, the port will wait for the occurrence of the sfd pattern (10101011) and then start a frame receiving process. source address and destination address after a frame is received by the ACD82112, the em- bedded destination address and source address are retrieved. the destination address is passed to the lookup table to find the destination port. the source address is automatically stored into the address lookup table. for applications that uses an external arl, the ACD82112 will disable the internal lookup table and pass the da and sa to the external arl for address lookup and learning. during the receive process, the lookup engine will at- tempt to match the destination address with the addresses stored in the address table. if there is a match found, a link between the source port and the destination port is then established. if an external arl is used, the ACD82112 indicates the presence of 48-bit da through the status line of the arl interface. the external arl will use the value of da for address comparison and return a result of the lookup to the ACD82112. frame data frame data are transparent to the ACD82112. the ACD82112 will forward the data to destination port(s) without interpreting the content of the frame data field. fcs calculation each port of the ACD82112 has a crc checking logic to verify if the received frame has a correct fcs value. a wrong fcs value is an indication of a fragmented frame or a frame with frame bit error. the method of calculating the crc value is using the following polyno- mial, g(x) = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 as a divider to divide the bit sequence of the incoming frame, beginning with the first bit of the destination ad- dress field, to the end of the data field. the result of the
6 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory calculation, which is the residue after the polynomial division, is the value of the frame check sequence. this value should be equal to the fcs field appended at the end of the frame. if the value does not match the fcs field of the frame, the frame bit error led of the port will be turned on once and the packet will be dropped. illegal frame length during the receiving process, the mac will monitor the length of the received frame. legal ethernet frames should have a length of not less than 64 bytes and no more than 1518 bytes. if the carrier-sense signal of a frame is asserted for less than 76 bt, the frame is flagged with short event error. if the length of a frame is less then 512 bt, the frame is flagged with runt error. in order to support an application where extra byte length is required, an extra long frame option is provided. when the extra long frame option is enabled (table-7.24, bit- 7) , only frames longer than 1530 bytes are marked with a long event error. frame length is measured from the first byte of da to the last byte of fcs. frame filtering frames with any kind of error will be filtered. types of error include code error (indicated by assertion of rxer signal), fcs error, alignment error, short event, runt, and long event. any frame heading to its own source port will be fil- tered. when external arl is used, the filtering decision will be made by the arl. the ACD82112 will act in accor- dance with the arls direction. if the spanning tree support option is enabled, frames containing da equal to any reserved bridge manage- ment group address specified in table 3.5 of the ieee 802.1d will not be forwarded to any ports, except port- 11, which may receive bpdu frames . if spanning tree support is not enabled, frames with da equal to the reserved group address for pbdu will be broadcasted to all ports in the same vlan of the source port. jabber lockup protection if a receiving port is active continuously for more than 50,000 bit times, the port is considered to be jabbering. a jabbering port will automatically be partitioned from the switch system in order to prevent it from impairing the performance of the network. the partitioned port will be re-activated as soon as the offending signal dis- continues. excessive collision in the event that there are more than 16 consecutive collisions, the ACD82112 will reset the counter to zero and retransmit the packet. this implementation insures there is no packet loss even under channel capture situation. however, the ACD82112 has an option to drop the packet on excessive collisions. when this option is enabled (table-7.24, bit-11) , the frame will be dropped after 16 consecutive collisions. if a port has encountered 256 consecutive collisions, it is assumed to be non-functional and will be partitioned. the partitioned port will not receive any frame. it will still transmit new frames, but without retry after encounter- ing a collision. the partition port will be released once a new frame is transmitted without incurring a collision, which indicates that, the port has regained normal func- tions. false carrier events if the signal in the mii interface is asserted but the re- ceive data valid (rxdv) signal is not, and the rxd shows 1110 at the same time, the port is considered to have a false carrier event. if a port has more than two con- secutive false carrier events, the port will automatically be partitioned from the switch system. the partitioned port will be re-activated if it has been idling for 33,000 bt or it has received 500 bits of valid data after a mini- mum 64 bt idle period. frame forwarding if the first bit of the destination address is 0, the frame is handled as a unicast frame. the destination address is passed to the address resolution logic; which re- turns a destination port number to identify which port the frame should be forwarded to. if the address reso- lution logic cannot find any match for the destination address, the frame will be treated as a frame with un- known da. the frame will be processed in one of two ways. if the option flood-to-all-port is enabled, the switch will forward the frame to all ports within the same vlan of the source port, except the source port itself. if the option is not enabled, the frame will be forwarded to the dumping port of the source port vlan only. the dump- ing port is determined by the vlan id of the source port. if the source port belongs to multiple vlans, a frame with unknown da will then be forwarded to mul- tiple dumping ports of the vlans.
7 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory if the first bit of the destination address is a 1, the frame is handled as a multicast or broadcast frame. the ACD82112 does not differentiate a multicast packet from a broadcast packet except for the reserved bridge man- agement group address, as specified in table 3.5 of ieee 802.1d standard. the destination ports of a broad- cast frame are all ports within the same vlan except the source port itself. the order of all broadcast frames with respect to the unicast frames is strictly enforced by the ACD82112. frame t ransmission the ACD82112 transmits all frames in accordance to ieee 802.3 standard. the ACD82112 will send the frames with a guaranteed minimum interframe gap of 96 bt, even if the received frames have an ifg less than the minimum requirement. before the transmit pro- cess is started, the mac logic will check if the channel has been silent for more than 64 bt. within the 64 bt silent window, the transmission process will defer on any receiving process. if the channel has been silent for more than 64 bt, the mac will wait an additional 32 bt before starting the transmit process. in the event that the carrier sense signal is asserted by the mii dur- ing the wait period, the mac logic will generate a jam signal to cause a forced collision. the mac logic will abort the transmit process if a colli- sion is detected through the assertion of the col signal of the mii. re-transmission of the frame is scheduled in accordance to the ieee 802.3s truncated binary expo- nential backoff algorithm. if the transmit process has encountered 16 consecutive collisions, an excessive collision error is reported, and the ACD82112 will try to re-transmit the frame, unless the drop-on-excessive- collision option of the port is enabled. it will first reset the number of collisions to zero and then start the trans- mission after a 96 bit time of inter frame gap. if drop- on-excessive-collision is enabled, the ACD82112 will not try to re-transmit the frame after 16 consecutive colli- sions. if collision is detected after 512 bt of the trans- mission, a late collision error will be reported, but the frame will still be retransmitted after proper backoff time. frame generation during a transmit process, frame data is read out from the memory buffer and is forwarded to the destination ports phy device in nibbles. 7 bytes of a preamble signal (10101010) will be generated first followed by the sfd (10101011), and then the frame data and 4 bytes of fcs are sent out at last. shared buffer all ports of the ACD82112 work in store-and-forward mode so that all ports can support both 10mbps and 100mbps data speeds. the ACD82112 utilizes a global memory buffer pool, which is shared by all ports. the device has a unique architecture that inherits the ad- vantage of both output buffer-based and input buffer- based switches. the output buffer-based switches store the received data only once into the memory, and hence has a short latency. whereas input buffer based switches typically have more efficient flow control. starvation control scheme all frames received by the ACD82112 will be stored into a common physical frame buffer pool. in order to make sure all ports have fair access to the network, a buffer allocation scheme (starvation control) is used to prevent active ports from occupying all the buffers and starve off the less active ports. the frame buffer pool is divided into 3 portions: the reserved poo l, the common pool and the extra pool , as shown in figure-5.1: extra pool (shared by all full duplex ports with flow control capability) reserved pool (dedicated to each port) common pool (shared by all the ports) ~50% ~80% figure-5.1: buffer partition
8 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory the reserved pool guarantees each port will have a fair network access possibility, even under the worst traffic congestion situation. it takes about 50% of the total buffer and is evenly allocated to each port as its dedicated buffer slot. the dedicated slot is not shared with other ports. the common pool provides a deep buffer for the busy ports (e.g. server port) to serve multiple low speed ports (e.g. client port) simultaneously. it helps to avoid head-of-line blocking. it takes about 30% of the total buffer and is shared by all ports. it stores the con- gested traffics before the flow control mechanism is triggered. the extra pool is reserved only for ports with pause frame based flow control capacity. it takes the remain- ing 20% of the total buffer. it is used to minimize the chance of frame dropping by buffering for the latency of the pause frame based flow control scheme. it is used only after a flow control mechanism is triggered. flow control scheme flow control activity is triggered when the buffer utilization exceeds certain thresholds specified by the dedicated registers. register-10 is used to specify the upper and the lower thresholds of the reserved buffer slot for each port. register-11 is used to specify the upper and the lower thresholds of the broadcast queue. under full duplex operation, if the buffer utilization of a port has exceeded the upper threshold of the reserved buffer slot, and the common pool has been used up, a max-pause-frame ( a pause frame with a maximum time interval of ffffh) will be sent to the sending party to stop it from sending new frames. if pause- frame based flow control is not enabled at that port, the frame will be dropped. once a max-pause-frame is sent, if the utilization of the reserved buffer slot of the port drops below the lower threshold, a mini- pause-frame (a pause frame with minimum time interval of 0) will be sent to the linking party to enable new frame transmission. under half duplex operation, if the buffer utilization of a port has exceeded the upper threshold of the reserved buffer slot, and the common pool has been used up, the port will execute back-pressure based flow control by sending a jam pattern on each incom- ing frame. if backpressure flow control of the port is not enabled, the frame will be dropped. if the broadcast flow control is enabled (when bit-13 of register-25 is set), flow control will be triggered when the broadcast queue is longer than the upper thresh- old specified by register-11 . all full duplex ports with pause-frame capability will send a max-pause-frame to its linking party. all half-duplex ports with backpressure capability will jam incoming frames. after a max-pause-frame is sent, and if the broadcast queue is shorten below the lower threshold specified by register-11 , a mini-pause-frame will be sent to release the hold on transmission. vlan support (registers 23 & 24) the ACD82112 can support up to 4 port-based security vlans. each port of the ACD82112 can be assigned to up to four vlan. on power up, every port is assigned to vlan-i as the default vlan. frames from the source port will only be forwarded to destination ports within the same vlan domain. a broadcast/multicast frame will be forwarded to all ports within the vlan(s) of the source port. a unicast frame will be forwarded to the destination port only if the destination port is in the same vlan as the source port. otherwise, the frame will be treated as a frame with unknown da. each vlan can be assigned with a dedicated dumping port. multiple vlans can also share a dumping port. unicast frames with unknown destination addresses will be forwarded to the dumping port of the source port vlan. security vlan can be disabled by setting the corre- sponding bit in the system configuration register (bit 8 of register 16, see table 7.15 ). when security vlan is disabled, each vlan becomes a leaky vlan and is equivalent to a broadcast domain. four dumping ports of four different leaky vlans can be grouped together to form a fat pipe uplink (for example, port 0, port 1, port 2, and port 3 can be grouped to form an 800 mbps uplink port). when multiple dumping ports are grouped as a single pipe, each port has to be assigned to one and only one vlan. a unicast frame with a matched da will be forwarded to any destination port, even if the vlan id is different. all unmatched da packets will be forwarded to the designated dumping port of the source port vlan. the broadcast and multicast packets will only be forwarded to the ports in the same vlan of the source port. therefore, a 200 to 800 mbit/s pipe can be established by carefully grouping the dumping ports, and directly connecting with any segmentation switches. dumping port each vlan can be assigned with a dedicated dumping port. multiple vlans can share a dumping port. each dumping port can be used for an up-link connection or for a dte connection. that is, the dumping port can be used to connect the switch with a computer repeater
9 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory hub, a workgroup switch, a router, or any type of inter- connection device compliant with ieee 802.3 standard. ACD82112 will direct the following frames to the dump- ing port: a frame with a unicast destination address that does not match with any ports source address within the vlan of the source port. a frame with a broadcast/multicast destination ad- dress*. *see spanning tree support if the device is configured to work under flood-to-all- port mode (register 25, bit 8) , the frames with un- known da will be forwarded to all the ports in the vlan(s) of the source port except the source port itself. mode of operation (register 18) all ports of the ACD82112 can work in half duplex mode or full duplex mode. if auto-negotiation is enabled, the mode is determined by the phy device. otherwise, the mode is assigned by the full duplex mode indication/ assignment register. spanning t ree support the ACD82112 supports the spanning tree protocol. when spanning tree support is enabled (register-16 bit 1, see table 7.15) , frames from the cpu port (port 11) having a da value equal to the reserved bridge management group address for bpdu will be forwarded to the port specified by the cpu. frames from all other ports with a da value equal to the reserved group ad- dress for bpdu will be forwarded to the cpu port if the port is in the same vlan of the cpu port. port 11 is designed as the default cpu port. when spanning tree support is disabled, all reserved group addresses for bridge management is treated as broadcast address, with the exception of the reserved multicast addresses for pause frame specified by ieee802.3x. every port of the ACD82112 can be set to block-and- listen mode through the cpu interface. in this mode, incoming frames with a da value equal to the reserved group address for bpdu will be forwarded to the cpu port. incoming frames with all other da values will be dropped. outgoing frames with a da value equal to the group address for bpdu will be forwarded to the at- tached phy device; all other outgoing frames will be filtered. queue management each port of the ACD82112 has its own individual trans- mission queue. all frames coming into the ACD82112 are stored into the shared memory buffer, and are lined up in the transmission queues of the corresponding destination port. the order of all frames, unicast or broadcast, is strictly enforced by the ACD82112. the ACD82112 is designed with a non-blocking switching architecture. it is capable of achieving wire speed for- warding rates and can handle maximum traffic loads. mii interface the mac of each port of the ACD82112 interfaces with the ports phy device through the standard mii inter- face. for reception, the received data (rxd) is sampled by the rising edge of the receive clock (rxclk). as- sertion of the receive data valid (rxdv) signal will cause the mac to look for the start of sfd. for transmission, the transmit data enable (txen) signal is asserted when the first preamble nibble is sent on the transmit data (txd) lines. the transmit data are clocked out by the falling edge of the transmit clock (txclk). phy management the ACD82112 supports phy device management through the serial mdio and mdc signal lines. the ACD82112 can continuously poll the status of the phy devices through the serial management interface, with- out cpu intervention. the ACD82112 will also config- ure the phy capability field to ensure proper operation of the link. the ACD82112 also enables the cpu to access any registers in the phy devices through the cpu interface. the id of the phy device can start from either 1 or 4, depending on the setting of bit-10 of register-25. reversed mii interface five of the ACD82112s 12 ports can be configured with reversed mii interface. reversed mii behaves as a phy mii: the txclk, col, rxd<3:0>, rxclk, rxdv, crs signals (names specified by ieee 802.3u) be- come output signals of the ACD82112, and the txer, txd<3:0>, txen, rxer signals (names specified by ieee 802.3u) become input signals of the ACD82112. the reversed mii interface enables an external mac device to be connected directly with the ACD82112.
10 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory sram interface the ACD82112 requires the use of asram, or flow- through ssram as a memory buffer. each read or write cycle takes up to 20 ns. for asram, the access time should be at or less than 12 ns. for ssram, the speed should be at or higher than 100mhz. the sram inter- face contains a 52-bit data bus, a 17-bit address bus and 4 chip-select signals. cpu interface the ACD82112 does not require any microprocessor for operation. initialization and most configurations can be done with the pull-up or pull-down of designated hard- ware pins. a cpu interface is provided for a micropro- cessor to access the control registers and status regis- ters. the microprocessor can send a read command to retrieve the status of the switch, or send a write com- mand to configure the switch through the interface. the interface is a commonly used uart type interface. the cpu interface can also be used to access the registers inside each phy device connected with the ACD82112. arl interface the ACD82112 has a built-in mac address storage for up to 2,048 source addresses. if more than 2,048 ad- dresses are needed, an external arl (e.g. acd80800) can be used to expand the address space to 11k en- tries. the external arl is connected through the arl inter- face (table-7.24, bit-9) . it can tap the value of da out of the memory interface bus, and execute a lookup pro- cess to map the value of the da into a port number. it can also learn the sa values embedded in the received frames. the value of sa is used to build the address lookup table inside the acd80800. mib interface traffic activities on all ports of the ACD82112 can be monitored through the mib interface. through the mib interface, a mib device can view the frames transmitted from or received by any port. therefore, the mib de- vice can maintain a record of traffic statistics for each port to support network management. since all received data are stored into the memory buffer, and all transmit- ted data are retrieved from the memory buffer, the data of the activities can also be captured from the memory interface data bus. the status of each data transaction between the ACD82112 and the sram is displayed by dedicated status signal pins of the ACD82112. led interface the ACD82112 provides a wide variety of led indica- tors for simple system management. the update of the led is completely autonomous and merely requires low speed ttl or cmos devices as led drivers. the sta- tus display is designed to be flexible to allow the system designer to choose those indicators appropriate for the specification of the equipment. there are two led control signals, ledvld0 and ledvld1. they are used to indicate the start and end of the led data signal presented on nled0-nled3. the ledclk signal is a 2.5mhz clock signal. the ris- ing edge of ledclk should be used to latch the led data signal into the led driver circuitry. the led data signals contain lnk, xmt, rcv, col, err, fdx and spd, which represent link status, transmit sta- tus, receive status, collision indication, frame error indication, full duplex operation and operational speed status respectively. these status signals are sent out sequentially from port 11 to port 0, once every 50ms. for details about the timing diagrams of the led sig- nals, refer to the chapter of timing description life pulse the ACD82112 continuously sends out life pulses to the wchdog pin when it is operating properly. in a catastrophic event, the ACD82112 will not send the life pulse to cause the external watchdog circuitry to time- out and reset the switch system.
11 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory 6. interface description mii interface (mii) the ACD82112 communicates with the external 10/100 ethernet transceivers through standard mii interface. the signals of mii interface are described in table-6.1 : for mii interface, signal pxrxdv, pxrxer and pxrxd0 through pxrxd3 are sampled by the rising edge of pxrxclk. signal pxtxen, and pxtxd0 through pxtxd3 are clocked out by the falling edge of pxtxclk. the detailed timing requirement is described in the chap- ter of timing description ports 0, 1, 2, 3 and 11 can be configured as reversed mii ports ( register 28 , the reversed mii enable regis- ter). these ports, when configured as normal mii, have the same characteristics as all other mii ports. how- ever, when configured as reversed mii interface, they will behave logically like a phy device, and can inter- face directly with a mac device. the signal of reversed mii interface are described by table-6.2 : *collision indication for half-duplex, receive-not-ready for full duplex only. for reversed mii interface, signal pxrxdvr, and pxrxd0r through pxrxd3r are clocked out by the falling edge of pxrxclkr. signal pxtxenr, and pxtxd0r through pxtxd3r can be sampled by the falling edge or rising edge of pxtxclkr, depends on the setting of bit 9 of register-16 . the timing behavior is described in the chapter of timing description. phy management interface all control and status registers of the phy devices are accessible through the phy management interface. the interface consists of two signals: mdc and mdio, which are described in table-6.3 . frames transmitted on mdio has the following format ( table-6.4 ): table-6.1: mii interface signals name type description pxcrs i carrier sense pxrxdv i receive data valid pxrxclk i receive clock (25/2.5 mhz) pxrxerr i receive error pxrxd0 i receive data bit 0 pxrxd1 i receive data bit 1 pxrxd2 i receive data bit 2 pxrxd3 i receive data bit 3 pxcol i collision indication pxtxen o transmit data valid pxtxclk i transmit clock (25/2.5 mhz) pxtxd0 o transmit data bit 0 pxtxd1 o transmit data bit 1 pxtxd2 o transmit data bit 2 pxtxd3 o transmit data bit 3 table-6.2: reversed mii interface signals name type description pxcrsr o carrier sense pxrxdvr i transmit data valid pxrxclkr o transmit clock (25/2.5 mhz) pxrxerr i transmit-not-ready pxrxd0r i transmit data bit 0 pxrxd1r i transmit data bit 1 pxrxd2r i transmit data bit 2 pxrxd3r i transmit data bit 3 pxcolr* o collision indication/ receive-not-ready* pxtxenr o receive data valid pxtxclkr o receive clock (25/2.5 mhz) pxtxd0r o receive data bit 0 pxtxd1r o receive data bit 1 pxtxd2r o receive data bit 2 pxtxd3r o receive data bit 3 table-6.3: phy management interface signals name type description mdc o phy management clock (1.25mhz) mdio i/o phy management data table-6.4: mdio format operation pre st op phy-id reg-ad ta data idle write 11 01 01 aaaaa rrrrr 10 dd z read 11 01 10 aaaaa rrrrr z0 dd z
prior to any transaction, the ACD82112 will output thirty- two bits of 1 as preamble signal. after the preamble, a 01 signal is used to indicate the start of the frame. for a write operation, the device will send a 01 to sig- nal a write operation. following the 01 write signal will be the 5 bit id address of the phy device and the 5 bit register address. a 10 turn around signal is then fol- lowed. after the turn around, the 16 bit of data will be written into the register. after the completion of the write transaction, the line will be left in a high impedance state. for a read operation, the ACD82112 will output a 10 to indicate read operation after the start of frame indica- tor. following the 10 read signal will be the 5-bit id address of the phy device and the 5-bit register ad- dress. then, the ACD82112 will cease driving the mdio line, and wait for one bit time. during this time, the mdio should be in a high impedance state. the ACD82112 will then synchronize with the next bit of 0 driven by the phy device, and continue on to read 16 bits of data from the phy device. the system designer can set the id of the phy devices as 1 for port 0, 2 for port 1, and 12 for port 11, when the phyid option (bit-10 of register-25) is set to 0. if the phyid option is set to 1, the corresponding phy id should set to 4 through 15. the detailed timing re- quirements on phy management signals are described in the chapter of timing description. cpu interface the ACD82112 includes a cpu interface to enable an external cpu to access the internal registers of the ACD82112. the signal used in the cpu is uart. the baud rate can be from 1200 bps to 76800 bps. the ACD82112 automatically detects the baud rate for each command, and returns the result at the same baud rate. the signals in cpu interface are described in table- 6.5 . a command sent by cpu comes through the cpudi line. the command consists of 8 octets. command frames transmitted on cpudi have the following format ( table-6.6 ): the byte order of data in all fields follows the big-endian convention, i.e. most significant octet first. the bit or- der is the least significant order first. the command octet specifies the type of the operation. bit 2 and bit 3 of the command octet is used to specify the device id of the chip. they are set by bit 16 and bit 17 of the register 25 at power on strobing. the address octet specifies the type of the register. the index octet speci- fies the index of the register in a register array. for write operation, the data field is a 3-octet value to specify what to write into the register. for read operation, the data field is a 3-octet 0 as padded data. the checksum value is an 8-bit value of exclusive-or of all octets in the frame, starting from the command octet. for each valid command heading to it, the ACD82112 will always send a response. response from the ACD82112 is sent through the cpudo line. response frames sent by the ACD82112 has the following format ( table-6.7 ): the command octet specifies the type of the response. the result octet specifies the result of the execution. the result field in a response frame is defined as: 00 for no error 01 for checksum 10 for address incorrect 11 for mdio waiting timeout for response to a read operation, the data field is a 4- octet value to indicate the content of the register. for response to a write operation, the data field is 32 bits of 0. the checksum value is an 8-bit value of exclusive-or of all octets in the response frame, starting from the command octet. table-6.5: cpu interface signals name type description cpudi i cpu data input cpudo o cpu data output cpuirq o cpu interrupt request table-6.6: cpudi format operation command address index data che cksum write 0010xx11 8-bit 8-bit 24-bit 8-bit read 0010xx01 8-bit 8-bit 24-bit 8-bit table-6.7: switch response format response command result data che cksum write 00100011 8-bit 24-bit 8-bit read 00100001 8-bit 24-bit 8-bit 12
13 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory cpuirq is used to notify the cpu that some special status has been encountered by the ACD82112, like port partition, fatal system error, etc. by clearing the appropriate bit in the interrupt mask register, one can stop the specific source from generating an interrupt request. reading the interrupt source register retrieves the source of the interrupt request and clears the inter- rupt source register. sram interface all received frames are stored into the shared memory buffer through the sram interface. when the destina- tion port is ready to transmit the frame, data is read from the shared memory buffer through the sram in- terface. the signals in sram interface are described in table-6.8 . data is written into the sram or read from the sram in 52-bit wide words. the data is a 48 bit wide value and the control is a 4 bit wide value. addr specifies the address of the word, and data contains the content of the word. bit 0 ~ 47 of data bus are used to pass 48- bit frame data. bit 48 are used to indicate the start and end of a frame. bit 49~51 are used to indicate the length of the data shown on first 48 bit of data bus. noe and nwe are used to control the timing of read or write operation respectively. ncsx selects the sram chip corresponding to the word address. the timing requirement on sram access is described in timing description (chapter-9). arl interface the arl interface provides a communication path be- tween the ACD82112 and an arl device, which can provide up to 11k of address lookup. as the ACD82112 receives a frame, the destination address and source address of the frame are displayed on the arldo data lines for the external arl device. after the external arl finds the corresponding destination port, it returns the result through the arldix lines to the ACD82112. the timing requirement on arl signals is described in chap- ter 9, timing description. table-6.9 shows the asso- ciated signals in arl interface. the data signal is tapped from the data bus of the sram interface. since all data of the received frames will be written into the shared memory through the data bus, the bus can be used to monitor occurrences of da and sa values, indicated by the status signal of arlstat. therefore, arld0 through arld51 are the same sig- nals of data0 through data51. the arldir1 and arldir0 are used to indicate the direction of data on the arldo bus: 00: idle 01: for receiving data 10: for transmitting data 11: header the arlsync is used to indicate port 0 is driving the data bus. since the bus is pre-allocated in time divi- sion multiplexing manner, the arl device can deter- mine which port is driving the data bus. the arlstat are used to indicate the status of the data shown on the first 48 bit of data bus. the 4-bit status is defined as: 0000 - idle 0001 - first word (da) 0010 - second word (sa) 0011 - third through last word 0100 - filter event 0101 - drop event 0110 - jabber 0111 - false carrier/deferred transmission* 1000 - alignment error/single collision* 1001 - flow control/multiple collision* 1010 - short event/excessive collision * 1011 - runt/late collision * 1100 - symbol error 1101 - fcs error table-6.8: sram interface name type description data0 - data51 i/o memory data bus addr0 - addr16 o memory address bus noe o output enable, low active nwe o write enable, low active ncs0 - ncs3 o chip select signals, low active. table-6.9: arl interface signals name type description arldo0-rldo51 o arl data output, shared with data 0 - data 51 arldir1-arldir0 o arl data direction indicator 00 for idle 01 for receive 10 for transmit 11 for control arlsync o arl port synchronization arlstat0- arlstat3 o arl data state indicator arlclk o arl clock arldi0 - arldi3 i arl data input arldiv i arl input data valid
14 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory 1110 - long event 1111 - reserved * note: error type depends on the port is receiving or transmitting. arldix is used to receive the lookup result from the external arl. the result is returned by external arl device through the arldix lines. returned data can be sampled by the rising or the falling edges of arlclk, depending on the setting of bit-18 of register-25. the arl results have the following format: where sid is a 5-bit id of the source port (0 - 11) rslt is a 2-bit result, defined as: 00 - reserved 01 - matched 10 - not matched 11 - forced discard did is a 5-bit id of the destination port (0 - 11) the start of each arl result is indicated by assertion of arldiv signal. led interface the signals in the led interface is described in table- 6.10 : the status of each port is displayed on the led inter- face for every 50ms. ledvld0 and ledvld1 are used to indicate the start and end of the led data. led data is clocked out by the falling edge of ledclk, and should be sampled by the rising edge of ledclk. led data of port-11 are clocked out first, followed by port-10 down to port-0. all led signals are low active. sid rslt did table-6.10: led interface signals name type description signal group 1 signal group 2 ledvld0 o led signal valid #0 1 0 ledvld1 o led signal valid #1 0 1 nledclk o 2.5 mhz led clock - - nled0 o dual purpose indicator address learning status frame error indicator nled1 o dual purpose indicator full duplex indication collision indication nled2 o dual purpose indicator port speed (1=10mbps,0=100mbps) receiving activity nled3 o dual purpose indicator link status transmit activity
15 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory table-6.12: other interface name type description clk50 i 50 mhz clock input nreset i hardware reset wchdog o watch dog life pulse signal vdd - 3.3 v power vss - ground configuration interface the default values of certain register bits are set by internal pull-high/pull-low with 75k ohm resistors. these default values can be overwritten by external pull-high/ pull-low of certain designated pins with 4.7k ohm exter- nal resistors. table-6.11 lists all the available pins. the meanings of the register bits are described in the chap- ter of register description. other interface ( table-6.12 ) the clk50 should come from a clock oscillator, with 0.01% (100 ppm) accuracy. the nreset is a low-active hardware reset pin. asser- tion of this pin will cause the ACD82112 to go through the power-up initialization process. all registers are set to their default value after reset. the wchdog pin is used to handle exceptional cases. a normal working ACD82112 sends out continuous life pulses from the wchdog pin, which can be monitored by an external watchdog circuit. if no life pulse is de- tected , the external watchdog circuit may force reset of the switch system. it is a safeguard against unfore- seeable situations. the vdd is 3.3v power supply. the vss is power ground. table-6.11: configuration interface pin name register # bit # default p7txd0 0 p7txd1 1 p7txd2 2 p7txd3 3 p6txd0 4 p6txd1 5 p6txd2 6 p6txd3 7 ledclk 8 ledvld0 9 ledvld1 10 nled3 11 nled2 12 nled1 13 nled0 14 p5txd0 15 p5txd1 16 p5txd2 17 p5txd3 18 p0txd0 0 p0txd1 1 p0txd2 2 p0txd3 3 p1txd0 4 p1txd1 5 p1txd2 6 p1txd3 7 p2txd3 3 0 p2txd2 1 1 20, inside the internal arl see table-7.25 see table-7.30 30 25
16 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory 7. register description registers in the ACD82112 are used to define the op- eration mode of various function modules of the switch controller and the peripheral devices. default values at power-on are defined by the factory. the management cpu (optional) can read the content of all registers and modify some of the registers to change the operation mode. table-7.0 lists all the registers inside the switch controller. intsrc register (register 1) the intsrc register indicates the source of the inter- rupt request. before the cpu starts to respond to an interrupt request, it should read this register to find out the interrupt source. this register is automatically cleared after each read. table-7.1 lists all the bits of this regis- ter. syserr register (register 2) the syserr register indicates the presence of sys- tem errors. it is automatically cleared after each read. table-7.2 lists all kind of system error. table-7.0: register list address name type size depth description 0 reserved r - - - 1 intsrc r 8 bit 1 interrupt source 2 syserr r 12 bit 1 system error 3 par r 12 bit 1 port partition indication 4 pmerr r 12 bit 1 phy management error 5 act r 12 bit 1 port avtivity 6 reserved r - - - 7 reserved r - - - 8 sal r/w 24 bit 1 source address, bit 23:0 9 sah r/w 24 bit 1 source address, bit 47:24 10 uth r/w 16 bit 1 unicast threshold 11 bth r/w 16 bit 1 broadcast threshold 12 maxl r/w 16 bit 1 fcs of max-pause-frame, bit 15:0 13 maxh r/w 16 bit 1 fcs of max-pause-frame, bit 31:16 14 minl r/w 16 bit 1 fcs of min-pause-frame, bit 15:0 15 minh r/w 16 bit 1 fcs of min-pause-frame, bit 31:16 16 syscfg r/w 16 bit 1 system configuration 17 intmsk r/w 8 bit 1 interrupt mask 18 speed r/w 12 bit 1 port s peed 19 link r/w 12 bit 1 port link 20 nfwd r/w 12 bit 1 port forward disable 21 nbp r/w 12 bit 1 port back pressure disable 22 nport r/w 12 bit 1 port disable 23 pvid r/w 4 bit 12 port vlan id 24 vpid r/w 5 bit 4 vlan dum ping port 25 poscfg r/w 20 bit 1 power-on-strobe configuration 26 pause r/w 12 bit 1 port pause frame disable 27 dplx r/w 12 bit 1 port duplex mode 28 rvsmii r/w 5 bit 1 reversed mii selection 29 npm r/w 12 bit 1 port phy management disable 30 errmsk r/w 8 bit 1 error mask 31 clkadj r/w 4 bit 1 arl clock delay adjustment 32-43 phyreg r/w 16 bit * pointer to registers in phy devices 44-63 reserved r/w - - - table-7.1: intsrc register bit description default 0 system initialization completed 1 system error occurred 2 port partition occurred 3 arl interrupt 4 5 6 7 reserved 0
17 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory p ar register (register 3) the par register indicates the presence of the parti- tioned ports and the port id. a port can be automati- cally partitioned if there is a consecutive false carrier event, an excessive collision or a jabber. this register is automatically cleared after each read. table-7.3 lists all the bits of this register. table-7.2: syserr register bit description default 0 bist failure indication 1 2 3 4 5 6 7 8 0 reserved table-7.3: par register bit description default 0 0 - port 0 is not partitioned. 1 - port 0 is partitioned. 1 0 - port 1 is not partitioned. 1 - port 1 is partitioned. 2 0 - port 2 is not partitioned. 1 - port 2 is partitioned. 3 0 - port 3 is not partitioned. 1 - port 3 is partitioned. 4 0 - port 4 is not partitioned. 1 - port 4 is partitioned. 5 0 - port 5 is not partitioned. 1 - port 5 is partitioned. 6 0 - port 6 is not partitioned. 1 - port 6 is partitioned. 7 0 - port 7 is not partitioned. 1 - port 7 is partitioned. 8 0 - port 8 is not partitioned. 1 - port 8 is partitioned. 9 0 - port 9 is not partitioned. 1 - port 9 is partitioned. 10 0 - port 10 is not partitioned. 1 - port 10 is partitioned. 11 0 - port 11 is not partitioned. 1 - port 11 is partitioned. 0 pmerr register (register 4) the pmerr register indicates the presence of phys that have failed to respond to the phy management command issued through the mdio line. this register is automatically cleared after each read. table-7.4 de- scribes all the bit of this register. act register (register 5) the act register indicates the presence of transmit or receive activities of each port since the register was last read. this register is automatically cleared after each read. table-7.5 describes all the bits of this regis- ter. table-7.4: pmerr register bit description default 0 0 - port 0's phy responded 1 - port 0s phy failed to respond 1 0 - port 1s phy responded 1 - port 1s phy failed to respond 2 0 - port 2s phy responded 1 - port 2s phy failed to respond 3 0 - port 3s phy responded 1 - port 3s phy failed to respond 4 0 - port 4s phy responded 1 - port 4s phy failed to respond 5 0 - port 5s phy responded 1 - port 5s phy failed to respond 6 0 - port 6s phy responded 1 - port 6s phy failed to respond 7 0 - port 7s phy responded 1 - port 7s phy failed to respond 8 0 - port 8s phy responded 1 - port 8s phy failed to respond 9 0 - port 9s phy responded 1 - port 9s phy failed to respond 10 0 - port 10s phy responded 1 - port 10s phy failed to respond 11 0 - port 11s phy responded 1 - port 11s phy failed to respond 0
18 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory sal & sah register (register 8,9) the sal and sah registers together contain the com- plete source address for pause frame generation. sal contains the least significant 24 bit of the mac address. sah contains the most significant 24 bit of the mac address. the default locally managed source address for pause frame generation is feh-ffh-ffh-ffh-ffh- ffh a. table-7.8 and table-7.9 describes all the bits of these two registers. uth register (register 10) the uth register contains the unicast buffer thresholds for each port. when the upper threshold is exceeded, the mac may generate a max-pause-frame. when the lower threshold is crossed, the mac may generate a mini-pause-frame. table-7.10 describes each bit in this register. * note: the default value is related to the memory size specified by bit[6:5] of register 25. bth register (register 1 1) the bth register contains the broadcast queue buffer threshold for each port. when the upper threshold is exceeded, the mac may generate a max-pause-frame. when the lower threshold is crossed, the mac may generate a mini-pause-frame. table-7.11 describes each bit in this register. minl & minh register (register 12,13) the minl and minh registers together contain the 32- bit frame check sequence (fcs) of the mini-pause- frame. minl contains the least significant 16 bit of the fcs. minh contains the most significant 16 bit of the fcs. the default fcs value assumes the default source address for the mini-pause-frame. table-7.12 and table- 7.13 describe all the bits of these two registers. table-7.8: sal register bit description default 7:0 bit 47:40 of the switchs mac address. feh 15:8 bit 39:32 of the switchs mac address. 23:16 bit 31:24 of the switchs mac address. ffh table-7.9: sah register bit description default 7:0 bit 23:16 of the switchs mac address. 15:8 bit 15:8 of the switchs mac address. 23:16 bit 7:0 of the switchs mac address. ffh table-7.10: uth register bit description default* 7:0 lower threshold of unicast utilization. 4,8,16,32 15:8 higher threshold of unicast utilization. 8,24,64,144 table-7.5: act register bit description default 0 0 - port 0 no activity 1 - port 0 has activity 1 0 - port 1 no activity 1 - port 1 has activity 2 0 - port 2 no activity 1 - port 2 has activity 3 0 - port 3 no activity 1 - port 3 has activity 4 0 - port 4 no activity 1 - port 4 has activity 5 0 - port 5 no activity 1 - port 5 has activity 6 0 - port 6 no activity 1 - port 6 has activity 7 0 - port 7 no activity 1 - port 7 has activity 8 0 - port 8 no activity 1 - port 8 has activity 9 0 - port 9 no activity 1 - port 9 has activity 10 0 - port 10 no activity 1 - port 10 has activity 11 0 - port 11 no activity 1 - port 11 has activity 0 table-7.11: bth register bit description default 7:0 lower threshold of broadcast queue 16 15:8 higher threshold of broadcast queue 48 table-7.12: minl register bit description default 7:0 bit 31:24 of the mini-pause-frames fcs 89 15:8 bit 23:16 of the mini-pause-frames fcs o3 table-7.13: minh register bit description default 7:0 bit 15:18 of the mini-pause-frames fcs d7 15:8 bit 7:0 of the mini-pause-frames fcs a9
19 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory maxl & maxh register (register 14,15) the maxl and maxh registers together contain the 32-bit frame check sequence (fcs) of the max-pause- frame. maxl contains the least significant 16 bit of the fcs. maxh contains the most significant 16 bit of the fcs. the default fcs value assumes the default source address for the max-pause-frame. table-7.14 and table- 7.15 describe all the bits of these two registers. syscfg register (register 16) the syscfg register specifies certain system con- figurations. the system options are described in the chapter of function description. table-7.16 describes all the bit of this register. intmsk register (register 17) the intmsk register defines the valid interrupt sources allowed to assert interrupt request pin. table-7.17 lists all the bits of this register. table-7.17: intmsk register bit description default 0 enable "system initialization completion" to interrupt 1 enable "internal system error" to interrupt 2 enable "port partition event" to interrupt 3 enable "internal arl" to interrupt 4 arl interupt enable 5 6 7 1 reserved table-7.16: syscfg register bit description default 0 0 - bist enabled; 1 - bist disabled. 1 0 - spanning tree support disabled; 1 - spanning tree support enabled 2 0 - rising edge of rxclk to latch rxd for mii 1 - falling edge of rxclk to latch rxd for mii 3 reserved. 4 reserved. 5 0 - wait for cpu. 1 - system ready to start *this bit is used by the cpu when bit-15 of register-25 is set as "0" (for system with control cpu). the system w ill wait for cpu to set this bit. 6 0 - phy management not completed 1 - phy management completed. *this bit is used by the cpu when bit-15 of register-25 is set as "0" (for system with a control cpu). the mac will not start until this bit is set sy the cpu. 7 0 - watchdog function enabled. 1 - watchdog function disabled. 8 0 - secure vlan checking rule enforced. 1 - leaky vlan checking rule enforced. 9 0 - rising edge of rxclk to latch data. 1 - falling edge of rxclk to latch data. *for reversed mii port only. 10 0 - late back-pressure scheme disabled 1 - late back-pressure scheme enabled *when enabled, the mac will generate back- pressure only after reading the first bit of da 11 0 - special handling of broadcast frames disabled 1 - special handling of broadcast frames enabled *when enabled, all broadcast frames from non-cpu port are forwarded to the cpu port only, and all broadcast frames from the cpu port are forwarded to all other ports. 12 software reset: "1" to start a system reset to innitialize all state machines. 13 hardware reset: "1" to stop the life pulse on the watchdog pin, which in turn will trigger the external watchdog circuitry to reset the whole system. 14 reserved 15 reserved 0 table-7.14: maxl register bit description default 7:0 bit 31:24 of the max-pause-frames fcs 0d 15:8 bit 23:16 of the max-pause-frames fcs 68 table-7.15: maxh register bit description default 7:0 bit 15:8 of the max-pause-frames fcs d8 15:8 bit 7:0 of the max-pause-frames fcs d0
20 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory speed register (register 18) the speed register specifies or indicates the speed rate of each port. it is read-only, unless the bit-12 of register-25 is set (through pos to disable automatic phy management). at read-only mode, it indicates the speed achieved through phy management. at the write- able mode, the control cpu will be able to assign speed rate for each port. table-7.18 describes all the bit of this register. link register (register 19) the link register specifies or indicates the link status of each port. it is read-only, unless bit-12 of register-25 is set (through pos, to disable automatic phy man- agement). at read-only mode, it indicates the result achieved by phy management. at write-able mode, the control cpu can assign link status for each port. table- 7.19 describes all the bit of this register. nfwd register (register 20) the nfwd register defines the forwarding mode of each port. under forwarding mode, a port can forward all frames. under block-and-listen mode, a port will not forward regular frames, except bpdu frames. if the spanning tree algorithm discovers redundant links, the control cpu will allow only one link remaining in for- warding mode and force all other links into block-and- listen mode. setting the associated bit in this register will put the port into block-and-listen mode. table-7.20 table-7.18: speed register bit description default 0 0 - port 0 at 10mbps 1 - port 0 at 100mbps 1 0 - port 1 at 10mbps 1 - port 1 at 100mbps 2 0 - port 2 at 10mbps 1 - port 2 at 100mbps 3 0 - port 3 at 10mbps 1 - port 3 at 100mbps 4 0 - port 4 at 10mbps 1 - port 4 at 100mbps 5 0 - port 5 at 10mbps 1 - port 5 at 100mbps 6 0 - port 6 at 10mbps 1 - port 6 at 100mbps 7 0 - port 7 at 10mbps 1 - port 7 at 100mbps 8 0 - port 8 at 10mbps 1 - port 8 at 100mbps 9 0 - port 9 at 10mbps 1 - port 9 at 100mbps 10 0 - port 10 at 10mbps 1 - port 10 at 100mbps 11 0 - port 11 at 10mbps 1 - port 11 at 100mbps 0 table-7.19: link register bit description default 0 0 - port 0 link not established 1 - port 0 link established 1 0 - port 1 link not established 1 - port 1 link established 2 0 - port 2 link not established 1 - port 2 link established 3 0 - port 3 link not established 1 - port 3 link established 4 0 - port 4 link not established 1 - port 4 link established 5 0 - port 5 link not established 1 - port 5 link established 6 0 - port 6 link not established 1 - port 6 link established 7 0 - port 7 link not established 1 - port 7 link established 8 0 - port 8 link not established 1 - port 8 link established 9 0 - port 9 link not established 1 - port 9 link established 10 0 - port 10 link not established 1 - port 10 link established 11 0 - port 11 link not established 1 - port 11 link established 0 table-7.20: nfwd register bit description default 0 0 - port 0 in forwarding state. 1 - port 0 in block-and-listen state. 1 0 - port 1 in forwarding state. 1 - port 1 in block-and-listen state. 2 0 - port 2 in forwarding state. 1 - port 2 in block-and-listen state. 3 0 - port 3 in forwarding state. 1 - port 3 in block-and-listen state. 4 0 - port 4 in forwarding state. 1 - port 4 in block-and-listen state. 5 0 - port 5 in forwarding state. 1 - port 5 in block-and-listen state. 6 0 - port 6 in forwarding state. 1 - port 6 in block-and-listen state. 7 0 - port 7 in forwarding state. 1 - port 7 in block-and-listen state. 8 0 - port 8 in forwarding state. 1 - port 8 in block-and-listen state. 9 0 - port 9 in forwarding state. 1 - port 9 in block-and-listen state. 10 0 - port 10 in forwarding state. 1 - port 10 in block-and-listen state. 11 0 - port 11 in forwarding state. 1 - port 11 in block-and-listen state. 0
21 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory describes all the bit of this register. nbp register (register 21) the nbp register defines back-pressure flow control capability for each port. table-7.21 describes all the bit of this register. nport register (register 22) the nport register is used to isolate ports from the network. setting the associated bit in this register will stop a port from receiving or transmitting any frame. table-7.22 describes all the bits of this register. pvid register (register 23) the pvid registers assign vlan ids for each port. there are 12 pvid registers, one for each port. a pvid consists of 4 bits, each corresponding to one of the 4 vlans. a port can belong to more than one vlan at the same time. table-7.23 describes all the bits of this register. vpid register (register 24) the vpid registers specify the dumping port for each vlan. there are 4 vpid 5-bit registers, one for each vlan. a valid vpid are 0 through 11 (other values are reserved and should not used). table-7.24 describes all the bits of this register. table-7.21: nbp register bit description default 0 0 - port 0 back-pressure scheme enabled 1 - port 0 back pressure scheme disabled 1 0 - port 1 back-pressure scheme enabled 1 - port 1 back pressure scheme disabled 2 0 - port 2 back-pressure scheme enabled 1 - port 2 back pressure scheme disabled 3 0 - port 3 back-pressure scheme enabled 1 - port 3 back pressure scheme disabled 4 0 - port 4 back-pressure scheme enabled 1 - port 4 back pressure scheme disabled 5 0 - port 5 back-pressure scheme enabled 1 - port 5 back pressure scheme disabled 6 0 - port 6 back-pressure scheme enabled 1 - port 6 back pressure scheme disabled 7 0 - port 7 back-pressure scheme enabled 1 - port 7 back pressure scheme disabled 8 0 - port 8 back-pressure scheme enabled 1 - port 8 back pressure scheme disabled 9 0 - port 9 back-pressure scheme enabled 1 - port 9 back pressure scheme disabled 10 0 - port 10 back-pressure scheme enabled 1 - port 10 back pressure scheme disabled 11 0 - port 11 back-pressure scheme enabled 1 - port 11 back pressure scheme disabled 0 table-7.22: nport register bit description default 0 0 - port 0 enabled 1 - port 0 disabled 1 0 - port 1 enabled 1 - port 1 disabled 2 0 - port 2 enabled 1 - port 2 disabled 3 0 - port 3 enabled 1 - port 3 disabled 4 0 - port 4 enabled 1 - port 4 disabled 5 0 - port 5 enabled 1 - port 5 disabled 6 0 - port 6 enabled 1 - port 6 disabled 7 0 - port 7 enabled 1 - port 7 disabled 8 0 - port 8 enabled 1 - port 8 disabled 9 0 - port 9 enabled 1 - port 9 disabled 10 0 - port 10 enabled 1 - port 10 disabled 11 0 - port 11 enabled 1 - port 11 disabled 0 table-7.23: pvid register bit description default 0 0 - port not in vlan-i. 1 1 - port in vlan-i. 1 0 - port not in vlan-ii. 1 - port in vlan-ii. 2 0 - port not in vlan-iii. 1 - port in vlan-iii. 3 0 - port not in vlan-iv. 1 - port in vlan-iv. 0 table-7.24: vpid re g isters (4 registers) bit description default 4:0 dumping port id for vlan-1 "00000" 4:0 dumping port id for vlan-2 "11111" 4:0 dumping port id for vlan-3 dumping port 4:0 dumping port id for vlan-4 not defined
22 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory poscfg register (register 25) the poscfg register specifies a certain configuration setting for the switch system. the default values of this register can be changed through pull-up/pull-down of specific pins, as described in the configuration inter- face section of the interface description chapter. table-7.25 describes all the bit of this register. table-7.25: poscfg register bit description default 3:0 8 timing adjustment levels for sram read data latching: 0000 0000 - no delay 0001 - level 1 delay 0011 - level 2 delay 0101 - level 3 delay 0111 - level 4 delay 1001 - level 5 delay 1011 - level 6 delay 1101 - level 7 delay 1111 - level 8 delay 4 0 - absolute address mode: 1 row of 512k words, ncs2=a ddr17, ncs3=addr18 0 1 - chip-select address mode: 4 rows of 128k words, ncs[3:0] to select 4 rows of memory 6:5 sram size selection: 01 00 - 64k words 01 - 128k words 10 - 256k words 11 - 512k words 7 0 - long event defined as frame longer than 1518 byte. 1 1 - long event defined as frame longer than 1530 byte. 8 0 - frames with unknown da forwarded to the dumping port. 1 1 - frames with unknown da forwarded to all ports. 9 0 - internal arl selected (2k mac address entry). 0 1 - external arl selected (11k mac address entry). 10 0 - phy ids start from 1, range from 1 to 12. 1 1 - phy ids start from 4, range from 4 to 15. 11 0 - re-transmit after excessive collision. 0 1 - drop after excessive collision. 12 0 - automatic phy management enabled 0 1 - automatic phy management disabled: the control cpu need to update the speed, link, dplx and npause registers 13 reserved 0 14 0 - sysem errors will trigger software reset 0 1 - sysem errors will trigger hardware reset 15 0 - system start itself without a control cpu 0 1 - system start after system-ready bit in register-16 is set by the control cpu 17:16 2-bit device id for uart communication. the device responses only to uart commands with matching id 00 18 0 - rising edge of arlclk to latch arldi. 1 1 - falling edge of arlclk to latch arldi.
23 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory p ause register (register 26) the pause register defines the pause-frame based flow control capability of each port. table-7.26 describes all the bits of this register. dplx register (register 27) the dplx register specifies or indicates the half/full- duplex mode of each port. it is read-only, unless bit-12 of register-25 is set (through pos, to disable automatic phy management). at read-only mode, it indicates the result achieved by the phy management. at write-able mode, the control cpu can assign a half-duplex or full- duplex mode for each port. table-7.27 describes all the bits of this register. rvsmii register (register 28) the rvsmii register defines the reversed mii mode for each port. table-7.28 describes all the bits of this regis- ter. table-7.26: pause register bit description default 0 0 - port 0 pause-frame disabled 1 - port 0 pause-frame enabled 1 0 - port 1 pause-frame disabled 1 - port 1 pause-frame enabled 2 0 - port 2 pause-frame disabled 1 - port 2 pause-frame enabled 3 0 - port 3 pause-frame disabled 1 - port 3 pause-frame enabled 4 0 - port 4 pause-frame disabled 1 - port 4 pause-frame enabled 5 0 - port 5 pause-frame disabled 1 - port 5 pause-frame enabled 6 0 - port 6 pause-frame disabled 1 - port 6 pause-frame enabled 7 0 - port 7 pause-frame disabled 1 - port 7 pause-frame enabled 8 0 - port 8 pause-frame disabled 1 - port 8 pause-frame enabled 9 0 - port 9 pause-frame disabled 1 - port 9 pause-frame enabled 10 0 - port 10 pause-frame disabled 1 - port 10 pause-frame enabled 11 0 - port 11 pause-frame disabled 1 - port 11 pause-frame enabled 1 table-7.27: dplx register bit description default 0 0 - port 0 under half duplex mode 1 - port 0 under full duplex mode 1 0 - port 1 under half duplex mode 1 - port 1 under full duplex mode 2 0 - port 2 under half duplex mode 1 - port 2 under full duplex mode 3 0 - port 3 under half duplex mode 1 - port 3 under full duplex mode 4 0 - port 4 under half duplex mode 1 - port 4 under full duplex mode 5 0 - port 5 under half duplex mode 1 - port 5 under full duplex mode 6 0 - port 6 under half duplex mode 1 - port 6 under full duplex mode 7 0 - port 7 under half duplex mode 1 - port 7 under full duplex mode 8 0 - port 8 under half duplex mode 1 - port 8 under full duplex mode 9 0 - port 9 under half duplex mode 1 - port 9 under full duplex mode 10 0 - port 10 under half duplex mode 1 - port 10 under full duplex mode 11 0 - port 11 under half duplex mode 1 - port 11 under full duplex mode 0 table-7.28: rvsmii register bit description default 0 0 - port 0 under normal mii mode 1 - port 0 under reversed mii mode 1 0 - port 1 under normal mii mode 1 - port 1 under reversed mii mode 2 0 - port 2 under normal mii mode 1 - port 2 under reversed mii mode 3 0 - port 3 under normal mii mode 1 - port 3 under reversed mii mode 4 0 - port 11 under normal mii mode 1 - port 11 under reversed mii mode 0
24 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory npm register (register 29) the npm register indicates the automatic phy man- agement capability of each port. if a bit is set in this register, the corresponding speed, link, dplx, and pause status registers of a port will remain unchanged. table-7.29 describes all the bits of this register. errmsk register (register 30) the errmsk register defines certain errors as sys- tem errors . it is reserved for factory use only. table- 7.30 lists all the error masks specified by this register. table-7.29: npm register bit description default 0 0 - port 0s status update enabled 1 - port 0s status update disabled 1 0 - port 1s status update enabled 1 - port 1s status update disabled 2 0 - port 2s status update enabled 1 - port 2s status update disabled 3 0 - port 3s status update enabled 1 - port 3s status update disabled 4 0 - port 4s status update enabled 1 - port 4s status update disabled 5 0 - port 5s status update enabled 1 - port 5s status update disabled 6 0 - port 6s status update enabled 1 - port 6s status update disabled 7 0 - port 7s status update enabled 1 - port 7s status update disabled 8 0 - port 8s status update enabled 1 - port 8s status update disabled 9 0 - port 9s status update enabled 1 - port 9s status update disabled 10 0 - port 10s status update enabled 1 - port 10s status update disabled 11 0 - port 11s status update enabled 1 - port 11s status update disabled 0 table-7.30: errmsk register bit description default 0 1 2 3 4 5 6 7 reserved 1 clkadj register (register 31) the clkadj register defines the delay time of the arlclk relative to the transition edge of the data sig- nals. the arlclk provides reference timing for sup- porting chips, such as the acd80800 and the acd80900, which need to snoop the data bus for cer- tain activities. table-7.31 describes all the bits of this register. phyreg register (register 32-44) the phyreg refers to the registers residing on the phy devices. the ACD82112 merely provides an ac- cess path for the control cpu to access the registers on the phys. for detailed information about these reg- isters, please refer to the phy data sheet. register-32 through register-44 are assigned to phy- 0 through phy-11 respectively. the contents of these registers are the register ids inside the corresponding phys. for example, a 4 in register-44 will point to the control register-4 inside phy-11. table-7.31: clkadj register bit description default 0 - arlclk not inverted 1 - arlclk inverted arlclk delay levels: 000 - level 0 delay 001 - level 1 delay 010 - level 2 delay 011 - level 3 delay 100 - level 4 delay 101 - level 5 delay 110 - level 6 delay 111 - level 7 delay 000 0 0 3:1
25 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory 8. pin descriptions figure-8.1: pin diagram/bottom view aa ab ac ad ae af 2 4 6 8 10 12 14 16 18 20 22 24 26 1 3 5 7 9 11 13 15 17 19 21 23 25 a b c d e f g h j k l m n p r t u v w y table-8.1: thermal ground pins pin signal i/o type l[11:16] m[11:16] n[11:16] p[11:16] r[11:16] t[11:16] vss ground/thermal
26 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory table-8.2: pin list by location pin signal name i/o type pin signal name i/o type pin signal name i/o type pin signal name i/o type a01 dat a51 3.3v i/o d11 arls ync 3.3v o p01 dat a25 3.3v i/o ac17 vs s a02 dat a50 3.3v i/o d12 vs s p02 dat a24 3.3v i/o ac18 p3t xenr 3.3v o a03 s t at 1 3.3v o d13 vs s p03 vdd ac19 p3rxd0r 3.3v i a04 s t at 3 3.3v o d14 p11rxd3r 3.3v i p04 vs s ac20 vs s a05 addr9 3.3v o d15 vs s p23 p7t xd0 3.3v i/o ac21 p4t xd1 3.3v o a06 addr8 3.3v o d16 p11rxd1r 3.3v i p24 p7t xd1 3.3v i/o ac22 p4rxclk 3.3v i a07 addr7 3.3v o d17 vs s p25 p7t xd2 3.3v i/o ac23 vs s a08 addr6 3.3v o d18 p11t xenr 3.3v o p26 p7t xd3 3.3v i/o ac24 p5col 3.3v i a09 addr5 3.3v o d19 p11colr 3.3v i/o r01 dat a23 3.3v i/o ac25 p5t xd2 3.3v i/o a10 nwe 3.3v o d20 vs s r02 dat a22 3.3v i/o ac26 p5t xd1 3.3v i/o a11 ncs 0 3.3v o d21 p10rxer 3.3v i r03 vdd ad01 dat a5 3.3v i/o a12 addr4 3.3v o d22 p10t xd2 3.3v o r04 vs s ad02 dat a4 3.3v i/o a13 addr3 3.3v o d23 vs s r23 p7col 3.3v i ad03 vdd a14 addr2 3.3v o d24 p9rxd0 3.3v i r24 p7crs 3.3v i ad04 p0crs r 3.3v i/o a15 addr1 3.3v o d25 p9t xd1 3.3v o r25 p6rxd3 3.3v i ad05 p0t xd1r 3.3v i/o a16 addr0 3.3v o d26 p9t xd2 3.3v o r26 p6rxd2 3.3v i ad06 p0t xclkr 3.3v i/o a17 p11rxerr 3.3v i e01 dat a43 3.3v i/o t 01 dat a21 3.3v i/o ad07 vdd a18 p11t xd1r 3.3v o e02 dat a42 3.3v i/o t 02 dat a20 3.3v i/o ad08 p1crs r 3.3v i/o a19 p11crs r 3.3v i/o e03 arldir0 3.3v o t 03 ledclk 3.3v i/o ad09 p1t xd0r 3.3v i/o a20 p10rxd3 3.3v i e04 arldir1 3.3v o t 04 cpuirq 3.3v o ad10 vdd a21 p10rxd1 3.3v i e23 p9rxdv 3.3v i t 23 p6rxd1 3.3v i ad11 p1rxdvr 3.3v i a22 p10rxdv 3.3v i e24 p9t xen 3.3v o t 24 p6rxd0 3.3v i ad12 p1rxd3r 3.3v i a23 p10t xd0 3.3v o e25 p9col 3.3v i t 25 p6rxdv 3.3v i ad13 p2t xd2r 3.3v o a24 p10col 3.3v i e26 p9crs 3.3v i t 26 p6rxclk 3.3v i ad14 vdd a25 p9rxd3 3.3v i f01 dat a41 3.3v i/o u01 dat a19 3.3v i/o ad15 p2rxclkr 3.3v i/o a26 p9rxd1 3.3v i f02 dat a40 3.3v i/o u02 dat a18 3.3v i/o ad16 p2rxd2r 3.3v i b01 dat a49 3.3v i/o f03 vdd u03 vdd ad17 vdd b02 dat a48 3.3v i/o f04 vs s u04 vs s ad18 p3t xd0r 3.3v o b03 s t at 0 3.3v o f23 p9t xd0 3.3v o u23 vs s ad19 p3rxdvr 3.3v i b04 s t at 2 3.3v o f24 p9t xd3 3.3v o u24 vdd ad20 vdd b05 addr10 3.3v o f25 p8rxd3 3.3v i u25 p6rxer 3.3v i ad21 p4col 3.3v i b06 addr11 3.3v o f26 p8rxd2 3.3v i u26 p6t xclk 3.3v i ad22 p4t xd0 3.3v o b07 addr12 3.3v o g01 dat a39 3.3v i/o v01 dat a17 3.3v i/o ad23 p4rxdv 3.3v i b08 addr13 3.3v o g02 dat a38 3.3v i/o v02 dat a16 3.3v i/o ad24 vdd b09 addr14 3.3v o g03 vdd v03 vdd ad25 p4rxd3 3.3v i b10 noe 3.3v i/o g04 vs s v04 vs s ad26 p5crs 3.3v i b11 addr15 3.3v o g23 vs s v23 p6t xd0 3.3v i/o ae01 dat a3 3.3v i/o b12 addr16 3.3v o g24 vdd v24 p6t xen 3.3v o ae02 dat a2 3.3v i/o b13 ncs 2 3.3v o g25 p8rxdv 3.3v i v25 p6t xd1 3.3v i/o ae03 vs s b14 ncs 3 3.3v o g26 p8rxclk 3.3v i v26 p6t xd2 3.3v i/o ae04 p0t xd3r 3.3v i/o b15 ncs 1 3.3v o h01 dat a37 3.3v i/o w01 dat a15 3.3v i/o ae05 p0t xd0r 3.3v i/o b16 p11rxdvr 3.3v i h02 dat a36 3.3v i/o w02 dat a14 3.3v i/o ae06 p0rxclkr 3.3v i/o b17 p11rxclkr 3.3v i/o h03 led2 3.3v i/o w03 cpudo 3.3v i/o ae07 p0rxd0r 3.3v i b18 p11t xd0r 3.3v o h04 led3 3.3v i/o w04 cpudi 3.3v i ae08 p1colr 3.3v i/o b19 p11t xd2r 3.3v o h23 p8rxd1 3.3v i w23 p6crs 3.3v i ae09 p1t xd2r 3.3v i/o b20 p10rxd2 3.3v i h24 p8rxd0 3.3v i w24 p6col 3.3v i ae10 p1t xclkr 3.3v i/o b21 p10rxd0 3.3v i h25 p8rxer 3.3v i w25 p6t xd3 3.3v i/o ae11 p1rxclkr 3.3v i/o b22 p10t xclk 3.3v i h26 p8t xd0 3.3v o w26 p5rxd3 3.3v i ae12 p1rxd2r 3.3v i b23 p10t xd1 3.3v o j01 dat a35 3.3v i/o y01 dat a13 3.3v i/o ae13 p2t xd3r 3.3v o b24 p10crs 3.3v i j02 dat a34 3.3v i/o y02 dat a12 3.3v i/o ae14 p2t xenr 3.3v o b25 p9rxd2 3.3v i j03 vdd y03 vdd ae15 p2rxerr 3.3v i b26 p9rxer 3.3v i j04 vs s y04 vs s ae16 p2rxd1r 3.3v i c01 dat a47 3.3v i/o j23 p8t xclk 3.3v i y23 vs s ae17 p3colr 3.3v i/o c02 dat a46 3.3v i/o j24 p8t xen 3.3v o y24 vdd ae18 p3t xd2r 3.3v o c03 vdd j25 p8t xd1 3.3v o y25 p5rxd1 3.3v i ae19 p3t xclkr 3.3v i/o c04 arldiv 3.3v i j26 p8t xd2 3.3v o y26 p5rxd2 3.3v i ae20 p3rxclkr 3.3v i/o c05 vdd k01 dat a33 3.3v i/o aa01 dat a11 3.3v i/o ae21 p3rxd2r 3.3v i c06 arldi2 3.3v i k02 dat a32 3.3v i/o aa02 dat a10 3.3v i/o ae22 p4crs 3.3v i c07 vdd k03 vdd aa03 mdio 3.3v i/o ae23 p4t xd2 3.3v o c08 arldi0 3.3v i k04 vs s aa04 wchdog 3.3v o ae24 p4rxer 3.3v i c09 vdd k23 vs s aa23 p5t xclk 3.3v i ae25 p4rxd1 3.3v i c10 vdd k24 vdd aa24 p5rxer 3.3v i ae26 p4rxd2 3.3v i c11 arlclk 3.3v o k25 p8t xd3 3.3v o aa25 p5rxdv 3.3v i af01 dat a1 3.3v i/o c12 vdd k26 p8col 3.3v i aa26 p5rxd0 3.3v i af02 dat a0 3.3v i/o c13 vdd l01 dat a31 3.3v i/o ab01 dat a9 3.3v i/o af03 clk50 3.3v i c14 p11rxd2r 3.3v i l02 dat a30 3.3v i/o ab02 mdc 3.3v o af04 p0t xd2r 3.3v i/o c15 vdd l03 led1 3.3v i/o ab03 dat a8 3.3v i/o af05 p0rxerr 3.3v i c16 p11rxd0r 3.3v i l04 led0 3.3v i/o ab04 vs s 3.3v i af06 p0rxdvr 3.3v i c17 vdd l23 p8crs 3.3v i ab23 p5t xd3 3.3v i/o af07 p0rxd1r 3.3v i c18 p11t xclkr 3.3v i/o l24 p7rxd3 3.3v i ab24 p5t xd0 3.3v i/o af08 p0rxd2r 3.3v i c19 p11t xd3r 3.3v o l25 p7rxd2 3.3v i ab25 p5t xen 3.3v o af09 p1t xd3r 3.3v i/o c20 vdd l26 p7rxd1 3.3v i ab26 p5rxclk 3.3v i af10 p1t xenr 3.3v o c21 p10rxclk 3.3v i m01 dat a29 3.3v i/o ac01 dat a7 3.3v i/o af11 p1rxerr 3.3v i c22 p10t xen 3.3v o m02 dat a28 3.3v i/o ac02 dat a6 3.3v i/o af12 p1rxd1r 3.3v i c23 p10t xd3 3.3v o m03 vdd ac03 nres et 3.3v i af13 p2colr 3.3v i/o c24 vdd m04 vs s ac04 vs s af14 p2t xd0r 3.3v o c25 p9rxclk 3.3v i m23 p7rxd0 3.3v i ac05 p0colr 3.3v i/o af15 p2t xclkr 3.3v i/o c26 p9t xclk 3.3v i m24 p7rxdv 3.3v i ac06 p0t xenr 3.3v o af16 p2rxd0r 3.3v i d01 dat a45 3.3v i/o m25 p7rxclk 3.3v i ac07 vs s af17 p3crs r 3.3v i/o d02 dat a44 3.3v i/o m26 p7rxer 3.3v i ac08 p0rxd3r 3.3v i af18 p3t xd3r 3.3v o d03 vs s 3.3v i n01 dat a27 3.3v i/o ac09 p1t xd1r 3.3v i/o af19 p3t xd1r 3.3v o d04 vs s n02 dat a26 3.3v i/o ac10 vs s af20 p3rxerr 3.3v i d05 arldi3 3.3v i n03 ledvld1 3.3v i/o ac11 p1rxd0r 3.3v i af21 p3rxd1r 3.3v i d06 vs s n04 ledvld0 3.3v i/o ac12 p2crs r 3.3v i/o af22 p3rxd3r 3.3v i d07 vs s n23 vs s ac13 p2t xd1r 3.3v o af23 p4t xd3 3.3v o d08 arldi1 3.3v i n24 vdd ac14 vs s af24 p4t xen 3.3v o d09 vs s n25 p7t xclk 3.3v i ac15 p2rxdvr 3.3v i af25 p4t xclk 3.3v i d10 vs s n26 p7t xen 3.3v o ac16 p2rxd3r 3.3v i af26 p4rxd0 3.3v i
27 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory table-8.3: pin list by name signal name i/o type pin signal name i/o type pin signal name i/o type pin signal name i/o type pin addr0 3.3v o a16 ledvld1 3.3v i/o n03 p5rxd0 3.3v i aa26 p11crs r 3.3v i/o a19 addr1 3.3v o a15 mdc 3.3v o ab02 p5rxd1 3.3v i y25 p11rxclkr 3.3v i/o b17 addr2 3.3v o a14 mdio 3.3v i/o aa03 p5rxd2 3.3v i y26 p11rxd0r 3.3v i c16 addr3 3.3v o a13 ncs 0 3.3v o a11 p5rxd3 3.3v i w26 p11rxd1r 3.3v i d16 addr4 3.3v o a12 ncs 1 3.3v o b15 p5rxdv 3.3v i aa25 p11rxd2r 3.3v i c14 addr5 3.3v o a09 ncs 2 3.3v o b13 p5rxer 3.3v i aa24 p11rxd3r 3.3v i d14 addr6 3.3v o a08 ncs 3 3.3v o b14 p5t xclk 3.3v i aa23 p11rxdvr 3.3v i b16 addr7 3.3v o a07 noe 3.3v i/o b10 p5t xd0 3.3v i/o ab24 p11rxerr 3.3v i a17 addr8 3.3v o a06 nres et 3.3v i ac03 p5t xd1 3.3v i/o ac26 p11t xclkr 3.3v i/o c18 addr9 3.3v o a05 nwe 3.3v o a10 p5t xd2 3.3v i/o ac25 p11t xd0r 3.3v o b18 addr10 3.3v o b05 p0colr 3.3v i/o ac05 p5t xd3 3.3v i/o ab23 p11t xd1r 3.3v o a18 addr11 3.3v o b06 p0crs r 3.3v i/o ad04 p5t xen 3.3v o ab25 p11t xd2r 3.3v o b19 addr12 3.3v o b07 p0rxclkr 3.3v i/o ae06 p6col 3.3v i w24 p11t xd3r 3.3v o c19 addr13 3.3v o b08 p0rxd0r 3.3v i ae07 p6crs 3.3v i w23 p11t xenr 3.3v o d18 addr14 3.3v o b09 p0rxd1r 3.3v i af07 p6rxclk 3.3v i t 26 s t at 0 3.3v o b03 addr15 3.3v o b11 p0rxd2r 3.3v i af08 p6rxd0 3.3v i t 24 s t at 1 3.3v o a03 addr16 3.3v o b12 p0rxd3r 3.3v i ac08 p6rxd1 3.3v i t 23 s t at 2 3.3v o b04 arlclk 3.3v o c11 p0rxdvr 3.3v i af06 p6rxd2 3.3v i r26 s t at 3 3.3v o a04 arldi0 3.3v i c08 p0rxerr 3.3v i af05 p6rxd3 3.3v i r25 vdd power 3.3v ad03 arldi1 3.3v i d08 p0t xclkr 3.3v i/o ad06 p6rxdv 3.3v i t 25 vdd power 3.3v ad07 arldi2 3.3v i c06 p0t xd0r 3.3v i/o ae05 p6rxer 3.3v i u25 vdd power 3.3v ad14 arldi3 3.3v i d05 p0t xd1r 3.3v i/o ad05 p6t xclk 3.3v i u26 vdd power 3.3v ad20 arldir0 3.3v o e03 p0t xd2r 3.3v i/o af04 p6t xd0 3.3v i/o v23 vdd power 3.3v ad24 arldir1 3.3v o e04 p0t xd3r 3.3v i/o ae04 p6t xd1 3.3v i/o v25 vdd power 3.3v c03 arldiv 3.3v i c04 p0t xenr 3.3v o ac06 p6t xd2 3.3v i/o v26 vdd power 3.3v c05 arls ync 3.3v o d11 p1colr 3.3v i/o ae08 p6t xd3 3.3v i/o w25 vdd power 3.3v c09 clk50 3.3v i af03 p1crs r 3.3v i/o ad08 p6t xen 3.3v o v24 vdd power 3.3v c12 cpudi 3.3v i w04 p1rxclkr 3.3v i/o ae11 p7col 3.3v i r23 vdd power 3.3v c13 cpudo 3.3v i/o w03 p1rxd0r 3.3v i ac11 p7crs 3.3v i r24 vdd power 3.3v c15 cpuirq 3.3v o t 04 p1rxd1r 3.3v i af12 p7rxclk 3.3v i m25 vdd power 3.3v c20 dat a0 3.3v i/o af02 p1rxd2r 3.3v i ae12 p7rxd0 3.3v i m23 vdd power 3.3v c24 dat a1 3.3v i/o af01 p1rxd3r 3.3v i ad12 p7rxd1 3.3v i l26 vdd power 3.3v g03 dat a2 3.3v i/o ae02 p1rxdvr 3.3v i ad11 p7rxd2 3.3v i l25 vdd power 3.3v j03 dat a3 3.3v i/o ae01 p1rxerr 3.3v i af11 p7rxd3 3.3v i l24 vdd power 3.3v n24 dat a4 3.3v i/o ad02 p1t xclkr 3.3v i/o ae10 p7rxdv 3.3v i m24 vdd power 3.3v p03 dat a5 3.3v i/o ad01 p1t xd0r 3.3v i/o ad09 p7rxer 3.3v i m26 vdd power 3.3v r03 dat a6 3.3v i/o ac02 p1t xd1r 3.3v i/o ac09 p7t xclk 3.3v i n25 vdd power 3.3v y24 dat a7 3.3v i/o ac01 p1t xd2r 3.3v i/o ae09 p7t xd0 3.3v i/o p23 vdd power 3.3v ad17 dat a8 3.3v i/o ab03 p1t xd3r 3.3v i/o af09 p7t xd1 3.3v i/o p24 vdd power 3.3v c10 dat a9 3.3v i/o ab01 p1t xenr 3.3v o af10 p7t xd2 3.3v i/o p25 vdd power 3.3v k03 dat a10 3.3v i/o aa02 p2colr 3.3v i/o af13 p7t xd3 3.3v i/o p26 vdd power 3.3v k24 dat a11 3.3v i/o aa01 p2crs r 3.3v i/o ac12 p7t xen 3.3v o n26 vdd power 3.3v u03 dat a12 3.3v i/o y02 p2rxclkr 3.3v i/o ad15 p8col 3.3v i k26 vdd power 3.3v u24 dat a13 3.3v i/o y01 p2rxd0r 3.3v i af16 p8crs 3.3v i l23 vdd power 3.3v y03 dat a14 3.3v i/o w02 p2rxd1r 3.3v i ae16 p8rxclk 3.3v i g26 vdd power 3.3v ad10 dat a15 3.3v i/o w01 p2rxd2r 3.3v i ad16 p8rxd0 3.3v i h24 vdd power 3.3v c07 dat a16 3.3v i/o v02 p2rxd3r 3.3v i ac16 p8rxd1 3.3v i h23 vdd power 3.3v c17 dat a17 3.3v i/o v01 p2rxdvr 3.3v i ac15 p8rxd2 3.3v i f26 vdd power 3.3v f03 dat a18 3.3v i/o u02 p2rxerr 3.3v i ae15 p8rxd3 3.3v i f25 vdd power 3.3v g24 dat a19 3.3v i/o u01 p2t xclkr 3.3v i/o af15 p8rxdv 3.3v i g25 vdd power 3.3v m03 dat a20 3.3v i/o t 02 p2t xd0r 3.3v o af14 p8rxer 3.3v i h25 vdd power 3.3v v03 dat a21 3.3v i/o t 01 p2t xd1r 3.3v o ac13 p8t xclk 3.3v i j23 vs s 3.3v i ab04 dat a22 3.3v i/o r02 p2t xd2r 3.3v o ad13 p8t xd0 3.3v o h26 vs s 3.3v i d03 dat a23 3.3v i/o r01 p2t xd3r 3.3v o ae13 p8t xd1 3.3v o j25 vs s ground d09 dat a24 3.3v i/o p02 p2t xenr 3.3v o ae14 p8t xd2 3.3v o j26 vs s ground d12 dat a25 3.3v i/o p01 p3colr 3.3v i/o ae17 p8t xd3 3.3v o k25 vs s ground d15 dat a26 3.3v i/o n02 p3crs r 3.3v i/o af17 p8t xen 3.3v o j24 vs s ground d20 dat a27 3.3v i/o n01 p3rxclkr 3.3v i/o ae20 p9col 3.3v i e25 vs s ground g04 dat a28 3.3v i/o m02 p3rxd0r 3.3v i ac19 p9crs 3.3v i e26 vs s ground ac04 dat a29 3.3v i/o m01 p3rxd1r 3.3v i af21 p9rxclk 3.3v i c25 vs s ground ac14 dat a30 3.3v i/o l02 p3rxd2r 3.3v i ae21 p9rxd0 3.3v i d24 vs s ground ac23 dat a31 3.3v i/o l01 p3rxd3r 3.3v i af22 p9rxd1 3.3v i a26 vs s ground d04 dat a32 3.3v i/o k02 p3rxdvr 3.3v i ad19 p9rxd2 3.3v i b25 vs s ground d10 dat a33 3.3v i/o k01 p3rxerr 3.3v i af20 p9rxd3 3.3v i a25 vs s ground d13 dat a34 3.3v i/o j02 p3t xclkr 3.3v i/o ae19 p9rxdv 3.3v i e23 vs s ground k04 dat a35 3.3v i/o j01 p3t xd0r 3.3v o ad18 p9rxer 3.3v i b26 vs s ground k23 dat a36 3.3v i/o h02 p3t xd1r 3.3v o af19 p9t xclk 3.3v i c26 vs s ground p04 dat a37 3.3v i/o h01 p3t xd2r 3.3v o ae18 p9t xd0 3.3v o f23 vs s ground r04 dat a38 3.3v i/o g02 p3t xd3r 3.3v o af18 p9t xd1 3.3v o d25 vs s ground y04 dat a39 3.3v i/o g01 p3t xenr 3.3v o ac18 p9t xd2 3.3v o d26 vs s ground ac07 dat a40 3.3v i/o f02 p4col 3.3v i ad21 p9t xd3 3.3v o f24 vs s ground ac10 dat a41 3.3v i/o f01 p4crs 3.3v i ae22 p9t xen 3.3v o e24 vs s ground ac17 dat a42 3.3v i/o e02 p4rxclk 3.3v i ac22 p10col 3.3v i a24 vs s ground ac20 dat a43 3.3v i/o e01 p4rxd0 3.3v i af26 p10crs 3.3v i b24 vs s ground ae03 dat a44 3.3v i/o d02 p4rxd1 3.3v i ae25 p10rxclk 3.3v i c21 vs s ground d06 dat a45 3.3v i/o d01 p4rxd2 3.3v i ae26 p10rxd0 3.3v i b21 vs s ground d07 dat a46 3.3v i/o c02 p4rxd3 3.3v i ad25 p10rxd1 3.3v i a21 vs s ground d17 dat a47 3.3v i/o c01 p4rxdv 3.3v i ad23 p10rxd2 3.3v i b20 vs s ground d23 dat a48 3.3v i/o b02 p4rxer 3.3v i ae24 p10rxd3 3.3v i a20 vs s ground f04 dat a49 3.3v i/o b01 p4t xclk 3.3v i af25 p10rxdv 3.3v i a22 vs s ground g23 dat a50 3.3v i/o a02 p4t xd0 3.3v o ad22 p10rxer 3.3v i d21 vs s ground j04 dat a51 3.3v i/o a01 p4t xd1 3.3v o ac21 p10t xclk 3.3v i b22 vs s ground m04 led0 3.3v i/o l04 p4t xd2 3.3v o ae23 p10t xd0 3.3v o a23 vs s ground n23 led1 3.3v i/o l03 p4t xd3 3.3v o af23 p10t xd1 3.3v o b23 vs s ground u04 led2 3.3v i/o h03 p4t xen 3.3v o af24 p10t xd2 3.3v o d22 vs s ground u23 led3 3.3v i/o h04 p5col 3.3v i ac24 p10t xd3 3.3v o c23 vs s ground v04 ledclk 3.3v i/o t 03 p5crs 3.3v i ad26 p10t xen 3.3v o c22 vs s ground y23 ledvld0 3.3v i/o n04 p5rxclk 3.3v i ab26 p11colr 3.3v i/o d19 wchdog 3.3 v o aa04
28 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory t1 t2 rxclk rxdv rxd[3:0] rxer t# description: min typ max unit t1 rx_dv, rxd, rx_er setup time 5 - - ns t2 rx_dv, rxd, rx_er hold time 5 - - ns mii receive timing 9. timing description txclk txen txd[3:0] t2 t1 t# desciption min typ max unit t1 txen, txd setup time 10 - - ns t2 txen, txd hold time 10 - - ns mii transmit timing
29 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory rxclk rxdv rxd[3:0] t1 t2 t# description: min typ max unit t1 rxdv, rxd setup time 10 - ns t2 rxdv, rxd hold time 10 ns reversed mii receive timing t1 t2 txclk txen txd[3:0] t# description: min typ max unit t1 rxdv, rxd setup time 5 - ns t2 rxdv, rxd hold time 5 ns reversed mii transmit timing
30 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory rxclk rxd[3:0] rxdv t1 t# desciption min typ max unit t1 rxd to rxdv 0 - - ns reversed mii packet timing (start of packet) rxclk rxd[3:0] rxdv t1 t# desciption min typ max unit t1 pxd to rxdv delay time 0 - - ns reversed mii packet timing (end of packet)
31 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory t1 mdc mdio phy management read timing t2 t# description min typ max unit t1 mdio setup time 0 - 300 ns t2 mdc c y cle - 800 - ns t1 t2 mdc mdio t3 t4 t5 t # des cription min t y p max u nit t1 mdc high time 300 - 500 ns t2 mdc low time 300 - 500 ns t3 mdc period - 800 - ns t4 mdio s et up time 10 - - ns t5 mdio hold time 10 - - ns phy management write timing
32 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory t1 address data __ oe __ ce t2 t3 valid data t4 t5 t7 t6 t9 t8 high-z high-z t# description min typ max unit t1 read cycle time - 20 - ns t2 address access time - - 12 ns t3 output hold tim e 0 - - ns t4 oe access tim e - - 12 ns t5 ce access tim e - - 12 ns t6 oe to low-z output 0 - - ns t7 ce to low-z output 0 - - ns t8 oe to high-z output - - 6 ns t9 ce to high-z output - - 6 ns sram read timing sram read timing t1 address data __ ce t2 t3 valid data t6 t4 t8 t7 ___ we t5 t# description min typ max unit t1 w rite cycle time - 20 - ns t2 address setup to w rite end time 12 - - ns t3 address hold for w rite end time 0 - - ns t4 ce to w rite end time 12 - - ns t5 address setup time 4 - - ns t6 w e pulse width 8 - - ns t7 data setup to w rite end 8 - - ns t8 data hold for w rite end 0 - - ns sram w rite timing
33 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory t2 t3 da1 result1 da2 arlclk arldo arldi t1 result2 arl result timing t # des cription min t y p max u nit t1 time between das 0 - - ns t2 time for ar l res ult 0 - 200 ns t3 time between res ults 0 - - ns t2 cpudi idle state start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit t1 cpudo stop bit start bit stop bit t3 bit 7 bit 6 bit0 cpu command timing t4 t # des cription min t y p max u nit t1 cp u idle time 0 - - us t2 cpu command bit time 10 - 1000 us t3 response time 0 - 20 ms t4 comman d ti me - - 2 0 ms
34 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory 10. electrical specification absolute maximum ratings operation at absolute maximum ratings is not implied exposure to stresses outside those listed could cause permanent damage to the device. recommended operation conditions nled0 nled1 nled3 nled2 ledclk p11 p10 p9 p2 p1 p0 p11 p10 p9 p2 p1 p0 led signal timing ledvld0 ledvld1 fdx spd lnk fdx spd lnk fdx spd lnk fdx spd lnk fdx spd lnk fdx spd lnk err col rcv xmt err col rcv xmt err col rcv xmt err col rcv xmt err col rcv xmt err col rcv xmt dc supply voltage : vdd -0.3v ~ +5.0v dc input current: iin +/-10 ma dc input voltage: vin -0.3 ~ vdd + 0.3v dc output voltage: vout -0.3 ~ vdd + 0.3v storage temperature: tstg -40 to +125 o c supply voltage: vdd 3.3v, +/-0.3v operating temperature: ta 0 o c -70 o c maximum power consumption 3.3w
35 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory side view 11. packaging 0.6 2.33 0.56 bottom view 31.75 0.75 0.635 1.27 2 4 6 8 10 12 14 16 18 20 22 24 26 aa ab ac ad ae af a b c d e f g h j k l m n p r t u v w y 11 13 15 17 19 21 23 25 1 3 5 7 9 top view 30 35 advanced comm. devices flllll smayyww ACD82112
36 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory address resolution logic (the built-in arl with 2048 mac addresses) appendix-a1
37 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory 1. summary the internal address resolution logic (arl) of acds switch controllers automatically builds up an address table and maps up to 2,048 mac addresses into their associated port. it can work by itself without any cpu intervention in an un-managed system. for a managed system, the management cpu can con- figure the operation mode of the arl, learn all the ad- dress in the address table, add new address into the table, control security or filtering feature of each ad- dress entry etc. the arl is designed with such a high performance that it will never slow down the frame switching operation. it helps the switch controllers to reach wire speed for- warding rate under any type of traffic load. the address space can be expanded to 11k entries by using the external arl, the acd80800. 2. features supports up to 2,048 mac address lookup provides uart type of interface for the manage- ment cpu wire speed address lookup time. wire speed address learning time. address can be automatically learned from switch without the cpu intervention address can be manually added by the cpu through the cpu interface each mac address can be secured by the cpu from being changed or aged out each mac address can be marked by the cpu from receiving any frame each newly learned mac address is notified to the cpu each aged out mac address is notified to the cpu automatic address aging control, with configurable aging period cpu interface address registers data registers command registers control registers switch interface address learning engine cpu interface engine address table (2048 entries) figure-1. arl block diagram address aging engine address lookup engine
38 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory 3. functional description the arl provides address resolution service for acds switch controllers. figure 2 is a block diagram of the arl. t raf fic snooping all ethernet frames received by acds switch controller have to be stored into memory buffer. as the frame data are written into memory, the status of the data shown on the data bus are displayed by acds switch controller through a state bus. the arls switch con- troller interface contains the signals of the data bus and the state bus. by snooping the data bus and the state bus of acds switch controller, the arl can detect the occurrence of any destination mac address and source mac address embedded inside each frame. address learning each source address caught from the data bus, to- gether with the id of the ingress port, is passed to the address learning engine of the arl. the address learning engine will first determine whether the frame is a valid frame. for a valid frame, it will first try to find the source address from the current address table. if that address doesnt exist, or if it does exist but the port id associated with the mac address is not the ingress port, the address will be learned into the address table. after an address is learned by the address learning engine, the cpu will be notified to read this newly learned address so that it can add it into the cpus address table. address aging after each source address is learned into the address table, it has to be refreshed at least once within each address aging period. refresh means it is caught again from the switch interface. if it has not occurred for a pre-set aging period, the address aging engine will re- move the address from the address table. after an ad- dress is removed by the address aging engine, the cpu will be notified through interrupt request that it needs to read this aged out address so that it can remove this address from the cpus address table. address lookup each destination address is passed to the address lookup engine of the arl. the address lookup en- gine checks if the destination address matches with any existing address in the address table. if it does, the arl returns the associated port id to acds switch controller through the output data bus. otherwise, a no match result is passed to acds switch controller through the output data bus. cpu interface the cpu can access the registers of the arl by send- ing commands to the uart data input line. each com- mand is consisted by action (read or write), register type, register index, and data. each result of command execution is returned to the cpu through the uart data output line. cpu interface registers the arl provides a bunch of registers for the control cpu. through the registers, the cpu can read all ad- dress entries of the address table, delete particular ad- dresses from the table, add particular addresses into the table, secure an address from being changed, set filtering on some addresses, change the hashing algo- rithm etc. through a proper interrupt request signal, the cpu can be notified whenever it needs to retrieve data for a newly-learned address or an aged-out address so that the cpu can build an exact same address table learned by the arl. cpu interface engine the command sent by the control cpu is executed by the cpu interface engine. for example, the cpu may send a command to learn the first newly-learned ad- dress. the cpu interface engine is responsible to find the newly-learned address from the address table, and passes it to cpu. the cpu may request to learn next newly-learned address. then, it is again the responsi- bility of the cpu interface engine to search for next newly-learned address from the address table. address t able the address table can hold up to 2,048 mac addresses, together with the associated port id, security flag, filter- ing flag, new flag, aging information etc. the address table resides in the embedded sram inside the arl.
39 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory header address data checksum header address data checksum 4. interface description cpu interface the cpu can communicate with the arl through the uart interface of the switch ic. the management cpu can send command to the arl by writing into associ- ated registers, and retrieve result from arl by reading corresponding registers. the registers are described in the section of register description. the cpu inter- face signals are described by table-1 : uartdi is used by the control cpu to send command into the arl. the baud rate will be automatically de- tected by the arl. the result will be returned through the uartdo line with the detected baud rate. the for- mat of the command packet is shown as follows: where: header is further defined as: b1:b0 - read or write, 01 for read, 11 for write b4:b2 - device number, 000 to 111 (0 to 7, same as the host switch control- ler) b7:b5 - device type, 010 for arl address - 8-bit value used to select the reg- ister to access data - 32-bit value, only the lsb is used for write operation, all 0 for read operation checksum - 8-bit value of xor of all bytes uartdo is used to return the result of command ex- ecution to the cpu. the format of the result packet is shown as follows: where: header is further defined as: b1:b0 - read or write, 01 for read, 11 for write b4:b2 - device number, 000 to 111 (0 to 7) b7:b5 - device type, 010 for arl address - 8-bit value for address of the selected register data - 32-bit value, only the lsb is used for read operation, all 0 for write operation checksum - 8-bit value of xor of all bytes the arl will always check the cmd header to see if both the device type and the device number matches with its setting. if not, it ignores the command and will not generate any response to this command. table-1: cpu interface name i/o description uartdi i uart input data line. uartdo o uart output data line.
40 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory the dataregx are registers used to pass the param- eter of the command to the acd80800, and the result of the command to the cpu. the addrregx are registers used to specify the ad- dress associated with the command. the cmdreg is used to pass the type of command to the acd80800. the command types are listed in table- 3 . the details of each command is described in the chapter of command description. the rstreg is used to indicate the status of command execution. the result code is listed as follows: 01 - command is being executed and is not done yet 10 - command is done with no error 1x - command is done, with error indi- cated by x, where x is a 4-bit error code: 0001 for cannot find the entry as speci- fied 5. register description acd80800 provides a bunch of registers for the cpu to access the address table inside it. command is sent to acd80800 by writing into the associated registers. before the cpu can pass a command to acd80800, it must check the result register (register 11) to see if the command has been done. when the result register indicates the command has been done, the cpu may need to retrieve the result of previous command first. after that, the cpu has to write the associated param- eter of the command into the data registers. then, the cpu can write the command type into the command register. when a new command is written into the com- mand register, acd80800 will change the status of the result register to 0. the result register will indicate the completion of the command at the end of the execution. before the completion of the execution, any command written into the command register is ignored by acd80800. the registers accessible to the cpu are described by table-2 : table-3: command list command description 0x09 add the specified mac address into the address table 0x0a set a lock for the specified mac address 0x0b set a filtering flag for the specified mac address 0x0c delete the specified mac address from the address table 0x0d assign a port id to the specified mac address 0x10 read the first entry of the address table 0x11 read next entry of address book 0x20 read first valid entry 0x21 read next valid entry 0x30 read first new page 0x31 read next new page 0x40 read first aged page 0x41 read next aged page 0x50 read first locked page 0x51 read next locked page 0x60 read first filtered page 0x61 read next filtered page 0x80 read first page with specified pid 0x81 read next page with specified pid 0xff s y stem reset table-2: register description reg. name description 0 datareg0 byte 0 of data 1 datareg1 byte 1 of data 2 datareg2 byte 2 of data 3 datareg3 byte 3 of data 4 datareg4 byte 4 of data 5 datareg5 byte 5 of data 6 datareg6 byte 6 of data 7 datareg7 byte 7 of data 8 addrreg0 lsb of address value 9 addrreg1 msb of address value 10 cmdreg command register 11 rsltreg result register 12 cfgreg configuration register 13 intsrcreg interrupt source register 14 intmskreg interrupt mask register 15 nlearnreg0 address learning disable register for port 0 - 7 16 nlearnreg1 address learning disable register for port 8 - 15 17 nlearnreg2 address learning disable register for port 16 - 23 18 agetimereg0 lsb of aging period register 19 agetimereg1 msb of aging period register 20 poscfg power on strobe configuration register 0
41 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory the cfgreg is used to configure the way the acd80800 works. the bit definition of cfgreg is described as: bit 0 - disable address aging bit 1 - disable address lookup bit 2 - disable da cache bit 3 - disable sa cache bit 7:4 - hashing algorithm selection, de- fault is 0000 the intsrcreg is used to indicate what can cause in- terrupt request to cpu. the source of interrupt is listed as: bit 0 - aged address exists bit 1 - new address exists bit 2 - reserved bit 3 - reserved bit 4 - bucket overflowed bit 5 - command is done bit 6 - system initialization is completed bit 7 - self test failure the intmskreg is used to enable an interrupt source to generate an interrupt request. the bit definition is the same as intsrcreg. a 1 in a bit enables the corre- sponding interrupt source to generate an interrupt re- quest once it is set. the nlearnreg[2:0] are used to disable address learn- ing activity from a particular port. if the bit correspond- ing to a port is set, acd80800 will not try to learn new addresses from that port. the agetimereg[1:0] are used to specify the period of address aging control. the aging period can be from 0 to 65535 units, with each unit counted as 2.684 sec- ond. the poscfgreg is a configuration register whose de- fault value is determined by the pull-up or pull-down status of the associated hardware pin. the bits of poscfgreg0 is listed as follows: bit 1* - nocpu * , 0 = presence of control cpu, 1 = no control cpu; bit 0 - cpugo, 0 = wait for system start command from cpu before starting self initialization, 1 = cpu ready. only effec- tive when bit-1 (nocpu) is set to 0; note: when nocpu is set as 0, acd80800 will not start the initialization process until a system start com- mand is sent to the command register.
42 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory 6. command description command 09h description: add the specified mac address into the address table. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. store the as- sociated port number into datareg6. result: the mac address will be stored into the address table if there is space available. the result is indicated by the result register. command 0ah description: set the lock bit for the specified mac address. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. result: the state machine will seek for an entry with matched mac address, and set the lock bit of the en- try. the result is indicated by the result register. command 0bh description: set the filter flag for the specified mac address. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. result: the state machine will seek for an entry with matched mac address, and set the filter bit of the en- try. the result is indicated by the result register. command 0ch description: delete the specified mac address from the address table. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. result: the mac address will be removed from the ad- dress table. the result is indicated by the result regis- ter. command 0dh description: assign the associated port number to the specified mac address. parameter: store the mac address into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. store the port number into datareg6. result: the port id field of the entry containing the speci- fied mac address will be changed accordingly. the result is indicated by the result register. command 10h description: read the first entry of the address table. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of the first entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag * bits are stored in datareg7.the read pointer will be set to point to second entry of the address book. note - the flag bits are defined as: where: filter - 1 indicates the frame heading to this address should be dropped. lock - 1 indicates the entry should never be changed or aged out. new - 1 indicates the entry is a newly learned address. old - 1 indicates the address has been aged out. age - 1 indicates the address has not been visited for current age cycle. valid - 1 indicates the entry is a valid one. rsvd - reserved bits. b7 b6 b5 b4 b3 b2 b1 b0 rsvd rsvd filter lock new old age valid
43 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory command 1 1h description: read next entry of address book. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of the address book entry pointed by read pointer will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 con- tains the msb of the mac address and datareg0 con- tains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer will be increased by one. command 20h description: read first valid entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first valid entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 21h description: read next valid entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next valid entry from the read pointer of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 30h description: read first new page. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first new entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 31h description: read next new entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next new entry from the read pointer of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 40h description: read first aged entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first aged entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 41h description: read next aged entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next aged entry from the read pointer of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry.
44 acd confidential. do not reproduce. use under non-disclosure agreement only. data sheet: ACD82112 introductory command 50h description: read first locked entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first locked entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 51h description: read next locked entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next locked entry from the read pointer of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 60h description: read first filtered page. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of first filtered entry of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 61h description: read next valid entry. parameter: none result: the result is indicated by the result register. if the command is completed with no error, the content of next filtered entry from the read pointer of the address book will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 80h description: read first entry with specified port num- ber. parameter: store port number into datareg6. result: the result is indicated by the result register. if the command is completed with no error, the content of first entry of the address book with the said port num- ber will be stored into the data registers. the mac ad- dress will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command 81h description: read next valid entry. parameter: store port number into datareg6. result: the result is indicated by the result register. if the command is completed with no error, the content of next entry from the read pointer of the address book with the said port number will be stored into the data registers. the mac address will be stored into datareg5 - datareg0, with datareg5 contains the msb of the mac address and datareg0 contains the lsb. the port number is stored in datareg6, and the flag bits are stored in datareg7. the read pointer is set to point to this entry. command ffh description: system reset. parameter: none result: this command will reset the arl system. all entries of the address book will be cleared.

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