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19-3953; rev 4; 7/13 max3421e usb peripheral/host controller with spi interface evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maximintegrated.com. general description the max3421e usb peripheral/host controller contains the digital logic and analog circuitry necessary to implement a full-speed usb peripheral or a full-/low- speed host compliant to usb specification rev 2.0. a built-in transceiver features ?5kv esd protection and programmable usb connect and disconnect. an inter- nal serial interface engine (sie) handles low-level usb protocol details such as error checking and bus retries. the max3421e operates using a register set accessed by an spi interface that operates up to 26mhz. any spi master (microprocessor, asic, dsp, etc.) can add usb peripheral or host functionality using the simple 3- or 4- wire spi interface. the max3421e makes the vast collection of usb peripherals available to any microprocessor, asic, or dsp when it operates as a usb host. for point-to-point solutions, for example, a usb keyboard or mouse inter- faced to an embedded system, the firmware that oper- ates the max3421e can be simple since only a targeted device is supported. internal level translators allow the spi interface to run at a system voltage between 1.4v and 3.6v. usb-timed operations are done inside the max3421e with inter- rupts provided at completion so an spi master does not need timers to meet usb timing requirements. the max3421e includes eight general-purpose inputs and outputs so any microprocessor that uses i/o pins to implement the spi interface can reclaim the i/o pins and gain additional ones. the max3421e operates over the extended -40? to +85? temperature range and is available in a 32-pin tqfp package (5mm x 5mm) and a 32-pin tqfn pack- age (5mm x 5mm). applications features microprocessor-independent usb solution software compatible with the max3420e usb peripheral controller with spi interface complies with usb specification revision 2.0 (full-speed 12mbps peripheral, full-/low-speed 12mbps/1.5mbps host) integrated usb transceiver firmware/hardware control of an internal d+ pullup resistor (peripheral mode) and d+/d- pulldown resistors (host mode) programmable 3- or 4-wire, 26mhz spi interface level translators and v l input allow independent system interface voltage internal comparator detects v bus for self- powered peripheral applications esd protection on d+, d-, and vbcomp interrupt output pin (level- or programmable- edge) allows polled or interrupt-driven spi interface eight general-purpose inputs and eight general- purpose outputs interrupt signal for general-purpose input pins, programmable edge polarity intelligent usb sie automatically handles usb flow control and double buffering handles low-level usb signaling details contains timers for usb time-sensitive operations so spi master does not need to time events space-saving lead-free tqfp and tqfn packages (5mm x 5mm) embedded systems medical devices microprocessors and dsps custom usb devices cameras desktop routers plcs set-top boxes pdas mp3 players instrumentation part temp range pin- package top mark m ax 3421e e h j+ - 40c to + 85c 32 tqfp m ax 3421e e tj+ - 40c to + 85c 32 tqfn - e p *btbg ordering information * ep = exposed pad. + denotes a lead(pb)-free/rohs-compliant package.
max3421e usb peripheral/host controller with spi interface 2 maxim integrated features in host operation eleven registers (r21?31) are added to the max3420e register set to control host operation host controller operates at full speed or low speed fifos sndfifo: send fifo, double-buffered 64-byte rcvfifo: receive fifo, double-buffered 64-byte handles data0/data1 toggle generation and checking performs error checking for all transfers automatically generates sof (full-speed)/eop (low-speed) at 1ms intervals automatically synchronizes host transfers with beginning of frame (sof/eop) reports results of host requests supports usb hubs supports isochronous transfers simple programming sie automatically generates periodic sof (full-speed) or eop (low-speed) frame markers spi master loads data, sets function address, endpoint, and transfer type, and initiates the transfer max3421e responds with an interrupt and result code indicating peripheral response transfer request can be loaded any time sie synchronizes with frame markers for multipacket transfers, the sie automatically maintains and checks the data toggles features in peripheral operation built-in endpoint fifos ep0: control (64 bytes) ep1: out, bulk or interrupt, 2 x 64 bytes (double-buffered) ep2: in, bulk or interrupt, 2 x 64 bytes (double-buffered) ep3: in, bulk or interrupt (64 bytes) double-buffered data endpoints increase throughput by allowing the spi master to transfer data concurrent with usb transfers setup data has its own 8-byte fifo, simplifying firmware the max3421e connects to any microprocessor (?) using 3 or 4 interface pins (figure 1). on a simple microprocessor without spi hardware, these can be bit-banged general-purpose i/o pins. eight gpin and eight gpout pins on the max3421e more than replace the ? pins necessary to implement the inter- face. although the max3421e spi hardware includes separate data-in (mosi, master-out, slave-in) and data- out (miso, master-in, slave-out) pins, the spi interface can also be configured for the mosi pin to carry bidi- rectional data, saving an interface pin. this is referred to as half-duplex mode. typical application circuits 3.3v regulator spi 3, 4 int usb p max3421e figure 1. the max3421e connects to any microprocessor using 3 or 4 interface pins
max3421e usb peripheral/host controller with spi interface 3 maxim integrated 3.3v regulator power rail asic, dsp, etc. spi 3, 4 int max3421e usb figure 2. the max3421e connected to a large chip 3.3v regulator miso local gnd local power int max3421e sclk mosi ss micro asic dsp i s o l a t o r s usb figure 3. optical isolation of usb using the max3421e micro, asic, dsp usb peripheral usb "a" usb "b" v bus switch fault 5v spi 3, 4 int v bus d+ d- gnd v bus power on/off 3.3v regulator max3421e figure 4. the max3421e in an embedded host application two max3421e features make it easy to connect to large, fast chips such as asics and dsps (figure 2). first, the spi interface can be clocked up to 26mhz. second, the v l pin and internal level translators allow running the system interface at a lower voltage than the 3.3v required for v cc . the max3421e provides an ideal method for electrically isolating a usb interface (figure 3). usb employs flow control in which the max3421e automatically answers host requests with a nak handshake, until the micro- processor completes its data-transfer operations over the spi port. this means that the spi interface can run at any frequency up to 26mhz. therefore, the designer is free to choose the interface operating frequency and to make opto-isolator choices optimized for cost or per- formance. figure 4 shows a block diagram for a system in which the max3421e operates as a usb host. a usb host supplies 5v power to the v bus pin of the usb ??con- nector to power usb peripherals. a system that pro- vides power to an external peripheral should use protection circuitry on the power pin to prevent an external overcurrent situation from damaging the sys- tem. a v bus switch, such as the max4789, provides power control plus two additional features: it limits the current delivered to the peripheral (for example to 200ma), and it indicates a fault (overcurrent) condition to the spi controller. maxim offers a variety of v bus switches with various current limits and features. consult the maxim website for details. a 3.3v regulator (for example, the max6349tl) powers the max3421e, and optionally the system controller. if the system controller operates with a lower voltage, the max3421e spi and i/o interface can run at the lower voltage by connecting the system voltage (for exam- ple, 2.5v or 1.8v) to the max3421e v l pin. typical application circuits (continued)
max3421e usb peripheral/host controller with spi interface 4 maxim integrated functional diagram gpin0 1v to 3v vbcomp d- d+ v cc r gpin v bus comp ss miso sclk int spi slave interface usb sie (serial- interface engine) full-speed/ low-speed usb transceiver reset logic 1.5k internal por res xi xo power down osc and 4x pll 48mhz esd protection esd protection gpx operate sof busact/ inirq mux 0123 mosi vbus_det endpoint buffers max3421e gnd gpin1 gpin2 gpin3 gpin4 gpin5 gpin6 gpin7 gpout0 gpout1 gpout2 gpout3 gpout4 gpout5 gpout6 gpout7 v l r in 15k 15k
max3421e usb peripheral/host controller with spi interface 5 maxim integrated pin description pin name input/ output function 1 gpin7 input general-purpose input. gpin7?pin0 are connected to v l with internal pullup resistors. gpin7?pin0 logic levels are referenced to the voltage on v l . 2v l input level-translator voltage input. connect v l to the system? 1.4v to 3.6v logic-level power supply. bypass v l to ground with a 0.1? capacitor as close to v l as possible. 3, 19 gnd input ground 4 gpout0 5 gpout1 6 gpout2 7 gpout3 8 gpout4 9 gpout5 10 gpout6 11 gpout7 output general-purpose push-pull outputs. gpout7?pout0 logic levels are referenced to the voltage on v l . 12 res input device reset. drive res low to clear all of the internal registers except for pinctl (r17), usbctl (r15), and spi logic. the logic level is referenced to the voltage on v l . (see the device reset section for a description of resets available on the max3421e.) note: the max3421e is internally reset if either v c c or v l is not present. the register file is not accessible under these conditions. 13 sclk input s p i s er i al - c l ock inp ut. an exter nal s p i m aster sup p l i es s c lk w i th fr eq uenci es up to 26m h z. the l og i c l evel i s r efer enced to the vol tag e on v l . d ata i s cl ocked i nto the s p i sl ave i nter face on the r i si ng ed g e of s c lk. d ata i s cl ocked out of the s p i sl ave i nter face on the fal l i ng ed g e of s c lk. 14 ss input spi slave select input. the ss logic level is referenced to the voltage on v l . when ss is driven high, the spi slave interface is not selected, the miso pin is high impedance, and sclk transitions are ignored. an spi transfer begins with a high-to-low ss transition and ends with a low-to-high ss transition. 15 miso output spi serial-data output (master-in slave-out). miso is a push-pull output. miso is tri-stated in half-duplex mode or when ss = 1. the miso logic level is referenced to the voltage on v l . 16 mosi input or input/ output spi serial-data input (master-out slave-in). the logic level on mosi is referenced to the voltage on v l . mosi can also be configured as a bidirectional mosi/miso input and output. (see figure 15.) 17 gpx output g ener al - p ur p ose m ul ti p l exed p ush- p ul l o utp ut. the i nter nal m ax 3421e si g nal that ap p ear s on g p x i s p r og r am m ab l e b y w r i ti ng to the g p x b and g p x a b i ts of the p in c tl ( r17) r eg i ster and the s e p irq b i t of the m o d e ( r27) r eg i ster . gp x i nd i cates one of fi ve si g nal s ( see the g p x secti on) . 18 int output interrupt output. in edge mode, the logic level on int is referenced to the voltage on v l and is a push-pull output with programmable polarity. in level mode, int is open-drain and active low. set the ie bit in the cpuctl (r16) register to enable int. 20 d- input/ output usb d- signal. connect d- to a usb connector through a 33 ?% series resistor. a switchable 15k d- pulldown resistor is internal to the device.
max3421e usb peripheral/host controller with spi interface 6 maxim integrated pin description (continued) pin name input/ output function 21 d+ input/ output usb d+ signal. connect d+ to a usb connector through a 33 ?% series resistor. a switchable 1.5k d+ pullup resistor and 15k d+ pulldown resistor is internal to the device. 22 vbcomp input v bus comparator input. vbcomp is internally connected to a voltage comparator to allow the spi master to detect (through an interrupt or checking a register bit) the presence or loss of power on v bus . bypass vbcomp to ground with a 1.0? ceramic capacitor. vbcomp is pulled down to ground with r in (see electrical characteristics ). 23 v cc input u s b tr anscei ver and log i c c or e p ow er - s up p l y inp ut. c onnect v c c to a p osi ti ve 3.3v p ow er sup p l y. byp ass v c c to g r ound w i th a 1.0? cer am i c cap aci tor as cl ose to the v c c p i n as p ossi b l e. 24 xi input crystal oscillator input. connect xi to one side of a parallel resonant 12mhz ?.25% crystal and a load capacitor to gnd. xi can also be driven by an external clock referenced to v cc . 25 xo output c r ystal osci l l ator o utp ut. c onnect x o to the other si d e of a p ar al l el r esonant 12m h z 0.25% cr ystal and a l oad cap aci tor to gn d . leave x o unconnected i f x i i s d r i ven w i th an exter nal sour ce. 26 gpin0 27 gpin1 28 gpin2 29 gpin3 30 gpin4 31 gpin5 32 gpin6 input general-purpose inputs. gpin7?pin0 are connected to v l with internal pullup resistors. gpin7?pin0 logic levels are referenced to the voltage on v l . ep input e xp osed p ad , c onnected to g r ound . c onnect e p to g n d or l eave unconnected . e p i s l ocated on the b ottom of the tq fn p ackag e. the tqfp p ackag e d oes not have an exp osed p ad .
max3421e usb peripheral/host controller with spi interface 7 maxim integrated register description the spi master controls the max3421e by reading and writing 26 registers in peripheral mode (see table 1) or reading and writing 23 registers in host mode (see table 2). setting the host bit in the mode (r27) register con- figures the max3421e for host operation. when operating as a usb peripheral, the max3421e is register-compati- ble with the max3420e with the additional features listed in note 1b below table 1. for a complete description of register contents, refer to the max3421e programming guide on the maxim website. a register access consists of the spi master first writing an spi command byte followed by reading or writing the contents of the addressed register. all spi transfers are msb first. the command byte contains the register address, a direction bit (read = 0, write = 1), and the ackstat bit (figure 5). the spi master addresses the max3421e registers by writing the binary value of the register number in the reg4 through reg0 bits of the command byte. for example, to access the iopins1 (r20) register, the reg4 through reg0 bits would be as follows: reg4 = 1, reg3 = 0, reg2 = 1, reg1 = 0, reg0 = 0. the dir (direction) bit determines the direction for the data transfer. dir = 1 means the data byte(s) are written to the register, and dir = 0 means the data byte(s) are read from the register. the ackstat bit sets the ackstat bit in the epstalls (r9) register (periph- eral mode only). the spi master sets this bit to indicate that it has finished servicing a control transfer. since the bit is frequently used, having it in the spi command byte improves firmware efficiency. the ackstat bit is ignored in host mode. in spi full-duplex mode, the max3421e clocks out eight usb status bits as the com- mand byte is clocked in (figures 6, 7). in half-duplex mode, these status bits are accessed as register bits. the first five registers (r0?4) address fifos in both peripheral and host modes. repeated accesses to these registers freeze the internal register address so that mul- tiple bytes may be written to or read from a fifo in the same spi access cycle (while ss is low). accesses to registers r5?19 increment the internal register address for every byte transferred during the spi access cycle. accessing r20 freezes access at that register, access- ing r21?31 increments the internal address, and repeated accesses to r31 freeze at r31. the register maps in table 1 and table 2 show which register bits apply in peripheral and host modes. register bits that do not apply to a particular mode are shown as zeros. these register bits read as zero values and should not be written to with a logic 1. register map in peripheral mode the max3421e maintains register compatibility with the max3420e when operating in usb peripheral mode (max3421e host bit is set to 0 (default)). firmware written for the max3420e runs without modification on the max3421e. to support new max3421e features, the register set includes new bits, described in note 1b at the bottom of table 1. register map in host mode as table 2 shows, in host mode (host = 1), some max3420e registers are renamed (for example r1 becomes rcvfifo), some are not used (shown with zeros), and some still apply to host mode. in addition, 11 registers (r21?31) add the usb host capability. figure 7. usb status bits clocked out as first byte of every transfer in host mode (full-duplex mode only) status bits (host mode) b7 b6 b5 b4 b3 b2 b1 b0 hxfrdnirq frameirq connirq susdnirq sndbavirq rcvdavirq rsmreqirq buseventirq * the ackstat bit is ignored in host mode. figure 5. spi command byte b7 b6 b5 b4 b3 b2 b1 b0 reg4 reg3 reg2 reg1 reg0 0 dir ackstat* figure 6. usb status bits clocked out as first byte of every transfer in peripheral mode (full-duplex mode only) status bits (peripheral mode) b7 b6 b5 b4 b3 b2 b1 b0 suspirq uresirq sudavirq in3bavirq in2bavirq out1davirq out0davirq in0bavirq
max3421e usb peripheral/host controller with spi interface 8 maxim integrated table 1. max3421e register map in peripheral mode (host = 0) (notes 1a, 1b) r eg name b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 a c c r0 ep0 f if o b 7b 6b 5b 4b 3b 2b 1b 0rs c r1 ep1 o u t f if o b 7b 6b 5b 4b 3b 2b 1b 0rs c r2 ep2 in f if o b 7b 6b 5b 4b 3b 2b 1b 0rs c r3 ep3 in f if o b 7b 6b 5b 4b 3b 2b 1b 0rs c r4 su d f if o b 7b 6b 5b 4b 3b 2b 1b 0rs c r5 ep0 b c 0b 6b 5b 4b 3b 2b 1b 0rs c r6 ep1 o u t b c 0b 6b 5b 4b 3b 2b 1b 0rs c r7 ep2 in b c 0b 6b 5b 4b 3b 2b 1b 0rs c r8 ep3 in b c 0b 6b 5b 4b 3b 2b 1b 0rs c r9 epst a l l s 0ac ks tat s tls tat s tle p 3in s tle p 2in s tle p 1ou ts tle p 0ou ts tle p 0in rs c r10 c l r t o g s e p 3d is ab e p 2d is ab e p 1d is ab c tg e p 3in c tg e p 2in c tg e p 1ou t0 0rs c r11 epi r q 00s u d av irq in 3bav irq in 2bav irq ou t1d av irq ou t0d av irq in 0bav irq rc r12 epi en 00s u d av ie in 3bav ie in 2bav ie ou t1d av ie ou t0d av ie in 0bav ie rs c r13 u sb ir q u re s d n irq v bu s irq n ov bu s irq s u s p irq u re s irq bu s ac tirq rwu d n irq os c okirq rc r14 u sb ien u re s d n ie v bu s ie n ov bu s ie s u s p ie u re s ie bu s ac tie rwu d n ie os c okie rs c r15 u sb c t l h os c s te n v bg ate c h ip re s p wrd own c on n e c ts ig rwu 0 0 rs c r16 c pu c t l p u ls e wid 1p u ls e wid 00 0 0 0 0 ie rs c r17 pin c t l e p 3in ak e p 2in ak e p 0in ak fd u p s p iin tle v e lp os in tgp x bgp x ars c r18 r evisio n 00 010 0 1 1r r19 f n a d d r 0b 6b 5b 4b 3b 2b 1b 0r r20 io pin s1 gp in 3gp in 2gp in 1gp in 0gp o u t3 gp o u t2 gp o u t1 gp o u t0 rs c r21 iopins2 gp in 7gp in 6gp in 5gp in 4gp o u t7 gp o u t6 gp o u t5 gp o u t4 rs c r22 gpinirq gp in irq7 gp in irq6 gp in irq5 gp in irq4 gp in irq3 gp in irq2 gp in irq1 gp in irq0 rs c r23 gpinien gp in ie n 7gp in ie n 6gp in ie n 5gp in ie n 4gp in ie n 3gp in ie n 2gp in ie n 1gp in ie n 0rs c r24 gpinpol gp in p ol7 gp in p ol6 gp in p ol5 gp in p ol4 gp in p ol3 gp in p ol2 gp in p ol1 gp in p ol0 rs c r25 00 000 0 0 0 r26 00 000 0 0 0 r27 mode 00 0s e p irq 0 0 0 h os t = 0rs c r28 00 000 0 0 0 r29 00 000 0 0 0 r30 00 000 0 0 0 r31 00 000 0 0 0 note 1a: the acc (access) column indicates how the spi master can access the register. r = read, rc = read or clear, rsc = read, set, or clear. writing to an r register (read only) has no effect. writing a 1 to an rc bit (read or clear) clears the bit. writing a zero to an rc bit has no effect.
max3421e usb peripheral/host controller with spi interface 9 maxim integrated note 1b: in peripheral mode, the max3421e performs identically to the max3420e with the following enhancements: 1) r16 adds the pulsewid0 and pulsewid1 bits to control the int pulse width in edge interrupt mode (see figure 12.) these bits default to the max3420e setting of 10.6?. 2) r21 adds four more gpio bits. 3) r22 and r23 add general-purpose input pins to the interrupt system. r24 controls the edge polarity. 4) r27 controls the peripheral/host mode and the sepirq bit. 5) when [gpxb:gpxa] = [1:0] and the bit sepirq = 1 (r27 bit 4), the gpx output replaces the busact signal with a second irq pin dedicated to the gpin pin interrupts. table 2. max3421e register map in host mode (host = 1) (note 2) r eg name b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 a c c r0 0 0 0 0 0 0 0 0 r1 rcvfifo b 7b 6b 5b 4b 3b 2b 1b 0rs c r2 sndfifo b 7b 6b 5b 4b 3b 2b 1b 0rs c r3 0 0 0 0 0 0 0 0 r4 sudfifo b 7b 6b 5b 4b 3b 2b 1b 0rs c r5 0 0 0 0 0 0 0 0 r6 rcvbc 0b c 6bc 5bc 4bc 3bc 2b c 1b c 0rs c r7 sndbc 0b c 6bc 5bc 4bc 3bc 2b c 1b c 0rs c r8 00000 0 0 0 r9 00000 0 0 0 r10 00000 0 0 0 r11 00000 0 0 0 r12 00000 0 0 0 r13 usbirq 0v bu s irq n ov bu s irq 0 0 0 0 os c okirq rc r14 usbien 0v bu s ie n ov bu s ie 0 0 0 0 os c okie rs c r15 usbctl 00c h ip re s p wrd own 0 0 0 0 rs c r16 cpuctl p u ls e wid 1p u ls e wid 00 0 0 0 0 ie rs c r17 pinctl e p 3in ak e p 2in ak e p 0in ak fd u p s p iin tle v e lp os in tgp x bgp x ars c r18 revision 00010 0 1 1r r19 00000 0 0 0 r20 iopins1 gp in 3gp in 2gp in 1gp in 0gp o u t3 gp o u t2 gp o u t1 gp o u t0 rs c r21 iopins2 gp in 7gp in 6gp in 5gp in 4gp o u t7 gp o u t6 gp o u t5 gp o u t4 rs c r22 gpinirq gp in irq7 gp in irq6 gp in irq5 gp in irq4 gp in irq3 gp in irq2 gp in irq1 gp in irq0 rc r23 gpinien gp in ie n 7gp in ie n 6gp in ie n 5gp in ie n 4gp in ie n 3gp in ie n 2gp in ie n 1gp in ie n 0rs c r24 gpinpol gp in p ol7 gp in p ol6 gp in p ol5 gp in p ol4 gp in p ol3 gp in p ol2 gp in p ol1 gp in p ol0 rs c r25 hirq h x frd n irq fram e irq c on n irq s u s d n irq s n d bav irq rc v d av irq rs m re qirq bu s e v e n tirq rc r26 hien h x frd n ie fram e ie c on n ie s u s d n ie s n d bav ie rc v d av ie rs m re qie bu s e v e n tie rs c r27 mode d p p u lld n d m p u lld n d e lay is os e p irq s ofkae n ab h u bp re s p e e d h os t = 1rs c r28 peraddr 0b 6b 5b 4b 3b 2b 1b 0rs c r29 hctl s n d tog1 s n d tog0 rc v tog1 rc v tog0 s ig rs m bu s s am p le frm rs tbu s rs tls r30 hxfr h s is o ou tn in s e tu p e p 3e p 2e p 1e p 0ls r31 hrsl js tatu s ks tatu s s n d togrd rc v togrd h rs lt3 h rs lt2 h rs lt1 h rs lt0 r table 1. max3421e register map in peripheral mode (host = 0) (notes 1a, 1b) (continued)
max3421e usb peripheral/host controller with spi interface 10 maxim integrated max3421e tqfp (5mm x 5mm) top view 29 30 28 27 12 11 13 v l gpout0 gpout1 gpout2 gpout3 14 gpin7 v cc d+ d- xi gnd int 12 gpin2 4567 2324 22 20 19 18 gpin3 gpin4 ss sclk res gpout7 gnd vbcomp 3 21 31 10 gpin5 gpout6 32 9 gpin6 gpout5 gpin1 26 15 miso gpin0 25 16 mosi gpout4 gpx 8 17 xo + pin configurations note 2: the acc (access) column indicates how the spi master can access the register. r = read; rc = read or clear; rsc = read, set, or clear; ls = load-sensitive. writing to an r register (read only) has no effect. writing a 1 to an rc bit (read or clear) clears the bit. writing a zero to an rc bit has no effect. writing to an ls register initiates a host operation based on the contents of the register. max3421e tqfn (5mm x 5mm) top view of bottom leads 29 30 28 27 12 11 13 v l gpout0 gpout1 gpout2 gpout3 14 gpin7 v cc d+ d- xi gnd int 12 gpin2 4567 2324 22 20 19 18 gpin3 gpin4 ss sclk res gpout7 gnd vbcomp 3 21 31 10 gpin5 gpout6 32 9 gpin6 gpout5 gpin1 26 15 miso gpin0 25 16 mosi gpout4 gpx 8 17 xo + *exposed pad connected to ground *ep table 2. max3421e register map in host mode (host = 1) (note 2) (continued)
max3421e usb peripheral/host controller with spi interface 11 maxim integrated absolute maximum ratings electrical characteristics (v cc = +3v to +3.6v, v l = +1.4v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +3.3v, v l = +2.5v, t a = +25c.) (note 3) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd, unless otherwise noted.) v cc ......................................................................... -0.3v to +4v v l .............................................................................-0.3v to +4v vbcomp .................................................................-0.3v to +6v d+, d-, xi, xo ............................................-0.3v to (v cc + 0.3v) sclk, mosi, miso, ss, res, gpout7?pout0, gpin7?pin0, gpx, int ..........................-0.3v to (v l + 0.3v) continuous power dissipation (t a = +70?) 32-pin tqfn (derate 21.3mw/? above +70?) .......1702mw 32-pin tqfp (derate 13.1mw/? above +70?)........1047mw operating temperature range ...........................-40 c to +85c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150c lead temperature (soldering, 10s) .................................+300 c soldering temperature (reflow) .......................................+260 c parameter symbol conditions min typ max units dc characteristics supply voltage v cc v cc 3.0 3.3 3.6 v logic-interface voltage v l v l 1.4 3.6 v v cc supply current i cc continuously transmitting on d+ and d- at 12mbps, c l = 50pf on d+ and d- to gnd, connect = 0 45 ma v l supply current i l sclk toggling at 20mhz, ss = low, gpin7?pin0 = 0 2.35 10 ma v cc supply current during idle i ccid d+ = high, d- = low 8.7 15 ma v cc suspend supply current i ccsus connect = 0, pwrdown = 1 30 60 a v l s usp end s up p l y c urr ent i lsus connect = 0, pwrdown = 1 20 50 a logic-side i/o i load = +1ma v l - 0.4 i load = +5ma, v l < 2.5v (note 4) v l - 0.45 miso, gpout7?pout0, gpx, int output high voltage v oh i load = +10ma, v l 2.5v (note 4) v l - 0.4 v i load = -1ma 0.4 i load = -20ma, v l < 2.5v (note 4) 0.6 miso, gpout7?pout0, gpx, int output low voltage v ol i load = -20ma, v l 2.5v (note 4) 0.4 v sclk, mosi, gpin7?pin0, ss, res input high voltage v ih 2/3 x v l v sclk, mosi, gpin7?pin0, ss, res input low voltage v il 0.4 v sclk, mosi, ss, res input leakage current i il -1 +1 ? gp in 7gp in 0 p ul l up resi stor to v l r gpin 10 20 30 k transceiver specifications differential-receiver input sensitivity |v d+ - v d- | 0.2 v
max3421e usb peripheral/host controller with spi interface 12 maxim integrated electrical characteristics (continued) (v cc = +3v to +3.6v, v l = +1.4v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +3.3v, v l = +2.5v, t a = +25c.) (note 3) parameter symbol conditions min typ max units differential-receiver common- mode voltage 0.8 2.5 v single-ended receiver input low voltage v il 0.8 v single-ended receiver input high voltage v ih 2.0 v single-ended receiver hysteresis voltage 0.2 v d+, d- output low voltage v ol r l = 1.5k from d+ to 3.6v 0.3 v d+, d- output high voltage v oh r l = 15k from d+ and d- to gnd 2.8 3.6 v driver output impedance excluding external resistor (note 4) 2 7 11 d+ pullup resistor r ext = 33 1.425 1.5 1.575 k d+, d- pulldown resistor r ext = 33 14.25 15 15.75 k d+, d- input impedance 300 k esd protection (d+, d-, vbcomp) human body model 1? ceramic capacitors from vbcomp and v cc to gnd ?5 kv iec 61000-4-2 air-gap discharge 1? ceramic capacitors from vbcomp and v cc to gnd ?2 kv iec 61000-4-2 contact discharge 1? ceramic capacitors from vbcomp and v cc to gnd ? kv thermal shutdown thermal-shutdown low-to-high +160 ? thermal-shutdown high-to-low +140 ? crystal oscillator specifications (xi, xo) xi input high voltage 2/3 x v c c v cc v xi input low voltage 0.4 v xi input current 10 ? xi, xo input capacitance 3p f vbcomp comparator specifications vbcomp comparator threshold v th 1.0 2.0 3.0 v vbcomp comparator hysteresis v hys 375 mv vbcomp comparator input impedance r in 100 k
max3421e usb peripheral/host controller with spi interface 13 maxim integrated note 3: parameters are 100% production tested at t a = +25?. specifications over temperature are guaranteed by design. note 4: guaranteed by bench testing. limits are not production tested. note 5: at v l = 1.4v to 2.5v, derate all the spi timing characteristics by 50%. not production tested. note 6: the minimum period is derived from spi timing parameters. note 7: time-to-exit suspend is dependent on the crystal used. parameter symbol conditions min typ max units usb transmitter timing characteristics (full-speed mode) d+, d- rise time t rise c l = 50pf, figures 8 and 9 4 20 ns d+, d- fall time t fall c l = 50pf, figures 8 and 9 4 20 ns rise-/fall-time matching c l = 50pf, figures 8 and 9 (note 4) 90 110 % output-signal crossover voltage c l = 50pf, figures 8 and 9 (note 4) 1.3 2.0 v usb transmitter timing characteristics (host low-speed mode) d+, d- rise time t rise 200pf c l 600pf, figures 8 and 9 75 300 ns d+, d- fall time t fall 200pf c l 600pf, figures 8 and 9 75 300 ns rise-/fall-time matching 200p f c l 600p f, fi g ur es 8 and 9 80 120 % output-signal crossover voltage 200p f c l 600p f, fi g ur es 8 and 9 1.3 2.0 v spi bus timing characteristics (v l = 2.5v) (figures 10 and 11) (note 5) v l > 2.5v 38.4 s eri al c l ock ( sc lk) p eri od ( n ote 6) t cp v l = 1.4v 77.7 ns sclk pulse-width high t ch 17 ns sclk pulse-width low t cl 17 ns ss fall to miso valid t css 20 ns ss leading time before the first sclk edge t l 30 ns ss trailing time after the last sclk edge t t 30 ns data-in setup time t ds 5n s data-in hold time t dh 10 ns ss pulse high t csw 200 ns sclk fall to miso propagation delay t do 14.2 ns sclk fall to mosi propagation delay t di 14.2 ns sclk fall to mosi drive t on 3.5 ns ss high to mosi high impedance t off 20 ns suspend timing characteristics time-to-enter suspend pwrdown = 1 to oscillator stop 5 s time-to-exit suspend pwrdown = 1 to 0 to oscokirq (note 7) 3 ms timing characteristics ( v cc = +3v to +3.6v, v l = +1.4v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +3.3v, v l = +2.5v, t a = +25c.) (note 3 )
max3421e usb peripheral/host controller with spi interface 14 maxim integrated test circuits and timing diagrams figure 8. rise and fall times v ol v oh t rise t fall 90% 10% figure 9. load for d+/d- ac measurements max3421e d+ or d- test point 33 15k c l sclk ss mosi miso t ds t dh t cl t do t ch t t 8 1 2 9 10 16 t l t css t csw t cp high impedance high impedance figure 11. spi bus timing diagram (half-duplex mode, spi mode (0,0)) sclk mosi miso notes: 1) during the first 8 clocks cycles, the mosi pin is high impedance and the spi master drives data onto the mosi pin. setup and hold times are the same as for full-duplex mode. 2) for spi write cycles, the mosi pin continues to be high impedance and the external master continues to drive mosi. 3) for spi read cycles, after the 8th clock-falling edge, the max3421e starts driving the mosi pin after time t on . the external master must turn off its driver to the mosi pin before t on to avoid contention. propagation delays are the same as for the mosi pin in full-duplex mode. t ds t dh t cl t ch t di t off t t ss hi-z 8 1 2 9 10 16 t l t csw t on t cp high impedance high impedance figure 10. spi bus timing diagram (full-duplex mode, spi mode (0,0))
max3421e usb peripheral/host controller with spi interface 15 maxim integrated typical operating characteristics (v cc = +3.3v, v l = +3.3v, t a = +25?.) detailed description the max3421e contains digital logic and analog cir- cuitry necessary to implement a full-speed usb periph- eral or a full-/low-speed host compliant to usb specification rev 2.0. the max3421e is selected to operate as either a host or peripheral by writing to the host bit in the mode (r27) register. the max3421e features an internal usb transceiver with ?5kv esd protection on d+, d-, and vbcomp. a switchable 1.5k pullup resistor is provided on d+ and switchable 15k pulldown resistors are provided on both d+ and d-. any spi master can communicate with the max3421e through the spi slave interface that oper- ates in spi mode (0,0) or (1,1). an spi master accesses the max3421e by reading and writing to internal regis- ters. a typical data transfer consists of writing a first byte that sets a register address and direction with additional bytes reading or writing data to the register or internal fifo. in peripheral mode, the max3421e contains 384 bytes of endpoint buffer memory, implementing the following endpoints: ep0: 64-byte bidirectional control endpoint ep1: 2 x 64-byte double-buffered bulk/int out endpoint ep2: 2 x 64-byte double-buffered bulk/int in endpoint ep3: 64-byte bulk/int in endpoint the choice to use ep1, ep2, ep3 as bulk or inter- rupt endpoints is strictly a function of the endpoint descriptors that the spi master returns to the usb host during enumeration. in host mode, the max3421e contains 256 bytes of send and receive fifo memory: sndfifo: send fifo?ouble-buffered 64-byte fifo rcvfifo: receive fifo?ouble-buffered 64-byte fifo the host fifos can send setup, bulk, interrupt, and isochronous requests to a peripheral device, at full speed or low speed. the max3421e accommodates low-speed devices whether they are directly connected, or connected through a usb hub. because the max3421e does much of the host housekeeping, it is easy to program. the spi master does a typical host operation by setting the device address and endpoint, launching a packet, and waiting for a completion inter- rupt. then it examines transfer result bits to determine how the peripheral responded. it automatically gener- ates frame markers (full-speed sof packets or low- speed keep-alive pulses), and ensures that packets are dispatched at the correct times relative to these markers. the max3421e register set and spi interface is optimized to reduce spi traffic. an interrupt output pin, int, notifies the spi master when usb service is required; for exam- ple, when a packet arrives, a packet is sent, or the host suspends or resumes bus activity. double-buffered fifos eye diagram max3421e toc01 4 1 0 -1 01020304050607080 2 3 time (ns) d+ and d- (v)
max3421e usb peripheral/host controller with spi interface 16 maxim integrated help sustain bandwidth by allowing data to move concur- rently over usb and the spi interface. v cc power the usb transceiver and digital logic by apply- ing a positive 3.3v supply to v cc . bypass v cc to gnd with a 1.0? ceramic capacitor as close to the v cc pin as possible. v l v l acts as a reference level for the spi interface and all other digital inputs and outputs. connect v l to the sys- tem? logic-level power supply. internal level translators and v l allow the spi interface and all general-purpose inputs and outputs to operate at a system voltage between 1.4v and 3.6v. vbcomp the max3421e features a usb v bus detector input, vbcomp. the vbcomp pin can withstand input volt- ages up to 6v. bypass vbcomp to gnd with a 1.0? ceramic capacitor. vbcomp is internally connected to a voltage comparator to allow the spi master to detect (through an interrupt or checking a register bit) the presence or loss of power on v bus . vbcomp does not power any internal circuitry inside the max3421e. vbcomp is pulled down to ground with r in (see electrical characteristics ). vbcomp in peripheral mode vbcomp is internally connected to a voltage compara- tor so that the spi master can detect the presence or absence of v bus . according to the usb 2.0 specifica- tion, a self-powered peripheral must disconnect its 1.5k pullup resistor to d+ in the event that the host turns off bus power. the vbgate bit in the usbctl (r15) register provides the option for the max3421e internal logic to automatically disconnect the 1.5k resistor on d+. the vbgate and connect bits of usbctl (r15), along with the vbcomp comparator output (vbus_det), control the pullup resistor between v cc and d+ as shown in table 3 and the functional diagram. note that if vbgate = 1 and vbus_det = 0, the pullup resistor is disconnected regardless of the connect bit setting. if the device using the max3421e is bus powered (through a +3.3v regulator connected to v cc ), the max3421e vbcomp input can be used as a general-purpose input. see the applications information section for more details about this connection. vbcomp in host mode when using the max3421e in host mode, the presence of v bus does not need to be detected. in this case, the vbcomp input can be used as a general-purpose input. d+ and d- the internal usb full-/low-speed transceiver is brought out to the bidirectional data pins d+ and d-. these pins are ?5kv esd protected. connect d+ and d- to a usb b connector through 33 ?% series resistors. d+ and d- in peripheral mode in peripheral mode, the d+ and d- pins connect to a usb b connector through series resistors. a switchable 1.5k pullup resistor is internally connected to d+. d+ and d- in host mode in host mode, the d+ and d- pins connect to a usb a connector through series resistors. switchable 15k pulldown resistors are internally connected to d+ and d-. the dppulldn and dmpulldn bits in the mode (r27) register control the connection between d+ and d- to gnd. for host operation, set these bits to 1 to enable the pulldown resistors. a host interrupt bit called connirq alerts the spi master when a peripheral is attached or detached. xi and xo xi and xo connect an external 12mhz crystal to the internal oscillator circuit. xi is the crystal oscillator input, and xo is the crystal oscillator output. connect one side of a 12mhz 0.25% parallel resonant crystal to xi, and connect xo to the other side. connect load capacitors (20pf max) to ground on both xi and xo. xi can also be driven with an external 12mhz ?.25% clock. if driving xi with an external clock, leave xo unconnected. the external clock must meet the voltage characteristics depicted in the electrical character- istics table. internal logic is single-edge triggered. the external clock should have a nominal 50% duty cycle. table 3. internal pullup resistor control in peripheral mode connect vbgate vbus_det pullup 0 x x not connected 1 0 x connected 1 1 0 not connected 1 1 1 connected
max3421e usb peripheral/host controller with spi interface 17 maxim integrated res drive res low to put the max3421e into a chip reset. a chip reset sets all registers to their default states, except for pinctl (r17), usbctl (r15), and spi logic. all fifo contents are unknown during chip reset. bring the max3421e out of chip reset by driving res high. the res pulse width can be as short as 200ns. see the device reset section for a description of the resets available on the max3421e. int the max3421e int output pin signals when a usb event occurs that requires the attention of the spi mas- ter. int can also be configured to assert when any of the general-purpose inputs (gpin0?pin7) are activat- ed (see the gpin7?pin0 section for more details). the spi master must set the ie bit in the cpuctl (r16) register to activate int. when the ie bit is cleared, int is inactive (open for level mode, high for negative edge, low for positive edge). int is inactive upon power-up or after a chip reset (ie = 0). the int pin can be a push-pull or open-drain output. set the intlevel bit of the pinctl (r17) register high to program the int output pin to be an active-low level open-drain output. an external pullup resistor to v l is required for this setting. in level mode, the max3421e drives int low when any of the interrupt flags are set. if multiple interrupts are pending, int goes inactive only when the spi master clears the last active interrupt request bit (figure 12). the posint bit of the pinctl (r17) register has no effect on int in level mode. clear the intlevel bit to program int to be an edge active push-pull output. the active edge is programma- ble using the posint bit of the pinctl (r17) register. in edge mode, the max3421e produces an edge refer- enced to v l any time an interrupt request is activated, or when an interrupt request is cleared and others are pending (figure 12). set the posint bit in the pinctl (r17) register to make int active high, and clear the posint bit to make int active low. the pulsewid1 and pulsewid0 bits in the cpuctl (r16) register control the pulse width of int in edge mode as shown in table 4. gpin7?pin0 the spi master samples gpin3?pin0 states by read- ing bit 7 through bit 4 of the iopins1 (r20) register. gpin7?pin4 states are sampled by reading bit 7 through bit 4 of the iopins2 (r21) register. writing to these bits has no effect. three registers, operational in both peripheral and host mode, control eight interrupt requests from the gpin7?pin0 inputs. the gpinirq (r22) register con- tains the interrupt request flags for the eight gpin inputs. the gpinien (r23) register contains individual interrupt enable bits for the eight gpin interrupts. the gpinpol (r24) register controls the edge polarity for the eight gpin interrupts. the eight gpin interrupts are added into the max3421e interrupt system and appear on the int output pin if enabled and asserted. it is also possible to separate the gpin interrupts and make them available on the gpx output pin by setting sepirq = 1. this provides lower latency interrupt service since the source of the interrupt on the gpx output is known, and only the gpinirq register needs to be checked to determine the interrupt source. note that the gpinpol bits control the edge sensitivity of the gpin transitions as they set an internal ?nterrupt pending?flip-flop, not the int output pin. the int pin output characteristics are determined by the intlevel and posint register bits, as in the max3420e. if the gpx pin is configured as the gpin int pin, its output characteristics are the same as programmed for the int pin. table 4. pulse width of int output configured by pulsewid1 and pulsewid0 pulsewid1 pulsewid0 int pulse width (?) 0 0 10.6 0 1 5.3 1 0 2.6 1 1 1.3 clear first irq, second irq still active second irq active first irq active clear irq single irq , intlevel = 1 posint = x intlevel = 0 posint = 0 intlevel = 0 posint = 1 clear last pending irq (1) (2) int int int (1) width determined by time taken to clear the irq. (2) width determined by pulsewid1 and pulsewid0 bits in cpuctl (r16) register. figure 12. behavior of the int pin for different intlevel and posint bit settings
max3421e usb peripheral/host controller with spi interface 18 maxim integrated gpout7?pout0 the spi master controls the gpout3?pout0 states by writing to bit 3 through bit 0 of the iopins1 (r20) register. gpout7?pout4 states are controlled by writing to bit 3 through bit 0 of the iopins2 (r21) regis- ter. gpout7?pout0 logic levels are referenced to the voltage on v l . as shown in figure 13, reading the state of a gpout7?pout0 bit returns the state of the internal register bit, not the actual pin state. this is use- ful for doing read-modify-write operations to an output pin (such as blinking an led), since the load on the output pin does not affect the register logic state. gpx gpx is a push-pull output with a 4-way multiplexer that selects its output signal. the logic level on gpx is refer- enced to v l . the spi master writes to the gpxb and gpxa bits of pinctl (r17) register to select one of five internal signals as depicted in table 5. operate: this signal goes high when the max3421e is able to operate after a power-up or res reset. operate is active when the res input is high and the internal power-on-reset (por) is not asserted. operate is the default gpx output. vbus_det: vbus_det is the vbcomp comparator output. this allows the user to directly monitor the v bus status. busact: usb bus activity signal (active high). this signal is active whenever there is traffic on the usb bus. the busact signal is set whenever a sync field is detected. busact goes low during bus reset or after 32-bit times of j-state. register bit gpout write gpout read gpout pin figure 13. behavior of read and write operations on gpout3?pout0 full-speed time frame 1ms full-speed time frame 1ms sof usb packets gpx sof sof ~50% figure 14. gpx output in sof mode spi controller spi controller max3421e max3421e mosi miso mosi miso fdupspi = 0 (default) fdupspi = 1 figure 15. max3421e spi data pins for full-duplex (top) and half-duplex (bottom) operation table 5. gpx output state due to gpxb and gpxa bits gpxb gpxa gpx pin output 0 0 operate (default state) 0 1 vbus_det 1 0 busact/inirq* 1 1 sof * if sepirq = 1.
max3421e usb peripheral/host controller with spi interface 19 maxim integrated inirq: when the sepirq bit of the mode (r27) register is set high, the busact signal is removed from the int output and gpx is used as an irq output pin dedicated to gpin interrupts if gpx[b:a] = 10. in this mode, gpin interrupts appear only on the gpx pin, and do not appear on the int output pin. sof: a square wave with a positive edge that indicates the usb start-of-frame (figure 14). mosi (master-out, slave-in) and miso (master-in, slave-out) the spi data pins mosi and miso operate differently depending on the setting of a register bit called fdupspi (full-duplex spi). figure 15 shows the two configurations according to the fdupspi bit setting. in full-duplex mode (fdupspi = 1), the mosi and miso pins are separate, and the miso pin drives only when ss is low. in this mode, the first eight sclk edges (after ss = 0) clock the command byte into the max3421e on mosi, and 8 usb status bits are clocked out of the max3421e on miso. for an spi write cycle, any bytes following the command byte are clocked into the max3421e on mosi, and zeros are clocked out on miso. for an spi read cycle, any bytes following the command byte are clocked out of the max3421e on miso and the data on mosi is ignored. at the conclusion of the spi cycle ( ss = 1), the miso output tri-states. in half-duplex mode, the mosi pin is a bidirectional pin and the miso pin is tri-stated. this saves a pin in the spi interface. because of the shared data pin, this mode does not offer the 8 usb status bits (figures 6 and 7) as the command byte is clocked into the max3421e. the miso pin can be left unconnected in half-duplex mode. sclk (serial clock) the spi master provides the max3421e sclk signal to clock the spi interface. sclk has no low-frequency limit, and can be as high as 26mhz. the max3421e changes its output data (miso) on the falling edge of sclk and samples input data (mosi) on the rising edge of sclk. the max3421e ignores sclk transitions when ss is high. the inactive level of sclk may be low or high, depending on the spi operating mode (figure 16). ss (slave select) the max3421e spi interface is active only when ss is low. when ss is high, the max3421e tri-states the spi output pin and resets the internal max3421e spi logic. if ss goes high before a complete byte is clocked in, the byte-in-progress is discarded. the spi master can terminate an spi cycle after clocking in the first 8 bits (the command byte). this feature can be used in a full- duplex system to retrieve the usb status bits (figure 6 and 7) without sending or receiving spi data. applications information spi interface the max3421e operates as an spi slave device. a reg- ister access consists of the spi master first writing an spi command byte, followed by reading or writing the contents of the addressed register (see the register description section for more details). all spi transfers are msb first. the external spi master provides a clock signal to the max3421e sclk input. this clock fre- quency can be between dc and 26mhz. bit transfers ss miso mosi sclk mode 0,0 sclk mode 1,1 spi mode 0,0 or 1,1 *msb of next byte in burst mode (ss remains low) q7 q6 q5 q4 q3 d7 d6 d5 d4 d3 d2 d1 d0 * q2 q1 q0 * figure 16. spi clocking modes
max3421e usb peripheral/host controller with spi interface 20 maxim integrated occur on the positive edge of sclk. the max3421e counts bits and divides them into bytes. if fewer than 8 bits are clocked into the max3421e when ss goes high, the max3421e discards the partial byte. the max3421e spi interface operates without adjust- ment in either spi mode (cpol = 0, cpha = 0) or (cpol = 1, cpha = 1). no mode bit is required to select between the two modes since the interface uses the rising edge of the clock in both modes. the two clocking modes are illustrated in figure 16. note that the inactive sclk value is different for the two modes. figure 16 illustrates the full-duplex mode, where data is simultaneously clocked into and out of the max3421e. spi half- and full-duplex operation the max3421e can be programmed to operate in half- duplex (a bidirectional data pin) or full-duplex (one data-in and one data-out pin) mode. the spi master sets a register bit called fdupspi (full-duplex spi) to 1 for full-duplex, and 0 for half-duplex operation. half- duplex is the power-on default. full-duplex operation when the spi master sets fdupspi = 1, the spi inter- face uses separate data pins, mosi and miso to trans- fer data. because of the separate data pins, bits can be simultaneously clocked into and out of the max3421e. the max3421e makes use of this feature by clocking out 8 usb status bits as the command byte is clocked in. figure 17 shows the status bits clocked out in peripheral mode and figure 18 shows the status bits clocked out host mode. reading from the spi slave interface (miso) the spi master reads data from the max3421e slave interface using the following steps: 1) when ss is high, the max3421e is unselected and tri-states the miso output. 2) after driving sclk to its inactive state, the spi master selects the max3421e by driving ss low. the max3421e turns on its miso output buffer and places the first data bit (q7) on the miso output (figure 16). 3) the spi master simultaneously clocks the com- mand byte into the max3421e mosi pin, and usb status bits out of the max3421e miso pin on the rising edges of the sclk it supplies. the max3421e changes its miso output data on the falling edges of sclk. 4) after eight clock cycles, the master can drive ss high to deselect the max3421e, causing it to tri- state its miso output. the falling edge of the clock puts the msb of the next data byte in the sequence on the miso output (figure 16). 5) by keeping ss low, the master clocks register data bytes out of the max3421e by continuing to supply sclk pulses (burst mode). the master terminates the transfer by driving ss high. the master must ensure that sclk is in its inactive state at the beginning of the next access (when it drives ss low). in full-duplex mode, the max3421e ignores data on mosi while clocking data out on miso. writing to the spi slave interface (mosi) the spi master writes data to the max3421e slave interface through the following steps: 1) the spi master sets the clock to its inactive state. while ss is high, the master can drive the mosi input. 2) the spi master selects the max3421e by driving ss low and placing the first data bit to write on the mosi input. 3) the spi master simultaneously clocks the com- mand byte into the max3421e and usb status bits out of the max3421e miso pin on the rising edges of the sclk it supplies. the spi master changes its mosi input data on the falling edges of sclk. 4) after eight clock cycles, the master can drive ss high to deselect the max3421e. 5) by keeping ss low, the master clocks data bytes into the max3421e by continuing to supply sclk pulses (burst mode). the master terminates the transfer by driving ss high. the master must ensure that sclk is inactive at the beginning of the next access (when it drives ss low). in full-duplex mode, the max3421e outputs usb status bits on miso during the first 8 bits (the command byte), and sub- sequently outputs zeros on miso as the spi master clocks bytes into mosi. half-duplex operation the max3421e is put into half-duplex mode at power- on, or when the spi master clears the fdupspi bit. in half-duplex mode, the max3421e tri-states its miso pin and makes the mosi pin bidirectional, saving a pin in the spi interface. the miso pin can be left unconnect- ed in half-duplex operation. because of the single data pin, the usb status bits available in full-duplex mode are not available as the spi master clocks in the command byte. in half-duplex mode these status bits are accessed in the normal way, as register bits. the spi master must operate the mosi pin as bidirec- tional. it accesses a max3421e register as follows:
max3421e usb peripheral/host controller with spi interface 21 maxim integrated 1) the spi master sets the clock to its inactive state. while ss is high, the master can drive the mosi pin to any value. 2) the spi master selects the max3421e by driving ss low and placing the first data bit (msb) to write on the mosi input. 3) the spi master turns on its output driver and clocks the command byte into the max3421e on the rising edges of the sclk it supplies. the spi master changes its mosi data on the falling edges of sclk. 4) after eight clock cycles, the master can drive ss high to deselect the max3421e. 5) to write spi data, the spi master keeps its output driver on and clocks subsequent bytes into the mosi pin. to read spi data, after the eighth clock cycle the spi master tri-states its output driver and begins clocking in data bytes from the mosi pin. 6) the spi master terminates the spi cycle by return- ing ss high. figures 10 and 11 show timing diagrams for full- and half-duplex operation. usb serial-interface engine the serial-interface engine (sie) does most of the detailed work required by usb protocol: ss miso mosi sclk spi mode 0,0 (cpol = 0, cpha = 0) suspirq uresirq sudavirq in3bavirq in2bavirq reg4 reg3 reg2 reg1 reg0 0 dir ackstat out1davirq out0davirq in0bavirq x figure 17. spi port in full-duplex mode (peripheral mode) ss miso mosi sclk spi mode 0,0 (cpol = 0, cpha = 0) hxfrdnirq frameirq connirq susdnirq sndbavirq reg4 reg3 reg2 reg1 reg0 0 dir ackstat* rcvdavirq rsmreqirq buseventirq x *ackstat bit not used figure 18. spi port in full-duplex mode (host mode)
max3421e usb peripheral/host controller with spi interface 22 maxim integrated usb packet pid detection and checking crc check and generation automatic retries in case of errors usb packet generation nrzi data encoding and decoding bit stuffing and unstuffing usb error detection usb bus reset, suspend, and wake-up detection usb suspend/resume signaling automatic flow control (nak) pll an internal pll multiplies the 12mhz oscillator signal by four to produce an internal 48mhz clock. when the chip is powered down, the oscillator is turned off to conserve power. when repowered, the oscillator and pll require time to stabilize and lock. the oscokirq interrupt bit is used to indicate to the spi master that the clocking system is stable and ready for operation. the oscillator and pll can be turned off by setting the pwrdown bit in the usbctl (r15) register (see the suspend section). power management according to usb rev. 2.0 specification, when a usb host stops sending traffic for at least 3ms to a peripher- al, the peripheral must enter a power-down state called suspend. once suspended, the peripheral must have enough of its internal logic active to recognize when the host resumes signaling, or if enabled for remote wake- up, that the spi master wishes to signal a resume event. the following sections titled suspend and wakeup and usb resume describe how the spi mas- ter coordinates with the max3421e to accomplish this power management. suspend after 3ms of usb bus inactivity, a usb peripheral is required to enter the usb suspend state and draw no more than 500? of v bus current. the suspend state is handled differently depending on whether the max3421e is used as a host or as a peripheral. suspend in host mode in host mode, the max3421e suspends the bus by set- ting sofkaen = 0. this stops automatic generation of the 1ms frame signals (sof for full speed, keep-alive for low speed). suspend in peripheral mode in peripheral mode, after 3ms of usb bus inactivity, the max3421e sets the suspirq bit in the usbirq (r13) register and asserts the int output, if suspie = 1 and ie = 1. the spi master must do any necessary power- saving housekeeping and then set the pwrdown bit in the usbctl (r15) register. this instructs the max3421e to enter a power-down state, in which it does the following: stops the 12mhz oscillator keeps the int output active (according to the mode set in the pinctl (r17) register) monitors the usb d+ line for a low level monitors the spi port for any traffic note that the max3421e does not automatically enter a power-down state after 3ms of bus inactivity. this allows the spi master to perform any preshutdown tasks before it requests the max3421e to enter the power-down state by setting pwrdown = 1. wakeup and usb resume wakeup and usb resume are handled differently depending on whether the max3421e is used as a host or as a peripheral. wakeup and usb resume in host mode after a host has suspended the bus by setting sofkaen = 0, it can resume bus traffic in two ways: 1) the spi master initiates a host resume operation by setting the bit sigrsm = 1. the max3421e asserts the resume signaling for 20ms, and then asserts the buseventirq bit. the spi master then sets sofkaen = 1 to generate the 1ms frame markers that keep the peripheral alive. 2) the host recognizes a remote wakeup signal from a peripheral. the max3421e has an interrupt bit for this purpose called rsmreqirq (resume request irq). wakeup and usb resume in peripheral mode the max3421e can wake up in three ways while it is a peripheral in the power-down state: 1) the spi master clears the pwrdown bit in the usbctl (r15) register (this is also achieved by a chip reset). 2) the spi master signals a usb remote wakeup by setting the sigrwu bit in the usbctl (r15) regis- ter. when sigrwu = 1 the max3421e restarts the oscillator and waits for it to stabilize. after the oscil- lator stabilizes, the max3421e drives resume sig- naling (a 10ms k-state) on the bus. the max3421e times this interval to relieve the spi master of having to keep accurate time. the max3421e also ensures
max3421e usb peripheral/host controller with spi interface 23 maxim integrated that the resume signal begins only after at least 5ms of the bus idle state. when the max3421e fin- ishes its resume signaling, it sets the rwudnirq (remote wake-up done interrupt request) interrupt flag in the usbirq (r13) register. at this time the spi master should clear the sigrwu bit. 3) the host resumes bus activity. to enable the max3421e to wake up from host signaling, the spi master sets the hoscsten (host oscillator start enable) bit of the usbctl (r15) register. while in this mode, if the max3421e detects a 1 to 0 transi- tion on d+, the max3421e restarts the oscillator and waits for it to stabilize. device reset the max3421e has three reset mechanisms: power-on reset. this is the most inclusive reset (sets all internal register bits to a known state). chip reset. the spi master can assert a chip reset by setting the bit chipres = 1, which has the same effect as pulling the res pin low. this reset clears only some register bits and leaves others alone. usb bus reset. a usb bus reset is the least inclusive (clears the smallest number of bits). note: a power-on or chip reset clears the host bit and puts the max3421e into peripheral mode. power-on reset at power-on, all register bits except 3 are cleared. the following 3 bits are set to 1 to indicate that the in fifos are available for loading by the spi master (bav = buffer available): in3bavirq in2bavirq in0bavirq chip reset pulling the res pin low or setting chipres = 1 clears most of the bits that control usb operation, but keeps the spi and pin-control bits unchanged so the interface between the spi master and the max3421e is not dis- turbed. specifically: chipres is unchanged. if the spi master asserted this reset by setting chipres = 1, it removes the reset by writing chipres = 0. connect is unchanged, keeping the device connected if connect = 1. general-purpose outputs gpout7?pout0 are unchanged, preventing output glitches. the gpx output selector (gpxb, gpxa) is unchanged. the bits that control the spi interface are unchanged: fdupspi, intlevel, and posint. the bits that control power-down and wakeup behavior are unchanged: hoscsten, pwrdown, and sigrwu. all other bits except the three noted in the power-on reset section are cleared. note: the irq and ie bits are cleared using this reset. this means that firmware routines that enable interrupts should be called after a reset of this type. gpout7 gpout0 are left unchanged during chip reset. they are only cleared by an internal por. usb bus reset in peripheral mode when the max3421e detects 21.33? of se0, it asserts the uresirq bit, and clears certain bits. this reset is the least inclusive of the three resets. it maintains the bit states listed in the power-on reset and chip reset sections, plus it leaves the following bits in their previ- ous states: epfifo registers are unchanged. the gpout7?pout0 bits are unchanged. the ie bit is unchanged. uresie/irq and uresdnie/irq are unchanged, allowing the spi master to check the state of usb bus reset. the epfifo registers are left in their pre-usb bus reset states only for diagnostic purposes. their values should be considered invalid after a bus reset. the actual data in the fifos is never cleared. as with the chip reset, most of the interrupt request and interrupt enable bits are cleared, meaning that the device firmware must re-enable individual interrupts after a bus reset. the exceptions are the interrupts associated with the actual bus reset, allowing the spi master to detect the beginning and end of the host sig- naling usb bus reset. usb bus reset in host mode as a host, an spi master instructs the max3421e to generate a usb bus reset by setting the busrst bit in the hctl register (r29). the max3421e generates the correctly timed signal, and asserts the buseventirq bit in the hirq register (r25) at completion. crystal selection the max3421e requires a crystal with the following specifications: frequency: 12mhz 0.25%
max3421e usb peripheral/host controller with spi interface 24 maxim integrated c load : 18pf (max) c o : 7pf (max) drive level: 200? series resonance resistance: 60 (max) note: series resonance resistance is the resistance observed when the resonator is in the series resonant condition. this is a parameter often stated by quartz crys- tal vendors and is called r1. when a resonator is used in the parallel resonant mode with an external load capaci- tance, as is the case with the max3421e oscillator circuit, the effective resistance is sometimes stated. this effec- tive resistance at the loaded frequency of oscillation is: r1 x ( 1 + (c o / c load )) 2 for typical c o and c load values, the effective resis- tance can be greater than r1 by a factor of 2. max3421e in a bus-powered peripheral application figure 19 depicts the max3421e in a peripheral device that is powered by v bus . this configuration is advanta- geous because it requires no external power supply. v bus is specified from 4.75v to 5.25v, requiring a 3.3v regulator to power the max3421e. this diagram assumes that the microprocessor is powered by 3.3v as well, so the v l pin (logic-level reference voltage) is connected to v cc . therefore, the gpios (general-pur- pose inputs/outputs) are referenced to 3.3v. usb is a hot-plug system (v bus is powered when the device is plugged in), so it is good design practice to use a power-on reset circuit to provide a clean reset to the system when the device is plugged in. the max6349tl serves as an excellent usb regulator, since it has very low quiescent current and a por cir- cuit built in. because this design is bus powered, it is not necessary to test for the presence of v bus . in this case, the bus voltage-detection input, vbcomp, makes an excellent general-purpose input. the vbcomp input has two inter- rupts associated with it, vbusirq and novbusirq. these interrupts can detect both edges of any transitions on the vbcomp input. the configuration in figure 19 shows the spi interface using the maximum number of spi interface pins. the data pins, mosi and miso, are separate, and the max3421e supplies an interrupt signal through the int output pin to the ? to notify the ? when its attention is required. max3421e v cc v l xi xo int mosi miso sclk res d+ d- d+ d- vbcomp ss 0.1f gnd v bus 33 33 1.0f ceramic c xi c xo 12mhz 3.3v regulator max6349tl p 88 usb "b" connector gnd gpin gpout 4.7f gpio gpi figure 19. max3421e in a bus-powered peripheral application
max3421e usb peripheral/host controller with spi interface 25 maxim integrated max3421e in a self-powered application figure 20 shows a self-powered peripheral design in which the ? has its own power source. this is a com- mon configuration in battery-powered handheld devices. figure 20 also illustrates the spi interfacing with the minimum number of pins. this is achieved by using a single bidirectional data line and no interrupt pin connection. the max3421e register bit, fdupspi, configures the spi interface for bidirectional operation. although figure 20 shows v l = v cc , if the microcon- troller uses a different interface voltage (1.71v to 3.6v), this reference voltage can be connected to v l . the figure 20 circuit shows a connection from the max3421e gpx output to the microcontroller. gpx can be pro- grammed (see table 5) to connect the output of the inter- nal v bus comparator to the gpx output. this enables the microprocessor to detect a usb plug-in event even if the max3421e is put into its power-down state. the v bus detect input, vbcomp, is an important max3421e feature. because the ? is powered whether the usb device is plugged in or not, it needs some way to detect a plug-in event. a comparator inside the max3421e checks for a valid v bus connec- tion on vbcomp and provides a connect status bit to the ?. once connected, the ? can delay the logical connection to the usb bus to perform any required ini- tialization, and then connect by setting the connect bit to 1 in the max3421e register usbctl (r15). this connects the internal 1.5k resistor from d+ to 3.3v, to signal the host that a device has been plugged in. if a host turns off v bus while the device is connected, the usb rev. 2.0 specification requires that the device must not power its 1.5k pullup resistor connected to d+. the max3421e has two features to help service this event. first, the novbusirq bit indicates the loss of v bus . second, the ? can set a bit called vbgate (v bus gate) to instruct the max3421e to disconnect the pullup resistor anytime v bus goes away, regardless of the connect bit setting. max3421e in a host application figure 21 illustrates the max3421e operating as an embedded host. a host supplies v bus power to a peripheral; therefore, this circuit requires an external 5v supply. a circuit that provides power to external devices should include power protection (the max4793, for example, which limits current from 300ma to 400ma) to ensure that the circuit can contin- ue to operate if the plugged-in device causes an over- current condition. the flag indicator of the overcurrent switch connects to one of the eight max3421e gpin max3421e v cc v l xi xo int mosi miso sclk res d+ d- d+ d- vbcomp ss 0.1f gnd v bus 33 33 1.0f ceramic 1.0f ceramic c xi c xo 12mhz p 88 usb "b" connector gnd gpin gpout gpio gpx n.c. n.c. +3.3v figure 20. max3421e in a self-powered peripheral application
max3421e usb peripheral/host controller with spi interface 26 maxim integrated inputs, and the gpx pin is configured to serve as a sec- ond max3421e interrupt pin that activates only when a gpin pin changes state. one of the eight gpout pins turns the v bus switch on and off. seven max3421e gpin and gpout pins are available to the system. short-circuit protection the max3421e withstands v bus shorts to d+ and d- on the usb connector side of the 33 series resistors. esd protection d+, d-, and vbcomp possess extra protection against static electricity to protect the devices up to ?5kv. the esd structures withstand high esd in all operating modes: normal operation, suspend mode, and powered down. vbcomp and v cc require 1? ceramic capacitors connected to ground as close to the pins as possible. d+, d-, and vbcomp provide protection to the following limits: ? ?5kv using the human body model ? ?kv using the contact discharge method specified in iec 61000-4-2 ? ?2kv using the iec 61000-4-2 air-gap method esd test conditions esd performance depends on a variety of conditions. contact maxim for a reliability report that documents test setup, test methodology, and test results. human body model figure 22 shows the human body model, and figure 23 shows the current waveform generated when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of inter- est, which then discharges into the test device through a 1.5k resistor. iec 61000-4-2 the iec 61000-4-2 standard covers esd testing and performance of finished equipment. it does not specifi- cally refer to integrated circuits. the major difference between tests done using the human body model and iec 61000-4-2 is a higher peak current in iec 61000-4- 2, due to lower series resistance. hence, the esd with- stand voltage measured to iec 61000-4-2 generally is lower than that measured using the human body model. figure 24 shows the iec 61000-4-2 model. the max3421e v cc v l int mosi miso sclk d+ d- d+ d- vbcomp ss gnd v bus 33 33 5v switch with current limit and oc detect p usb "a" connector gnd 4.7f 5v xi xo c xi c xo 12mhz out in gpout gpin on flag 3.3v regulator with por 1.0f ceramic 0.1f gpx v cc gnd int1 int2 res figure 21. max3421e in a host application
max3421e usb peripheral/host controller with spi interface 27 maxim integrated contact discharge method connects the probe to the device before the probe is charged. the air-gap discharge test involves approaching the device with a charged probe. figure 23. human body model current waveform i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amperes figure 22. human body esd test models charge-current- limit resistor discharge resistance storage capacitor c s 100pf r c 1m r d 1.5k high- voltage dc source device under test figure 24. iec 61000-4-2 esd test model charge-current- limit resistor discharge resistance storage capacitor c s 150pf r c 50m to 100m r d 330 high- voltage dc source device under test chip information process: bicmos package information for the latest package outline information and land patterns (foot- prints), go to www.maximintegrated.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 32 tqfp h32+1 21-0110 90-0149 32 tqfn-ep t3255+4 21-0140 90-0012
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 28 ________________________________maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max3421e usb peripheral/host controller with spi interface revision history revision number revision date description pages changed 3 7/07 changes to pin description, addition of text 5, 25, 28?1 4 7/13 updated lead-free packaging info, pin description, register tables , absolute maximum ratings 1, 6, 8, 9, 10

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