91912hkpc 20120905-s00001 no. a1419-1/8 http://onsemi.com semiconductor components industries, llc, 2013 july, 2013 LC79401KNE overview the LC79401KNE is a 80-outputs segment driver lsi fo r graphic dot-matrix liquid crystal display systems. the LC79401KNE latches 80 bits of display data sent from a controller using a 4-bit parallel transfer technique and generates lcd drive signals. when combined as a kit with common driver, either the lc79430kne (qip100e), the LC79401KNE can drive large screen lcd panels. features ? incorporates lcd drive circuits for 80 bits of display. ? supports display duties from 1/64 to 1/256 ? the provision of a chip disable pin supports power reduction in large-scale panels. ? allows external provision of the bias power supply ? operating supply voltage/operating temperature v dd (logic block) : 2.7 to 5.5v/-20 to +85 c v dd -v ee (lcd block) : 12 to 32v/-20 to +85 c ? data transfer clock : 6.0mhz (max ), bidirectional shifting supported ? data input : 4-bit parallel input ? cmos process ? 100-pin flat plastic package (qip100e) ordering number : ena1419 cmos lsi dot-matrix lcd drivers
LC79401KNE no. a1419-2/8 specifications absolute maximum ratings at ta = 25 2 c, v ss = 0v parameter symbol conditions ratings unit maximum supply voltage (logic) v dd max -0.3 to +7.0 v maximum supply voltage (lcd) v dd -v ee max *1 0 to 35 v maximum input voltage v i max -0.3 to v dd +0.3 v storage temperature tstg -40 to +125 c note * 1 v dd v1 > v3 > v4 > v ee , v dd -v3 7v, v4-v ee 7v allowable operating ranges at ta = -20 to +85 c, v ss = 0v parameter symbol conditions min typ max unit supply voltage (logic) v dd 2.7 5.5 v supply voltage (lcd) v dd -v ee *2, 3 12 32 v input high level voltage v ih di1 to di4, cp, load, cdi, r/l, m, dispoff 0.8v dd v input low level voltage v il di1 to di4, cp, load, cdi, r/l, m, dispoff 0.2v dd v cp shift clock f cp cp 6.0 mhz cp pulse width t wc cp 50 ns load pulse width t wl load 50 ns setup time t setup di1 to di4 cp 30 ns v dd =2.7 to 4.5v 40 ns hold time t hold di1 to di4 cp v dd =4.5 to 5.5v 30 ns cp load t cl cp load 80 ns t lc1 load cp 110 ns v dd =2.7 to 4.5v 30 ns load cp t lc2 load cp v dd =4.5 to 5.5v 15 ns cp and load rise time t r cp, load *4 ns cp and load fall time t f cp, load *4 ns note * 2 v dd v1 > v3 > v4 > v ee , v dd -v3 7v, v4-v ee 7v * 3 when the power is turned on, either the logic system power must be turned on before the lcd drive system power or else they must both be turned on at the same time. when the power is turned off, either the lcd drive system power must be turned off before the logic system power, or else both must be turned off at the same time. * 4 the cp and load rise time (t r ) and the cp and load fall time (t f ) must satisfy equations (1) and (2) below at the same time. (1) t r , t f < 1 2f cp - t wc (2) t r , t f < 50ns stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LC79401KNE no. a1419-3/8 electrical characteristics at ta = 25 2 c, v dd = 2.7 to 5.5v parameter symbol conditions min typ max unit input high level current i ih v in =v dd , load, cp, cdi, r/l, di1 to di4, m, dispoff 1 a input low level current i il v in =v ss , load, cp, cdi, r/l, di1 to di4, m, dispoff -1 a output high level voltage v oh i oh =-400 a, cdo v dd -0.4 v output low level voltage v ol i ol =400 a, cdo 0.4 v r on (1) v dd -v ee =30v, ? v de -v o ? =0.5v: o1 to o80 *5 0.6 1.5 k driver on resistance r on (2) v dd -v ee =20v, ? v de -v o ? =0.5v: o1 to o80 *5 0.7 2.0 k standby current drain i st cdi=v dd , v dd -v ee =30v, cp=6.0mhz, output unloaded: v ss 200 a operating current drain i ss *6 v dd -v ee =30v, cp=6mhz, load=14khz, m=35hz: v ss 4.0 ma i ee *7 v dd -v ee =30v, cp=6mhz, load=14khz, m=35hz: v ee 0.5 ma input capacitance c i f=6.0mhz ; cp 8 pf note * 5 v de = one of v1, v3, v4 or v ee , v1 = v dd , v3 = 15/17 (v dd -v ee ), v4 = 2/17 (v dd -v ee ) * 6 i ss is the current flowing from v dd to v ss * 7 i ee is the current flowing from v dd to v ee switching characteristics at ta = 25 2 c, v ss = 0v, v dd = 2.7 to 5.5v parameter symbol conditions min typ max unit v dd =2.7 to 4.5v 100 ns output delay time 1 t d1 load=15pf: cdo v dd =4.5 to 5.5v 80 ns v dd =2.7 to 4.5v 100 ns output delay time 2 t d2 load=15pf: cdo v dd =4.5 to 5.5v 80 ns
LC79401KNE no. a1419-4/8 package dimensions unit:mm (typ) 3151a pin assignment top view sanyo : qip100e(14x20) 20.0 23.2 14.0 17.2 0.15 0.8 (2.7) 3.0max 0.1 0.3 0.65 (0.58) 130 80 51 31 50 100 81 LC79401KNE o50 o49 o48 o47 o46 o45 o44 o43 o42 o41 o40 o39 o38 o37 o36 o35 o34 o33 o32 o31 o1 o2 o3 o4 o5 o6 o7 o8 o9 o10 o11 o12 o13 o14 o15 o16 o17 o18 o19 o20 o21 o22 o23 o24 o25 o26 o27 o28 o29 o30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 49 47 48 46 45 44 42 43 41 40 39 37 38 36 35 34 32 33 31 50 o80 o79 o78 o77 o76 o75 o74 o73 o72 o71 o70 o69 o68 o67 o66 o65 o64 o61 o60 o59 o58 o57 o56 o55 o54 o53 o52 o51 o62 o63 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 82 84 83 85 86 87 89 88 90 91 92 94 93 95 96 97 99 98 100 81 cdi v1 v3 v4 v ee m load v ss dispoff v dd r/l nc nc nc di4 di3 di2 di1 cp cdo
LC79401KNE no. a1419-5/8 equivalent circuit block diagram o1 o2 o3 o79 o80 v1 v3 v4 v ee m r/l cp cdo v ss v dd load cdi address decoder 4 bits data bus interface level shifter (80 bits) 2nd latch (80 bits) 4 level lcd drive circuit (80 bits) 80 1st latch (80 bits) 80 80 4 20 address counter (5bits) chip disable & latch control di4 di3 di2 di1 shift control dispoff
LC79401KNE no. a1419-6/8 pin function pin no symbol i/o function 90 v dd 88 v ss 85 v ee supply v dd -v ss : logic power supply v dd -v ee : lcd drive circuit power supply 82 v1 83 v3 84 v4 supply lcd drive level power supply v1,v ee : selected level v3,v4 : unselected level 99 cp i display data acquisition clock (falling edge trigger) 87 load i display data latch clock (falling edge trigger) the display data lcd drive signal is output on the falling edge. 95 96 97 98 di4 di3 di2 di1 i display data lcd drive output lcd display h selected level on l unselected level off 91 r/l i control pin that inverts the data output destination number of clock r/l data input 1 2 3 ? ? ? 18 19 20 di1 o77 o73 o69 ? ? ? o9 o5 o1 di2 o78 o74 o70 ? ? ? o10 o6 o2 di3 o79 o75 o71 ? ? ? o11 o7 o3 l di4 o80 o76 o72 ? ? ? o12 o8 o4 di1 o4 o8 o12 ? ? ? o72 o76 o80 di2 o3 o7 o11 ? ? ? o71 o75 o79 di3 o2 o6 o10 ? ? ? o70 o74 o78 h di4 o1 o5 o9 ? ? ? o69 o73 o77 86 m i lcd drive output alternation signal 81 cdi i chip disable pin high level : data is not acquired. low level : data is acquired 100 cdo o connect to the cdi pin on the next chip when cascade connection is used. 89 dispoff i input that controls the o1 to o80 output pins. during periods when this pin is low, the o1 to o80 output pins out put the v1 level. see the truth table. 1 to 80 o1 to o80 o lcd drive outputs the output level are determined by the combination of the output the data, the m signal, and the dispoff pin as shown in the table. m q dispoff output l l h v3 l h h v1 h l h v4 h h h v ee * * l v1 note : don?t care (fixed at high or low) 92 nc 93 nc 94 nc - must be left open.
LC79401KNE no. a1419-7/8 application example (LC79401KNE/lc79430kne) r/l seg318 seg319 seg320 seg1 dio1 dio80 v dd v ss v ee seg2 seg3 com240 com239 com238 com3 lcd panel 240 320 1/240 duty power supply circuit case of 1/n bias com2 com1 lc79430kne #1 m rs/ls cp mode dmin v1 v2 v5 dispoff di1 to di4 o1 to o80 o1 to o80 o1 to o80 o1 to o80 o1 to o80 LC79401KNE #4 LC79401KNE #2 LC79401KNE #1 m load cp v1 v3 v4 v ee v ss v dd cdi v ee v ss v dd cdi v ee v ss v dd cdi cdo cdo cdo r/l dispoff di1 to di4 m load cp v1 v3 v4 controller flm m load gnd v dd v ee r r cp di1 to di4 dispoff dispoff dio1 dio80 v dd v ss v ee lc79430kne #3 m rs/ls cp mode dmin v1 v2 v5 dispoff r/l dispoff di1 to di4 m load cp v1 v3 v4 + - + - r (n-4)r r v1 v2 v3 v4 v5 + - + -
LC79401KNE no. a1419-8/8 switching characteristics diagram ps 0.8v dd 0.2v dd 0.8v dd 0.2v dd 0.8v dd 0.2v dd 0.2v dd 0.8v dd 0.8v dd 0.2v dd t lc2 t r t wc t wc t f t setup t hold t r t wl t f t cl t lc1 t d1 t d2 cp di1-di4 load cp cdo on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.
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