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| MON35W42 hardware monitoring ic with thermal diode interface features !" monitoring items - 3 thermal inputs from remote thermistors or 2n3904 npn-type transistors or pentium ? ii (deschutes) thermal diode output - 9 voltage inputs - typical for vcore, +3.3v, +12v, -12v, +5v, -5v, +5v vsb, vbat, and one reserved - 3 fan speed monitoring inputs - case open detection input - watchdog comparison of all monitored values - programmable hysteresis and setting points (alarm thresholds) for all monitored items !" action enabling - beep tone warning - 4 pwm (pulse width modulation) outputs for fan speed control (3 are mux optional); up to 3 sets of fan speed monitoring and control. - issue nsmi, novt, ngpo signals to activate system protection - warning signal pop-up for application software !" general - isa and i 2 c serial bus interface - 5 vid input pins for cpu vcore identification (for pentium ? ii) - initial power fault beep (for +3.3v, vcore) - master reset input to MON35W42 - independent power plane of digital vcc and analog vcc (inputs to ic) - 3 pins (ia0, ia1, ia2) to provide selectable address setting for application of multiple devices (up to 8 devices) wired through i 2 c interface - intel ? ldcm (dmi driver 2.0) support - acer adm (dmi driver 2.0) support - smsc hardware monitoring application software (hardware doctor) support, for both windows 95/98 and windows nt 4.0/5.0 - input clock rate optional for 24, 48, 14.318 mhz - 5v vcc operation !" package - 48 pin tqfp
2 general description the MON35W42 is an enhanced version of the mon35w41 hardware status monitoring ic. the MON35W42 can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for the stability and proper operation of high-end computer systems. MON35W42 provides both isa and i 2 c serial bus interface. an 8-bit analog-to-digital converter (adc) is contained within the MON35W42. the MON35W42 can simultaneously monitor 9 analog voltage inputs, 2 fan tachometer inputs, 3 remote temperature and 1 case-open detection signal. the remote temperature sensing can be performed by thermistors, or 2n3904 npn-type transistors, or directly from intel ? deschutes cpu thermal diode output. the MON35W42 provides: 4 pwm (pulse width modulation) outputs for the fan speed control; beep tone output for audio warning and nsmi, novt, and ngpo signals for system protection events. with application software such as the intel ? ldcm (landesk client managemet software, the user can read all the monitored parameters of system from time to time. and a pop-up warning can also be activated when the monitored item drifts out of the proper/preset range. also the user can set the upper and lower limits (alarm thresholds) of these monitored parameters and activate programmable and maskable interrupts. an optional beep tone can be used as a warning signal when the monitored parameter is out of the preset range. additionally, 5 vid inputs are provided to read the vid of cpu (i.e. pentium ? ii) if applicable. this provides automatic correction of the vcore voltage. the MON35W42 uniquely provides an optional feature: early stage (before bios is loaded) beep warning. this is to detect if a fatal condition is present --- vcore or +3.3v voltage fail, and the system can not boot up. there are 3 specific pins to provide selectable address settings for applications using multiple devices (up to 8 devices) wired through the i 2 c interface. 3 table of contents features....................................................................................................................... ..................... 1 general description ............................................................................................................ ........ 2 table of contents.............................................................................................................. ........... 3 key specifications ............................................................................................................. .................. 5 pin configuration .............................................................................................................. ............ 5 pin description................................................................................................................ ................ 6 description of pin functions ................................................................................................... .6 functional description ......................................................................................................... ............... 9 general description ............................................................................................................ ............... 9 access interface ............................................................................................................... ................. 9 analog inputs .................................................................................................................. ................. 16 fan speed count and fan speed control ..................................................................................... 19 temperature measurement machine ............................................................................................... 2 1 registers and ram.............................................................................................................. ......... 25 address register (port x5h).................................................................................................... ......... 25 data register (port x6h) ....................................................................................................... ........... 26 configuration register ! index 40h ................................................................................................ 27 interrupt status register 1 ! index 41h........................................................................................... 28 interrupt status register 2 ! index 42h.......................................................................................... 28 nsmi mask register 1 ! index 43h................................................................................................. 29 nsmi mask register 2 ! index 44h................................................................................................. 29 reserved register ! index 45h ...................................................................................................... 30 chassis clear register -- index 46h ............................................................................................ .... 30 vid/fan divisor register ! index 47h ............................................................................................ 30 serial bus address register ! index 48h....................................................................................... 31 value ram ! index 20h- 3fh or 60h - 7fh (auto-increment) ......................................................... 31 voltage id (vid4) & device id -- index 49h ..................................................................................... 32 temperature 2 and temperature 3 serial bus address register--index 4ah.................................. 33 pin control register -- index4bh ............................................................................................... ...... 33 nirq/novt property select -- index 4ch ........................................................................................ 3 4 fan in/out and beep/ngpo control register -- index 4dh......................................................... 35 register 50h ~ 5fh bank select -- index 4eh.................................................................................. 36 smsc vendor id -- index 4fh .................................................................................................... ..... 36 smsc test register -- index 50h - 55h (bank 0)............................................................................ 37 beep control register 1-- index 56h (bank 0) ................................................................................ 37 beep control register 2-- index 57h (bank 0) ................................................................................ 38 chip id -- index 58h (bank 0) .................................................................................................. ........ 38 reserved register -- index 59h (bank 0)....................................................................................... . 39 pwmout2 control -- index 5ah (bank 0) ....................................................................................... 39 pwmout1 control -- index 5bh (bank 0) ....................................................................................... 40 pwmout1/2 clock select -- index 5ch (bank 0)............................................................................ 41 vbat monitor control register -- index 5dh (bank 0)..................................................................... 41 pwmout3 control -- index 5eh (bank 0) ....................................................................................... 42 pwmout4 control -- index 5fh (bank 0) ....................................................................................... 42 temperature sensor 2 temperature (high byte) register - index 50h (bank 1) ............................. 43 4 temperature sensor 2 temperature (low byte) register - index 51h (bank 1).............................. 43 temperature sensor 2 configuration register - index 52h (bank 1) ............................................... 44 temperature sensor 2 hysteresis (high byte) register - index 53h (bank 1)................................. 44 temperature sensor 2 hysteresis (low byte) register - index 54h (bank 1).................................. 45 temperature sensor 2 over-temperature (high byte) register - index 55h (bank 1) ..................... 45 temperature sensor 2 over-temperature (low byte) register - index 56h(bank 1) ....................... 46 temperature sensor 3 temperature (high byte) register - index 50h (bank 2) ............................. 46 temperature sensor 3 temperature (low byte) register - index 51h (bank 2).............................. 46 temperature sensor 3 configuration register - index 52h (bank 2) ............................................... 47 temperature sensor 3 hysteresis (high byte) register - index 53h (bank 2)................................. 47 temperature sensor 3 hysteresis (low byte) register - index 54h (bank 2).................................. 48 temperature sensor 3 over-temperature (high byte) register - index 55h (bank 2) ..................... 48 temperature sensor 3 over-temperature (low byte) register - index 56h(bank 2) ....................... 49 interrupt status register 3 -- index 50h (bank4) ............................................................................ 49 nsmi mask register 3 -- index 51h (bank 4)................................................................................. 50 beep control register 3-- index 53h (bank 4) ................................................................................ 50 reserved register -- index 54h--58h ............................................................................................ ... 51 real time hardware status register i -- index 59h (bank 4) .......................................................... 51 real time hardware status register ii -- index 5ah (bank 4)......................................................... 52 real time hardware status register iii -- index 5bh (bank 4)........................................................ 52 pwmout3/4 clock select -- index 5ch (bank 4)............................................................................ 53 value ram 2 ! index 50h - 5ah (auto-increment) (bank 5).......................................................... 53 smsc test register - index 50h (bank 6) ....................................................................................... 5 3 specifications ................................................................................................................. .............. 54 absolute maximum ratings ....................................................................................................... ...... 54 dc characteristics ............................................................................................................. .............. 54 ac characteristics............................................................................................................. ..... 56 isa read/write interface timing ................................................................................................ ..... 56 package dimensions............................................................................................................. ....... 58 5 key specifications "# voltage monitoring accuracy $ 1% (max) "# monitoring temperature range and accuracy - 40 % c to +120 % c $ 3 % c (max) "# supply voltage 5v "# operating supply current 5 ma typ. "# adc resolution 8 bits pin configuration MON35W42 vref vtin3/piitd3 vtin2piitd2 vtin1piitd1 vid0 novt ardmsel nsmi sa2/ia2 sa1/ia1 sa0/ia0 ncs 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 vid2 pwmtout1 sda scl fan1io fan2io fan3i0/pwmout2 vid4 caseopen mr gndd vcc 1 2 3 4 5 6 7 8 9 10 11 12 nior niow clkin d7 d6 d5 d4 d3 d2 d1/pwmout4 d0/pwmout3 vid1 36 35 34 33 32 31 30 29 28 27 26 25 vcorea vinr0 +3.3vin +5vin +12vin -12vin vbat 5vsb -5vin gnda beep/ngpo vid3 6 pin description i/o 12t - ttl level bi-directional pin with 12 ma source-sink capability i/o 12ts - ttl level and schmitt trigger out 12 - output pin with 12 ma source-sink capability aout - output pin (analog) od 12 - open-drain output pin with 12 ma sink capability in t - ttl level input pin in ts - ttl level input pin and schmitt trigger ain - input pin (analog) description of pin functions pin name pin no. type description nior 1 in ts an active low standard isa bus i/o read control. niow 2 in ts an active low standard isa bus i/o write control. clkin 3 in t system clock input. can select 48mhz or 24mhz or 14.318mhz. the default is 24mhz. d7~d2 4-9 i/o 12t bi-directional isa bus data lines. d0 corresponds to the low order bit, with d7 the high order bit. these pins are activated if pin adrmsel=0. d1/ pwmout4 10 i/o 12t out 12t bi-directional isa bus data lines. this pin is activated if pin adrmsel=0. /fan speed control pwm output. this pin is activated if pin adrmsel=1. d0/ pwmout3 11 i/o 12t out 12t bi-directional isa bus data lines. this pin is activated if pin adrmsel=0. /fan speed control pwm output. this pin is activated if pin adrmsel=1. vid1 12 in t voltage supply readouts from p6. this value is read in the vid/fan divisor register. v cc (+5v) 13 power +5v v cc power. bypass with the parallel combination of 10 & f (electrolytic or tantalum) and 0.1 & f (ceramic) bypass capacitors. gndd 14 dground internally connected to all digital circuitry. mr 15 in ts master reset input. ncaseopen 16 in t case open detection. an active low input from an external device when the case is opened. this signal can be latched if vbat is connect to a battery, even if the MON35W42 is power off. vid4 17 in t voltage supply readouts from p6. this value is read in the bit <0> of device id register. fan3io/ pwmout2 18 i/o 12t 0v to +5v amplitude fan tachometer input. / fan speed control pwm output. 7 pin name pin no. type description fan2io-fan1io 19-20 i/o 12t 0v to +5v amplitude fan tachometer input / fan on-off control output. these multi-functional pins can be programmable input or output. scl 21 in ts serial bus clock. sda 22 i/o 12ts serial bus bi-directional data. pwmout1 23 out 12t fan speed control pwm output. vid2 24 in t voltage supply readouts from p6. this value is read in the vid/fan divisor register. vid3 25 in t voltage supply readouts from p6. this value is read in the vid/fan divisor register. beep/ngpo 26 od 48 beep (default) / general purpose output this multi-functional pin is programmable. gnda 27 aground internally connected to all analog circuitry. the ground reference for all analog inputs. -5vin 28 ain 0v to 4.096v fsr analog inputs. 5vsb 29 ain 0v to 4.096v fsr analog inputs. vbat 30 ain 0v to 4.096v fsr analog inputs. (this pin should be connected to a 3v battery.) -12vin 31 ain 0v to 4.096v fsr analog inputs. +12vin 32 ain 0v to 4.096v fsr analog inputs. +5vin 33 ain this pin is analog vcc and connects internal monitor channel in3 with fixed scale. +3.3vin 34 ain 0v to 4.096v fsr analog inputs. vinr0 35 ain 0v to 4.096v fsr analog inputs. vcorea 36 ain 0v to 4.096v fsr analog inputs. vref 37 aout reference voltage. vtin3 / piitd3 38 ain thermistor 3 terminal input.(default) / pentium ? ii diode 3 input. this multi-functional pin is programmable. vtin2 / piitd2 39 ain thermistor 2 terminal input. (default)/ pentium ? ii diode 2 input. this multi-functional pin is programmable. vtin1 / piitd1 40 ain thermistor 1 terminal input. (default)/ pentium ? ii diode 1 input. this multi-functional pin is programmable. vid0 41 in t voltage supply readouts from p6. this value is read in the vid/fan divisor register. novt 42 od 12t over temperature shutdown output. adrmsel 43 in t pin 45--47 mode selection. 0 = the 3 lowest order bits of isa address bus.(default, internal pull-down 47k ohm) 1 = 7 bit i 2 c address setting pin.(bit2 - bit0) 8 pin name pin no. type description nsmi 44 od 12 system management interrupt (open drain). this output is enabled when bit 1 in the configuration register is set to 1. the default state is disabled. sa2-sa0 ia2,ia1,ia0 45-47 in t in t the three lowest order bits of the 16-bit isa address bus. a0 corresponds to the lowest order bit. (default, when ardmsel =0 or left open ) the hardware setting pin of 7 bit i 2 c serial address bit2, bit1 and bit0. (when ardmsel =1) ncs 48 in t chip select input from an external decoder, which decodes high order address bits on the isa address bus. this is an active low input. 9 functional description general description the MON35W42 provides 7 analog positive inputs, 3 fan speed monitors, up to 4 sets of fan pwm (pulse width modulation) control, 3 thermal inputs from remote thermistors or 2n3904 transistors or pentium ? ii (deschutes) thermal diode outputs, case open detection and beep function output. when the monitored value exceed the set limit value for voltage, temperature, or fan counter, the beep output can be generated. once the monitor function on the chip is enabled, the watch dog machine monitors each function and stores the values. if the monitored value exceeds the limit value, the interrupt status is set to 1and an interrupt can be generated. access interface the MON35W42 provides two interfaces for the microprocessor to read/write internal registers. isa interface the isa bus can be used to access the internal registers of the MON35W42. this uses an index register and data register to access the internal registers. the upper address bits of the isa bus (bits15:3) must be externally decoded for the chip select (ncs), the recommended address is 290h-297h. the chip then uses the lower three isa address bits (bits 2:0) to decode the index and data registers. these two i/o registers are described as following: port 295h: index register. port 296h: data register the register structure is shown in figure 1. 10 figure 1 ? isa interface access i 2 c interface the second interface uses the i 2 c serial bus. the MON35W42 uses three serial bus addresses. the first address defined at cr[48h] can read/write all registers excluding bank 1 and bank 2 temperature sensor 2/3 registers. the second address defined at cr[4ah] bit2-0 can only be used to read/write temperature sensor 2 registers, and the third address defined at data register port 6h port 5h index register isa data bus isa address bus configuration register 40h nsmi status/mask registers 41h, 42h, 44h, 45h vid<3:0>/fan divisor register 47h serial bus address 48h monitor value registers 20h~3fh and 60h~7fh (auto-increment) vid<4>/device id 49h temperature 2, 3 serial bus address 4ah control register 4bh~4dh select bank for 50h~5fh reg. 4eh winbond vendor id 4fh bank 0 r-t table value beep control register winbond test register 50h~58h bank 1 temperature 2 control/staus registers 50h~56h bank 2 temperature 3 control/staus registers 50h~56h bank 4 additional control/staus registers 50h~5ch bank 5 additional limit value & value ram 50h~57h 11 cr[4ah] bit6-4 can only be used to access (read/write) temperature sensor 3 registers. the first serial bus address, cr[48h], uses 3 hardware setting bits. when pin 43 is set high, pins 47-45 are used to set the i 2 c address for register cr[48h]. the selected address is 00101[pin45][pin46][pin47]. if pin45=1, pin46=1, pin47=0, the content of cr[48h] is 00101110. cr[4ah] is used to set the other two i 2 c addresses. if cr[4ah] bit 2-0 is xxx , the temperature sensor 2 serial address is 1001 xxxg, in which g is the r ead/write bit. if cr[4ah] bit 6-4 is yyy , the temperature sensor 3 serial address is 1001 yyyg, in which g is the read/write bit. the first serial bus access timing are shown as follows: (a) serial bus write to internal address register followed by the data byte figure 2 ? serial bus write to internal address register followed by the data byte 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by r/nw ack by MON35W42 scl sda d7 d6 d5 d4 d3 d2 d1 d0 ack by stop by master scl sda (continued) 780 78 0 78 frame 2 internal index register byte (continued) frame 3 data byte frame 1 serial bus address byte MON35W42 MON35W42 12 (b) serial bus write to internal address register only figure 3 ? serial bus write to internal address register only (c) serial bus read from a register with the internal address register preset to desired location figure 4 ? serial bus write to internal address register the serial bus timing of the temperature 2 and 3 is shown as follow: (a) typical 2-byte read from preset pointer location (temp, t os , t hyst ) figure 5 ? typical 2-byte read from present pointer location 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by r/nw ack by MON35W42 scl sda 780 78 0 frame 2 internal index register byte frame 1 serial bus address byte stop by master MON35W42 0 start by master 0101101 d7d6d5d4d3d2d1d0 ack by master r/nw ack by MON35W42 scl sda 780 78 0 frame 2 internal index register byte frame 1 serial bus address byte stop by master 0 start by master 0101101 d7 d1d0 ack by master r/nw ack by MON35W42 scl sda 780 78 frame 2 msb data byte frame 1 serial bus address byte d7 d1 d0 07 stop by master ... ... ... ack by master ... frame 3 lsb data byte 13 (b) typical pointer set followed by immediate read for 2-byte register (temp, t os , t hyst ) figure 6 ? typical pointer set followed by immediate read for 2-byte register (c) typical read 1-byte from configuration register with preset pointer figure 7 ? typical 1-byte read from configuration with reset 0 start by master d7 d1 d0 ack by master ack by MON35W42 scl sda 780 78 0 frame 4 msb data byte frame 3 serial bus address byte d7 d1 d0 07 stop by master ... ... ... no ack by master ... frame 5 lsb data byte 0 start by master 1001a2a1a0 r/nw ack by scl sda 780 frame 1 serial bus address byte 4 d1 d0 ack by frame 2 pointer byte 1001a2a1a0 r/nw 000000 MON35W42 MON35W42 0 start by master d7 d2 ack by MON35W42 scl sda 780 frame 2 data byte frame 1 serial bus address byte d0 7 stop by master no ack by master 1001 a2 a1 a0 r/nw d1 d5 d4 d3 d6 8 14 (d) typical pointer set followed by immediate read from configuration register figure 8 ? typical pointer set followed by immediate read from temp 2/3 configuration register (e) temperature 2/3 configuration register write figure 9 ? configuration register write 0 repea start by master d7 d5 d4 ack by scl (cont..) sda (cont..) 780 frame 4 msb data byte frame 3 serial bus address byte d2 d1 d0 7 stop by master no ack by master 0 start by master 1001a2a1a0 r/nw ack by MON35W42 scl sda 780 frame 1 serial bus address byte 4 d1 d0 ack by frame 2 pointer byte 1001 a2 a1 a0 r/nw ... ... d6 d3 8 78 00000 0 MON35W42 MON35W42 0 start by master 1 0 0 1 a2 a1 a0 r/nw ack by MON35W42 scl sda 780 frame 1 serial bus address byte 4 d1 d0 ack by frame 2 pointer byte 0 ack by scl (cont...) sda (cont...) 78 frame 3 configuration data byte 0 0 d4 d3 d2 d1 0d0 stop by master 0000000 78 MON35W42 MON35W42 15 (f) temperature 2/3 t os and t hyst write figure 10 ? configuration register write 0 ack by scl (cont...) sda (cont...) 78 frame 3 msb data byte 0 start by master 1001a2a1a0 r/nw ack by MON35W42 scl sda 780 frame 1 serial bus address byte 4 d1 d0 ack by frame 2 pointer byte d6 d5 d4 d3 d2 d1 d7 d0 0 78 d6 d5 d4 d3 d2 d1 d7 d0 ack by stop by master frame 4 lsb data byte 78 0 0 0000 MON35W42 MON35W42 MON35W42 16 analog inputs the maximum input voltage of the analog pin is 4.096v, the 8-bit adc has a 16mv lsb. for most pc applications, the analog inputs are connected to the power suppliers. the cpu v- core voltage,+3.3v and battery voltage can directly connected to these analog inputs. the 5vsb and +12v inputs should be reduced using external resistors to obtain the proper input range. refer to figure 11. figure 11 pin 36 +2.5vina +2.5vinb pin 35 +3.3vin 12vin pin 34 pin 32 pin 33 vdd(+5v) n12vin vbat pin 31 pin 30 r6 r1 v1 n5vin positive input negative input 8-bit adc with 16mv lsb typical thermister connection 10k, 1% r thm vref pin 37 vtin3 vtin2 vtin1 pin 38 pin 39 pin 40 5vsb pin 29 pin 28 positive inputs r5 r7 r8 10k, 25 c **the connections of vtin1 and vtin2 are same as vtin3 r2 r3 r4 r v2 v3 v4 17 monitor over 4.096v voltage: the input voltage +12vin can be expressed using the following equation. 12 1 2 12 vi nv r rr '( ) the value of r1 and r2 can be selected as 28k ohms and 10k ohms, respectively, when the input voltage v1 is 12v. the node voltage of +12vin will be subject to less than 4.096v for the maximum input range of the 8-bit adc. similarly, the node voltage of 5vsb (measured standby power vsb for atx power supply) also can be monitored by using two series resistors r3 and r4 which can be 5.1k ohms and 7.5k ohms so as to obtain the 5vsb as limited to less than 4.096v. pin 33 is connected to the power supply vcc at +5v. this pin supports two functions. the first function is to supply internal analog power in the MON35W42 and the second function is to monitor the 5v input through internal series resistors. the values of the two series resistors are 34k ohms and 50k ohms so that input voltage to adc is 2.98v which is less than 4.096v of the adc maximum input voltage. the voltage equation can be represent as follows. vvcc k kk v i n '( ) * 50 50 34 298 + ++ . where vcc is set to 5v. monitor negative voltage: the negative voltage should be connected to series resistors and a positive voltage vref (equal to 3.6v). in figure 11, the voltage v3 and v4 are two negative voltages, -12v and -5v respectively. the voltage v3 is connected to two series resistors and is then connected to vref which is a positive voltage. the voltage at node n12vin must be a positive voltage and will if the values of the two series resistors are carefully selected. if the value of two series resistors are r5=232k ohms and r6=56k ohm. the input voltage of node n12vin can be calculated by the following equation. nvi n vref v k kk v 12 232 232 56 55 ')( ) ) ()( ) + ++ where vref is equal 3.6v. if v 5 is equal to -12v then the voltage is equal to 0.567v and the converted hexdecimal data is set to 35h by the 8-bit adc with 16mv-lsb. this monitored value should be converted to the real negative voltage and the voltage is calculated by the following equation. v nvi n vref 5 12 1 ' ,( , - - where - is 232k/(232k+56k). if the n2vin is 0.567 then the v5 is approximately equal to -12v. 18 the other negative voltage input v6 (approximate -5v) also can be evaluated by a similar method and the series resistors can be selected as r7=120k ohms and r8=56k ohms. the equation for a v6 of - 5v voltage is as follows. v nvi n vref 6 5 1 ' ,( , . . where . is 120k/(120k+56k). if the monitored adc value in the n5vin channel is 0.8635, vref=3.6v and the parameter . is 0.6818 then the negative voltage of v6 can be -5v. monitor temperature from thermistor: the MON35W42 can connect to three thermistors to measure three different environment temperatures. the specification of thermistor is: (1) - value is 3435k, (2) resistor value is 10k ohms at 25 % c. in figure 11, the themistor is connected by a series resistor to a 10k ohms resistor, then to vref (pin 37). monitor temperature from pentium ? ii thermal diode or bipolar transistor 2n3904 the MON35W42 can monitor the temperature from the pentium ? ii (deschutes) thermal diode interface or a 2n3904 transistor. the circuit is shown in figure 12. the pentium ? ii d- pin is connected to power supply ground (gnd) and the d+ pin is connected to pin piitdx in the MON35W42. the resistor r=30k ohms is connected to vref to supply the diode bias current and the bypass capacitor c=3300pf is used to filter the high frequency noise. the transistor 2n3904 is to a form a diode, the base (b) and collector (c) in the 2n3904 are tied together to act as a thermal diode. 19 figure 12 fan speed count and fan speed control fan speed count fan speed count inputs provide for signals from fans equipped with tachometer outputs. these signals must be ttl level, and the maximum input voltage can not be over vcc. if the input signals from the tachometer outputs are above vcc, the external voltage must be reduced using external components to obtain the proper input voltage. the normal circuit and trimming circuits are shown in figure 13. determine the fan counter according to: count rpm divisor ' ( ( 135 10 6 . in other words, once the fan speed counter has been read from register cr28 or cr29 or cr2a, the fan speed can be evaluated by the following equation. rpm c ount d i vi so r ' ( ( 135 10 6 . the default divisor is 2 and defined in cr47.bit7~4, cr4b.bit7~6, and bank0 cr5d.bit5~7 which contain the three bits for the divisor. this provides very low speed fan counter support for fans such as power supply fan. the followed table is an example for the relation of divisor, rpm, and count. 2n3904 c e b r=30k, 1% c=3300pf bipolar transistor temperature sensor pentium ii cpu d+ d- therminal diode c=3300pf r=30k, 1% vref piitdx piitdx or mon35w82 20 table 1 divisor nominal rpm time per revolution counts 70% rpm time for 70% 1 8800 6.82 ms 153 6160 9.74 ms 2 (default) 4400 13.64 ms 153 3080 19.48 ms 4 2200 27.27 ms 153 1540 38.96 ms 8 1100 54.54 ms 153 770 77.92 ms 16 550 109.08 ms 153 385 155.84 ms 32 275 218.16 ms 153 192 311.68 ms 64 137 436.32 ms 153 96 623.36 ms 128 68 872.64 ms 153 48 1246.72 ms fan connector fan out +12v gnd pull-up resister 4.7k ohms +5v +12v fan input pin 18/19/20 mon35w82 fan connector fan out +12v gnd pull-up resister 4.7k ohms +12v fan input pin 18/19/20 14k~39k 10k figure 13b - fan with tach pull-up to +12v, or totem-pole output and register attenuator figure 13a - fan with tach pull-up to +5v fan connector fan out +12v gnd pull-up resister > 1k +12v fan input pin 18/19/20 fan connector fan out +12v gnd pull-up resister < 1k or totem-pole output +12v fan input pin 18/19/20 > 1k figure 13d - fan with tach pull-up to +12v, or totem-pole putput and zener clamp figure 13c - fan with tach pull-up to +12v and zener clamp 3.9v zener 3.9v zener diode diode diode diode mon35w82 mon35w82 mon35w82 21 fan speed control the MON35W42 provides four sets of controls for fan pwm speed control. the duty cycle of the pwm can be programmed by a 8-bit registers which are defined in the bank0 cr5a, cr5b, cr5e, and cr5f. the default duty cycle is set to 100%, the default 8-bit registers is set to ffh. the duty cycle can be calculated as follows. % 100 255 value register bit - 8 programmed (%) cycle duty ( ' the pwm clock frequency also can be program and defined in the bank0.cr5c and bank4.cr5c. the application circuit is shown in figure 14. figure 14 temperature measurement machine the temperature data format is 8-bit two?s-complement for sensor 1 and 9-bit two?s-complement for sensors 2/3. the 8-bit temperature data can be obtained by reading the cr[27h]. the 9-bit temperature data can be obtained by reading the 8 msbs from the bank1/2 cr[50h] and the lsb from the bank1/2 cr[51h] bit 7. the format of the temperature data is show in table 1. table 2 8-bit digital output 9-bit digital output temperature 8-bit binary 8-bit hex 9-bit binary 9-bit hex +125 c 0111,1101 7dh 0,1111,1010 0fah +25 c 0001,1001 19h 0,0011,0010 032h +1 c 0000,0001 01h 0,0000,0010 002h +0.5 c - - 0,0000,0001 001h +0 c 0000,0000 00h 0,0000,0000 000h -0.5 c - - 1,1111,1111 1ffh -1 c 1111,1111 ffh 1,1111,1110 1ffh -25 c 1110,0111 e7h 1,1100,1110 1ceh -55 c 1100,1001 c9h 1,1001,0010 192h +12v fan r1 r2 nmos pnp transistor c + - pwm clock input d s g 22 temperature sensor 1 nsmi interrupt modes: (1) comparator interrupt mode setting the t hyst (temperature hysteresis) limit to 127 c will set temperature sensor 1 nsmi to the comparator interrupt mode. temperatures which exceed t o (over temperature) limit cause an interrupt. this interrupt is reset by reading the interrupt status register. once an interrupt event has occurred by exceeding t o , and then reset, if the temperature remains above the t o , the interrupt will occur again when the next conversion has completed. if an interrupt event has occurred by exceeding t o and is not reset, the interrupts will not occur again. the interrupts will continue to occur in this manner until the temperature goes below t o . (figure 16-1) (2) two-times interrupt mode setting the t hyst lower than t o will set temperature sensor 1 nsmi to the two-times interrupt mode. the temperature exceeding t o causes an interrupt and then the temperature going below t hyst also causes an interrupt if the previous interrupt has been reset by reading the interrupt status register. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst , additional interrupts will not occur. (figure 15-2) t oi * * figure 15-1 - comparator interrupt mode *interrupt reset when interrupt status registers are read t oi t hyst figure 15-2 - two-times interrupt mode nsmi nsmi * * * * * t hyst 127'c 23 temperature sensor 2 and sensor 3 nsmi interrupt temperature sensor 2 and sensor 3 nsmi interrupt have two modes of operation and are programmed at cr[4ch] bit 6. (1) comparator interrupt mode temperatures exceeding t o cause an interrupt. this interrupt is reset by reading the interrupt status register. once an interrupt event has occurred by exceeding t o , and then reset, if the temperature remains above the t hyst , the interrupt occurs again when the next conversion has completed. if an interrupt event has occurred by exceeding t o and is not reset, the interrupt will not occur again. the interrupt continues to occur in this manner until the temperature goes below t hyst . (figure 16-1) (2) two-times interrupt mode temperatures exceeding t o cause an interrupt and then when the temperature going below t hyst it will also cause an interrupt if the previous interrupt has been reset by reading the interrupt status register. once an interrupt event has occurred by exceeding t o , and then reset, if the temperature remains above the t hyst , the interrupt will not re-occur. (figure 16-2) t oi t hyst * * * *interrupt reset when interrupt status registers are read t oi t hyst nsmi nsmi * * * * * figure 16-1 - comparator interrupt mode figure 16-2 - two-times interrupt mode 24 temperature sensors 2 and 3 over-temperature (novt) temperature sensors 2 and 3 over-temparature (novt) have two modes of operation. they are programmed at bank1 and bank2 cr[52h] bit1 . these two bits needs to be programmed to the same value. (1) comparator mode : temperatures exceeding t o cause the novt output to go active until the temperature is less than t hyst . (figure 17) (2) interrupt mode: temperatures exceeding t o causes the novt output to go active indefinitely until reset by reading temperature sensor 2 or sensor 3 registers. if the temperature exceeds t o , and then novt is reset, and then the temperature going below t hyst causes the novt to go active until reset by reading temperature sensor2 or sensor 3 registers. once the novt is activated by exceeding t o , then reset, if the temperature remains above t hyst , the novt is not be activated again. (figure 17). figure 17 ? over temperature response diagram *interru p t reset when interru p t status re g isters are read t oi t hyst nsmi ** 25 registers and ram address register (port x5h) data port: port x5h power on default value 00h attribute: bit 6:0 read/write , bit 7: read only size: 8 bits 7 6 5 4 3 2 1 0 data bit7: read only the logical 1 indicates the device is busy due to a serial bus transaction or another isa bus transaction. by checking this bit, multiple isa drivers can use the MON35W42 without interfering with each other or a serial bus driver. it is the user's responsibility not to have a serial bus and isa bus operations at the same time. this bit is: set: with a write to port x5h or when a serial bus transaction is in progress. reset: with a write or read from port x6h if it is set by a write to port x5h, or when the serial bus transaction is finished. bit 6-0: read/write bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 busy address pointer (power on default 00h) (power on default 0) a6 a5 a4 a3 a2 a1 a0 26 address pointer index (a6-a0) registers and ram a6-a0 in hex power on value of registers: 27 configuration register ! ! ! ! index 40h register location: 40h power on default value 00000001 binary attribute: read/write size: 8 bits bit 7: a one restores power-on default values to all registers except the serial bus address register. this bit clears itself since the power on default is zero. bit 6: a logical 1 in this bit drives a zero on beep/ngpo pin. bit 5: reserved bit 4: reserved bit 3: a one disables the nsmi output without affecting the contents of interrupt status registers. the device will stop monitoring. it will resume monitoring upon the clearing of this bit. bit 2: reserved bit 1: a one enables the nsmi interrupt output. bit 0: a one enables startup of monitoring operations, a zero puts the part in standby mode. note: the outputs of interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "int_clear'' bit. 7 6 5 4 3 2 1 0 start nsmienable reserved int_clear reserved reserved beep/ngpo initialization 28 interrupt status register 1 ! ! ! ! index 41h register location: 41h power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 vcorea vinro +3.3vin +5vin temp1 temp2 fan1 fan2 bit 7: a one indicates the fan count limit of fan2 has been exceeded. bit 6: a one indicates the fan count limit of fan1 has been exceeded. bit 5: a one indicates a high limit of vtin2 has been exceeded from temperature sensor 2. bit 4: a one indicates a high limit of vtin1 has been exceeded from temperature sensor 1. bit 3: a one indicates a high or low limit of +5vin has been exceeded. bit 2: a one indicates a high or low limit of +3.3vin has been exceeded. bit 1: a one indicates a high or low limit of vinr0 has been exceeded. bit 0: a one indicates a high or low limit of vcorea has been exceeded. interrupt status register 2 ! ! ! ! index 42h register location: 42h power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 +12vin -12vin -5vin fan3 chassis intrusion temp3 reserved reserved bit 7-6:reserved.this bit should be set to 0. bit 5: a one indicates a high limit of vtin3 has been exceeded from temperature sensor 3. bit 4: a one indicates chassis intrusion has gone high. bit 3: a one indicates the fan count limit of fan3 has been exceeded. bit 2: a one indicates a high or low limit of -5vin has been exceeded. bit 1: a one indicates a high or low limit of -12vin has been exceeded. bit 0: a one indicates a high or low limit of +12vin has been exceeded. 29 nsmi mask register 1 ! ! ! ! index 43h register location: 43h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 vcorea vinro +3.3vin +5vin temp1 temp2 fan1 fan2 bit 7-0: a one disables the corresponding interrupt status bit for nsmi interrupt. nsmi mask register 2 ! ! ! ! index 44h register location: 44h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 +12vin -12vin -5vin fan3 chassis intrusion temp3 reserved reserved bit 7-6: reserved. this bit should be set to 0. bit 5-0: a one disables the corresponding interrupt status bit for nsmi interrupt. 30 reserved register ! ! ! ! index 45h chassis clear register -- index 46h register location: 46h power on default value <7:0> = 00000000 binary attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved reserved reserved chassis clear bit 7: set to 1, clear chassis intrusion event. this bit self clears after clearing chassis intrusion event. bit 6-0:reserved. this bit should be set to 0. vid/fan divisor register ! ! ! ! index 47h register location: 47h power on default value <7:4> is 0101, <3:0> is mapped to vid<3:0> attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 vid0 vid1 vid2 vid3 fan1div_b0 fan1div_b1 fan2div_b0 fan2div_b1 bit 7-6: fan2 speed control. bit 5-4: fan1 speed control. bit 3-0: the vid <3:0> inputs note: please refer to bank0 cr[5dh] , fan divisor table. 31 serial bus address register ! ! ! ! index 48h register location: 48h power on default value serial bus address <6:0> = 0101101 and <7> = 0 binary size: 8 bits 7 6 5 4 3 2 1 0 serial bus address reserved bit 7: read only - reserved. bit 6-0: read/write - serial bus address <6:0> value ram ! ! ! ! index 20h- 3fh or 60h - 7fh (auto-increment) address a6-a0 address a6-a0 with auto-increment description 20h 60h vcorea reading 21h 61h vinr0 reading 22h 62h +3.3vin reading 23h 63h +5vin reading 24h 64h +12vin reading 25h 65h -12vin reading 26h 66h -5vin reading 27h 67h temperature reading 28h 68h fan1 reading note: this location stores the number of counts of the internal clock per revolution. 29h 69h fan2 reading note: this location stores the number of counts of the internal clock per revolution. 2ah 6ah fan3 reading note: this location stores the number of counts of the internal clock per revolution. 2bh 6bh vcorea high limit, default value is defined by vcore voltage +0.2v. 2ch 6ch vcorea low limit, default value is defined by vcore voltage -0.2v. 2dh 6dh vinr0 high limit. 2eh 6eh vinr0 low limit. 2fh 6fh +3.3vin high limit 30h 70h +3.3vin low limit 31h 71h +5vin high limit 32h 72h +5vin low limit 32 address a6-a0 address a6-a0 with auto-increment description 33h 73h +12vin high limit 34h 74h +12vin low limit 35h 75h -12vin high limit 36h 76h -12vin low limit 37h 77h -5vin high limit 38h 78h -5vin low limit 39h 79h temperature sensor 1 (vtin1) high limit 3ah 7ah temperature sensor 1 (vtin1) hysteresis limit 3bh 7bh fan1 fan count limit note: it is the number of counts of the internal clock for the low limit of the fan speed. 3ch 7ch fan2 fan count limit note: it is the number of counts of the internal clock for the low limit of the fan speed. 3dh 7dh fan3 fan count limit note: it is the number of counts of the internal clock for the low limit of the fan speed. 3e- 3fh 7e- 7fh reserved setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits. voltage id (vid4) & device id -- index 49h register location: 49h power on default value <7:1> is 000,0001b <0> is mapped to vid <4> size: 8 bits 7 6 5 4 3 2 1 0 did<6:0> vid4 bit 7-1: read only - device id<6:0> bit 0 : read/write - the vid4 inputs. 33 temperature 2 and temperature 3 serial bus address register--index 4ah register location: 4ah power on default value <7:0> = 0000,0001 binary. reset by mr attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 i2caddr2 i2caddr2 i2caddr2 dis_t2 i2caddr3 i2caddr3 i2caddr3 dis_t3 bit 7: set to 1, disable temperature sensor 3 and can not access any data from temperature sensor 3. bit 6-4: temperature 3 serial bus address. the serial bus address is 1001 xxx. where xxx are defi ned in these bits. bit 3: set to 1, disable temperature sensor 2 and can not access any data from temperature sensor 2. bit 2-0: temperature 2 serial bus address. the serial bus address is 1001 xxx. where xxx are defi ned in these bits. pin control register -- index4bh register location: 4bh power on default value <7:0> 44h. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved clkinsel clkinsel adcovsel adcovsel fan3div_b0 fan3div_b1 bit 7-6:fan3 speed divisor. please refer to bank0 cr[5dh] , fan divisor table. bit 5-4: select a/d converter clock input. <5:4> = 00 - default. adc clock select 22.5 khz. <5:4> = 01- adc clock select 5.6 khz. (22.5k/4) <5:4> = 10 - adc clock select 1.4khz. (22.5k/16) <5:4> = 11 - adc clock select 0.35 khz. (22.5k/64) bit 3-2: clock input select. 34 <3:2> = 00 - pin 3 (clkin) select 14.318mhz clock. <3:2> = 01 - default. pin 3 (clkin) select 24mhz clock. <3:2> = 10 - pin 3 (clkin) select 48mhz clock . <3:2> = 11 - reserved. pin 3 no clock input. bit 1-0: reserved. user defined. nirq/novt property select -- index 4ch register location: 4ch power on default value <7:0> --0000,0001. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved ovtpol dis_ovt1 dis_ovt2 reserved t23_intmode reserved bit 7: reserved. user defined. bit6: set to 1, the nsmi output type of temperature 2 and 3 is set to comparator interrupt mode. set to 0, the nsmi output type is set to two-times interrupt mode. (default 0) bit5: reserved. user defined. bit 4: disable temperature sensor 3 over-temperature (ovt) output if set to 1. default 0, enable ovt2 output through pin novt. bit 3: disable temperature sensor 2 over-temperature (ovt) output if set to 1. default 0, enable ovt1 output through pin novt. bit 2: over-temperature polarity. if this bit is 1, novt active high. if this bit is 0, novt active low. default 0. bit 1: reserved. user defined. bit 0: reserved. user defined. 35 fan in/out and beep/ngpo control register -- index 4dh register location: 4dh power on default value <7:0> 0001,0101. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 faninc1 fanopv1 faninc2 fanopv2 faninc3 fanopv3 gposel dis_abn bit 7: disable power-on abnormal voltage monitoring including v-core a and +3.3v. if these voltages exceed the limit value, the beep pin (open drain) will drive a 300hz or 600hz frequency signal. if this bit is 1, the frequency will be disable. default 0. after power on, the system should set 1 to this bit to 1 in order to disable beep. bit 6: beep/ngpo pin function select. if this bit is 1 select ngpo function. set 0, select beep function. this bit defaults to 0. bit 5: fan 3 output value if faninc3 is set to 0. if this bit is 1, then pin 18 always generate logic high signal. if this bit is 0, pin 18 always generates logic low signal. this bit default 0. bit 4: fan 3 input control. set to 1, pin 18 acts as fan clock input, which is default value. set to 0, this pin 18 acts as fan control signal and the output value of fan control is set by this register bit 5. this output pin can connect to power pmos gate to control fan on/off. bit 3: fan 2 output value if faninc2 sets to 0. if this bit is 1, then pin 19 always generate logic high signal. if this bit is 0, pin 19 always generates logic low signal. this bit default 0. bit 2: fan 2 input control. set to 1, pin 19 acts as fan clock input, which is default value. set to 0, this pin 19 acts as fan control signal and the output value of fan control is set by this register bit 3. this output pin can connect to power nmos gate to control fan on/off. bit 1: fan 1 output value if faninc1 sets to 0. if this bit is 1, then pin 20 always generate logic high signal. if this bit is 0, pin 20 always generates logic low signal. this bit default 0. bit 0: fan 1 input control. set to 1, pin 20 acts as fan clock input, which is default value. set to 0, this pin 20 acts as fan control signal and the output value of fan control is set by this register t 1. this output pin can connect to power pmos gate to control fan on/off. 36 register 50h ~ 5fh bank select -- index 4eh register location: 4eh power on default value <6:3> = reserved, <7> = 1, <2:0> = 0. reset by mr attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 banksel0 banksel1 banksel2 reserved reserved reserved reserved hbacs bit 7: hbacs- high byte access. set to 1, access register 4fh high byte register. set to 0, access register 4fh low byte register. default 1. bit 6-3: reserved. this bit should be set to 0. bit 2-0: index ports 0x50~0x5f bank select. smsc vendor id -- index 4fh register location: 4fh power on default value <15:0> = 5ca3h attribute: read only size: 16 bits 15 8 7 0 vidh vidl bit 15-8: vendor id high byte if cr4e.bit7=1.default 5ch. bit 7-0: vendor id low byte if cr4e.bit7=0. default a3h. 37 smsc test register -- index 50h - 55h (bank 0) beep control register 1-- index 56h ( bank 0 ) register location: 56h power on default value <7:0> 0000,0000. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 en_vca_bp en_vr0_bp en_v33_bp en_v5_bp en_t1_bp en_t2_bp en_fan1_bp en_fan2_bp bit 7: enable beep output from fan 2 if the monitor value exceed the limit value. if this bit is 1 (default), enable beep output. bit 6: enable beep output from fan 1 if the monitor value exceed the limit value. if this bit is 1 (default),, enable beep output. bit 5: enable beep output from temperature sensor 2 if the monitor value exceed the limit value. if this bit is 1, enable beep output. default 0 bit 4: enable beep output for temperature sensor 1 if the monitor value exceed the limit value. if this bit is 1, enable beep output. default 0 bit 3: enable beep output from vdd (+5v), if this bit is 1, enable beep output if the monitor value exceed the limits value. default 0, disable beep output. bit 2: enable beep output from +3.3v. if this bit is 1, enable beep output. default 1. bit 1: enable beep output from vinr0. if this bit is 1, enable beep output. default 1. bit 0: enable beep output from vcorea if the monitor value exceeds the limits value. if this bit is 1, enable beep output. default 1. 38 beep control register 2-- index 57h ( bank 0 ) register location: 57h power on default value <7:0> 1000-0000. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 en_v12_bp en_nv12_bp en_nv5_bp en_fan3_bp en_caso_bp en_t3_bp reserved en_gbp bit 7: enable global beep. if this bit is 1, enable global beep output. default 1. if this bit is 0, disable all beep outputs. bit 6: reserved. this bit should be set to 0. bit 5: enable beep output from temperature sensor 3 if the monitor value exceed the limit value. if this bit is 1, enable beep output. default 0 bit 4: enable beep output for case open if the monitor value exceed the limit value. if this bit is 1, enable beep output. default 0. bit 3: enable beep output from fan 3 if the monitor value exceed the limit value. if this bit is 1, enable beep output. default 0. bit 2: enable beep output from -5v, if this bit is 1, enable beep output if the monitor value exceed the limits value. default 0, disable beep output. bit 1: enable beep output from -12v, if this bit is 1, enable beep output if the monitor value exceed the limits value. default 0, disable beep output. bit 0: enable beep output from +12v, if this bit is 1, enable beep output if the monitor value exceed the limits value. default 0, disable beep output. chip id -- index 58h ( bank 0 ) register location: 58h power on default value <7:0> 0011-0000. reset by mr. attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 chipid bit 7: smsc chip id number. read this register will return 30h. 39 diode selection register -- index 59h (bank 0) register location: 59h power on default value <7>=0 and <6:4> = 111 and <3:0> = 0000 attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved reserved reserved selpiiv1 selpiiv2 selpiiv3 reserved bit 7: reserved bit 6: temperature sensor diode 3. set to 1, select pentium ii compatible diode. set to 0 to select 2n3904 bipolar mode. bit 5: temperature sensor diode 2. set to 1, select pentium ii compatible diode. set to 0 to select 2n3904 bipolar mode. bit 4: temperature sensor diode 1. set to 1, select pentium ii compatible diode. set to 0 to select 2n3904 bipolar mode. bit 3-0: reserved pwmout2 control -- index 5ah (bank 0) register location: 5ah power on default value: <7:0> 1111-1111. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 pwm2_duty bit 7: pwmout2 duty cycle control if this is ff, duty cycle is 100%, if this is 00, duty cycle is 0%. 40 pwmout1 control -- index 5bh ( bank 0 ) register location: 5bh power on default value: <7:0> 1111-1111. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 pwm1_duty bit 7: pwmout1 duty cycle control if this is ff, duty cycle is 100%, if this is 00, duty cycle is 0%. 41 pwmout1/2 clock select -- index 5ch ( bank 0 ) register location: 5ch power on default value <7:0> 0001-0001. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 pwm2clksel pwm2clksel pwm2clksel en_fanpwm2 pwm1clksel pwm1clksel pwm1clksel reserved bit 7: reserved bit 6-4: pwmout1 clock selection. the clock frequency definition is the same as pwmout2 clock selection. bit 3: set to 1. enable pwmout2 pwm control bit 2-0: pwmout2 clock selection. <2:0> = 000: 46.87khz <2:0> = 001: 23.43khz (default) <2:0> = 010: 11.72khz <2:0> = 011: 5.85khz <2:0> = 100: 2.93khz vbat monitor control register -- index 5dh ( bank 0 ) register location: 5dh power on default value <7:0> 0000-0000. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 en_vbat_mn t diodes1 diodes2 di odes3 reserved fandiv1_b2 fandiv2_b2 fandiv3_b2 bit 7: fan3 divisor bit 2. bit 6: fan2 divisor bit 2. bit 5: fan1 divisor bit 2. bit 4: reserved. bit 3: temperature sensor 3 select into thermal diode such as pentium ii cpu supported. set to 1, select bipolar sensor. set to 0, select thermistor sensor. bit 2: sensor 2 type selection. defined as diodes3 described in the bit 3. 42 bit 1: sensor 1 type selection. defined as diodes2 described in the bit 3.bit 0: set to 1, enable battery voltage monitor. set to 0, disable battery voltage monitor. if enabled, the monitor value is after one monitor cycle. note that the monitor cycle time is at least 300ms for MON35W42. fan divisor table bit 2 bit 1 bit 0 fan divisor bit 2 bit 1 bit 0 fan divisor 0 0 0 1 1 0 0 16 0 0 1 2 1 0 1 32 0 1 0 4 1 1 0 64 0 1 1 8 1 1 1 128 pwmout3 control -- index 5eh ( bank 0 ) register location: 5eh power on default value <7:0> 1111-1111. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 pwm3_duty bit 7: pwmout3 duty cycle control if this is ff, duty cycle is 100%, if this is 00, duty cycle is 0%. pwmout4 control -- index 5fh ( bank 0 ) register location: 5fh power on default value <7:0> 1111-1111. reset by mr. attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 pwm4_duty bit 7: pwmout4 duty cycle control if this is ff, duty cycle is 100%, if this is 00, duty cycle is 0%. 43 temperature sensor 2 temperature (high byte) register - index 50h ( bank 1 ) register location: 50h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 temp2<8:1> bit 7: temperature <8:1> of sensor 2, which is high byte. temperature sensor 2 temperature (low byte) register - index 51h ( bank 1 ) register location: 51h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 temp2<0> reserved bit 7: temperature <0> of sensor2, which is low byte. bit 6-0: reserved. this bit should be set to 0. 44 temperature sensor 2 configuration register - index 52h ( bank 1 ) register location: 52h power on default value <7:0> = 0x00 size: 8 bits 7 6 5 4 3 2 1 0 stop2 intmod reserved fault fault reserved reserved reserved bit 7-5: read - reserved. this bit should be set to 0. bit 4-3: read/write - number of faults to detect before setting novt output to avoid false tripping due to noise. bit 2: read - reserved. this bit should be set to 0. bit 1: read/write - novt interrupt mode select. this bit default is set to 0, which is compared mode. when set to 1, interrupt mode will be selected. bit 0: read/write - when set to 1 the sensor will stop monitoring. temperature sensor 2 hysteresis (high byte) register - index 53h ( bank 1 ) register location: 53h power on default value <7:0> = 0x4b attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 thyst2<8:1> bit 7-0: temperature hysteresis bit 8-1, which is high byte. the temperature default 75 degree c. 45 temperature sensor 2 hysteresis (low byte) register - index 54h ( bank 1 ) register location: 54h power on default value <7:0> = 0x0 attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 thyst2<0> reserved bit 7: temperature hysteresis bit 0, which is low byte. bit 6-0: reserved. this bit should be set to 0. temperature sensor 2 over-temperature (high byte) register - index 55h ( bank 1 ) register location: 55h power on default value <7:0> = 0x50 attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 tovf2<8:1> bit 7-0: over-temperature bit 8-1, which is high byte. the temperature default 80 degree c. 46 temperature sensor 2 over-temperature (low byte) register - index 56h( bank 1 ) register location: 56h power on default value <7:0> = 0x0 size: 8 bits 7 6 5 4 3 2 1 0 tovf2<0> reserved bit 7: read/write - over-temperature bit 0, which is low byte. bit 6-0: read only - reserved. this bit should be set to 0. temperature sensor 3 temperature (high byte) register - index 50h ( bank 2 ) register location: 50h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 temp2<8:1> bit 7-0: temperature <8:1> of sensor 2, which is high byte. temperature sensor 3 temperature (low byte) register - index 51h ( bank 2 ) register location: 51h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 temp2<0> reserved bit 7: temperature <0> of sensor2, which is low byte. bit 6-0: reserved. this bit should be set to 0. 47 temperature sensor 3 configuration register - index 52h ( bank 2 ) register location: 52h power on default value <7:0> = 0x00 size: 8 bits 7 6 5 4 3 2 1 0 stop3 intmod reserved fault fault reserved reserved reserved bit 7-5: read - reserved. this bit should be set to 0. bit 4-3: read/write - number of faults to detect before setting novt output to avoid false tripping due to noise. bit 2: read - reserved. this bit should be set to 0. bit 1: read/write - novt interrupt mode select. this bit default is set to 0, which is compared mode. when set to 1, interrupt mode will be selected. bit 0: read/write - when set to 1 the sensor will stop monitoring. temperature sensor 3 hysteresis (high byte) register - index 53h ( bank 2 ) register location: 53h power on default value <7:0> = 0x4b attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 thyst3<8:1> bit 7-0: temperature hysteresis bit 8-1, bit 8 is the msb. the temperature default 75 degree c. 48 temperature sensor 3 hysteresis (low byte) register - index 54h ( bank 2 ) register location: 54h power on default value <7:0> = 0x0 attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 thyst3<0> reserved bit 7: temperature hysteresis bit 0, this is the lsb. bit 6-0: reserved. this bit should be set to 0. temperature sensor 3 over-temperature (high byte) register - index 55h ( bank 2 ) register location: 55h power on default value <7:0> = 0x50 attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 tovf3<8:1> bit 7-0: over-temperature bit 8-1, bit 8 is the msb. the temperature default 80 degree c. 49 temperature sensor 3 over-temperature (low byte) register - index 56h( bank 2 ) register location: 56h power on default value <7:0> = 0x0 size: 8 bits 7 6 5 4 3 2 1 0 tovf3<0> reserved bit 7: read/write - over-temperature bit 0, this is the lsb. bit 6-0: read only - reserved. this bit should be set to 0. interrupt status register 3 -- index 50h (bank4) register location: 50h power on default value <7:0> = 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 5vsb vbat reserved reserved reserved reserved reserved reserved bit 7-2: reserved. bit 1: a one indicates a high or low limit of vbat has been exceeded. bit 0: a one indicates a high or low limit of 5vsb has been exceeded. 50 nsmi mask register 3 -- index 51h (bank 4) register location: 51h power on default value <7:0> = 0000,0000h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 5vsb vbat reserved reserved reserved reserved reserved reserved bit 7-2: reserved. bit 1: a one disables the corresponding interrupt status bit for nsmi interrupt. bit 0: a one disables the corresponding interrupt status bit for nsmi interrupt. beep control register 3-- index 53h ( bank 4 ) register location: 53h power on default value <7:0> 0000,0000. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 en_5vsb_bp en_vbat_bp reserved reserved reserved en_user_bp reserved reserved bit 7-6: reserved. bit 5: user define beep output function. if this bit is 1, the beep is always active. if this bit is 0, this function is inactive. (default 0) bit 4-2: reserved. bit 1: enable beep output from vbat. if this bit is 1, enable beep output, which is default value. bit 0: enable beep output from 5vsb. if this bit is 1, enable beep output, which is default value. 51 reserved register -- index 54h--58h real time hardware status register i -- index 59h ( bank 4 ) register location: 59h power on default value <7:0> 0000,0000. reset by mr. attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 vcorea_sts vinr0_sts +3.3vin_sts +5vin_sts temp1_sts temp2_sts fan1_sts fan2_sts bit 7: fan 2 status. set 1, the fan speed counter is over the limit value. set 0, the fan speed counter is in the limit range. bit 6: fan 1 status. set 1, the fan speed counter is over the limit value. set 0, the fan speed counter is in the limit range. bit 5: temperature sensor 2 status. set 1, the voltage of temperature sensor is over the limit value. set 0, the voltage of temperature sensor is in the limit range. bit 4: temperature sensor 1 status. set 1, the voltage of temperature sensor is over the limit value. set 0, the voltage of temperature sensor is in the limit range. bit 3: +5v voltage status. set 1, the voltage of +5v is over the limit value. set 0, the voltage of +5v is in the limit range. bit 2: +3.3v voltage status. set 1, the voltage of +3.3v is over the limit value. set 0, the voltage of +3.3v is in the limit range. bit 1: vinr0 voltage status. set 1, the voltage of vinr0 is over the limit value. set 0, the voltage of vinr0 is in the limit range. bit 0: vcorea voltage status. set 1, the voltage of vcore a is over the limit value. set 0, the voltage of vcore a is in the limit range. 52 real time hardware status register ii -- index 5ah ( bank 4 ) register location: 5ah power on default value <7:0> 0000,0000. reset by mr. attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 +12vin_sts -12vin_sts -5vin_sts fan3_sts case_sts temp3_sts reserved reserved bit 7-6: reserved bit 5: temperature sensor 3 status. set 1, the voltage of temperature sensor is over the limit value. set 0, the voltage of temperature sensor is in the limit range. bit 4: case open status. set 1, the case open sensor is sensed the high value. set 0 bit 3: fan3 voltage status. set 1, the fan speed counter is over the limit value. set 0, the fan speed counter is during the limit range. bit 2: -5v voltage status. set 1, the voltage of -5v is over the limit value. set 0, the voltage of -5v is during the limit range. bit 1: -12v voltage status. set 1, the voltage of -12v is over the limit value. set 0, the voltage of - 12v is during the limit range. bit 0: +12v voltage status. set 1, the voltage of +12v is over the limit value. set 0, the voltage of +12v is in the limit range. real time hardware status register iii -- index 5bh ( bank 4 ) register location: 5bh power on default value <7:0> = 0000,0000h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 5vsb_sts vbat_sts reserved reserved reserved reserved reserved reserved bit 7-2: reserved. bit 1: vbat voltage status. set 1, the voltage of vbat is over the limit value. set 0, the voltage of vbat is in the limit range. bit 0: 5vsb voltage status. set 1, the voltage of 5vsb is over the limit value. set 0, the voltage of 5vsb is in the limit range. 53 pwmout3/4 clock select -- index 5ch ( bank 4 ) register location: 5ch power on default value <7:0> 0001,0001. reset by mr. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 pwm3clksel pwm3clksel pwm3clksel reserved pwm4clksel pwm4clksel pwm4clksel reserved bit 7: reserved. bit 6-4: pwmout4 clock selection. the clock frequency definition is same as pwmout3 clock selection. bit 3: reserved. bit 2-0: pwmout3 clock selection. <2:0> = 000: 46.87khz <2:0> = 001: 23.43khz (default) <2:0> = 010: 11.72khz <2:0> = 011: 5.85khz <2:0> = 100: 2.93khz value ram 2 ! ! ! ! index 50h - 5ah (auto-increment) (bank 5) address a6-a0 auto-increment description 50h 5vsb reading 51h vbat reading 52h reserved 53h reserved 54h 5vsb high limit 55h 5vsb low limit. 56h vbat high limit 57h vbat low limit smsc test register - index 50h ( bank 6 ) 54 specifications absolute maximum ratings parameter rating unit power supply voltage -0.5 to 7.0 v input voltage -0.5 to vdd+0.5 v operating temperature 0 to +70 % c storage temperature -55 to +150 % c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc characteristics (ta = 0 % c to 70 % c, vdd = 5v $ 10%, vss = 0v) parameter sym. min. typ. max. unit conditions i/o 12t - ttl level bi-directional pin with source-sink capability of 12 ma input low voltage vil 0.8 v input high voltage vih 2.0 v output low voltage vol 0.4 v iol = 12 ma output high voltage voh 2.4 v ioh = - 12 ma input high leakage ilih +10 & a vin = vdd input low leakage ilil -10 & a vin = 0v i/o 12ts - ttl level bi-directional pin with source-sink capability of 12 ma and schmitt-trigger level input input low threshold voltage vt- 0.5 0.8 1.1 v vdd = 5 v input high threshold voltage vt+ 1.6 2.0 2.4 v vdd = 5 v hysteresis vth 0.5 1.2 v vdd = 5 v output low voltage vol 0.4 v iol = 12 ma output high voltage voh 2.4 v ioh = - 12 ma input high leakage ilih +10 & a vin = vdd input low leakage ilil -10 & a vin = 0v out 12t - ttl level output pin with source-sink capability of 12 ma output low voltage vol 0.4 v iol = 12 ma output high voltage voh 2.4 v ioh = -12 ma od 8 - open-drain output pin with sink capability of 8 ma output low voltage vol 0.4 v iol = 8 ma od 12 - open-drain output pin with sink capability of 12 ma output low voltage vol 0.4 v iol = 12 ma od 48 - open-drain output pin with sink capability of 48 ma output low voltage vol 0.4 v iol = 48 ma in t - ttl level input pin input low voltage vil 0.8 v 55 parameter sym. min. typ. max. unit conditions input high voltage vih 2.0 v input high leakage ilih +10 & a vin = vdd input low leakage ilil -10 & a vin = 0 v in ts - ttl level schmitt-triggered input pin input low threshold voltage vt- 0.5 0.8 1.1 v vdd = 5 v input high threshold voltage vt+ 1.6 2.0 2.4 v vdd = 5 v hysteresis vth 0.5 1.2 v vdd = 5 v input high leakage ilih +10 & a vin = vdd input low leakage ilil -10 & a vin = 0 v 56 ac characteristics isa read/write interface timing aen sa[2:0],ncs nior sd[7:0] irq t ar t rvd valid data t rd t ra t rdh t ri t rcu rc isa bus read timin g niow aen sa[2:0],ncs niow sd[7:0] irq t aw t ds valid data t wr t wa t dh t wi t wcu wc nior valid valid isa bus write timin g 57 isa read/write timing parameter symbol min. max. unit valid address to read active t - ar 10 ns valid address to write active t aw 10 ns data hold t dh 5 ns data setup t ds 80 ns address hold from inactive read t ra 40 ns read cycle update t rcu 200 ns read strobe width t rd 120 ns read data hold t rdh 40 ns read strobe to clear irq t ri 60 ns active read to valid data t rvd 115 ns address hold from inactive write t wa 5 ns write cycle update t wcu 80 ns write strobe to clear irq t wi 60 ns write strobe width t wr 120 ns read cycle = t ar + t rd +t rcv rc 210 ns write cycle = t aw +t wr - t wcv wc 210 ns serial bus timing diagram valid data scl sda in sda out t hd;sda t scl t hd;dat t su;sto t su;dat serial bus timing diagram serial bus timing parameter symbol min. max. unit scl clock period t - scl 10 us start condition hold time t hd;sda 4.7 us stop condition setup-up time t su;sto 4.7 us data to scl setup time t su;dat 120 ns data to scl hold time t hd;dat 5 ns scl and sda rise time t r 1.0 us scl and sda fall time t f 300 ns 58 package dimensions (48 pin tqfp) 2 1 a h d d e b e h e y a a seating plane l l 1 see detail f detail f c 37 48 1 12 13 24 25 36 1. dimensions d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeters 4. general appearance spec. should be based on final visual ins p ection s p ec. notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 1.40 0.20 0.50 1.00 7.00 9.00 9.00 7.00 --- --- --- 1.60 0.15 1.45 1.35 0.05 0.17 0.27 --- 0.09 0.20 0.45 0.60 0.75 0.08 0 3.5 7 --- --- MON35W42 revisions page(s) section/figure/entry correction date revised 39 diode selection register -- index 59h (bank 0) added the content of diode selection register index 59h (bank 0 ) 04/19/00 41 vbat monitor control register -- index 5dh ( bank 0 ) modified vbat monitor control resgister index 5dh (bank 0 ) 04/19/00 n/a original release -------------------------------------------------------- 01/12/99 ? standard microsystems corporation (smsc) 2000 80 arkay drive hauppauge, ny 11788 (631) 435-6000 fax (631) 273-3123 standard microsystems is a registered trademark of standard microsystems corporation, and smsc is a trademark of standard microsystems corporation. pentium is a registered trademark of intel corporation. product names and company names are the trademarks of their respective holders. circuit diagrams utilizing smsc products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and product descriptions at any time without notice. contact your local smsc sales office to obtain the latest specifications before placing your product order. the provision of this information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of smsc or others. all sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are available upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at http://www.smsc.com. smsc disclaims and excludes any and all warranties, including without limitation any and all implied warranties of merchantability, fitness for a particular purpose, title, and against infringement, and any and all warranties arising from any course of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indirect, special, punitive, or consequential damages, or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contract, tort, negligence of smsc or others, strict liability, breach of warranty, or otherwise; whether or not any remedy is held to have failed of its essential purpose; and whether or not smsc has been advised of the possibility of such damages. MON35W42 rev. 04/19/2000 |
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