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nbm ? bus converter rev 1.1 vicorpower.com page 1 of 26 09/2015 800 927.9474 nbm ? bus converter non-isolated, fixed ratio dc-dc converter nbm6123x46c15a6yzz c us s nrtl cus features ? up to 160 a continuous output current ? 3532 w/in 3 power density ? parallel operation for multi-kw arrays ? ov, oc, uv, short circuit and thermal protection ? 6123 through-hole chip package n 2.402? x 0.990? x 0.286? (61.00 mm x 25.14 mm x 7.26 mm) typical applications ? dc power distribution ? high end computing systems ? automated test equipment ? industrial systems ? high density power supplies ? communications systems ? transportation product description the vi chip? non-isolated bus converter (nbm?) is a high efficiency sine amplitude converter? (sac?), operating from a 36 to 46 vdc primary bus to deliver a non-isolated, ratiometric output from 12.0 to 15.3 vdc. the nbm6123x46c15a6yzz offers low noise, fast transient response, and industry leading efficiency and power density. in addition, it provides an ac impedance beyond the bandwidth of most downstream regulators, allowing input capacitance normally located at the input of a pol regulator to be located at the primary side of the nbm module. with a primary to secondary k factor of 1/3, that capacitance value can be reduced by a factor of 9x, resulting in savings of board area, material and total system cost. leveraging the thermal and density bene?ts of vicors chip packaging technology, the nbm module offers ?exible thermal management options with very low top and bottom side thermal impedances. thermally-adept chip-based power components, enable customers to achieve low cost power system solutions with previously unattainable system size, weight and efficiency attributes, quickly and predictably. the nbm non-isolated topology allows operation in forward and reverse directions and provides bidirectional protections. however if power train is disabled by any protection, and v sec is present, then voltage equal to v sec minus two diode drops will appear on primary side. product ratings v pri = 42 v (36 ? 46 v) p sec = up to 2400 w v sec = 14 v (12.0 ? 15.3 v) ( no load ) k = 1/3
nbm ? bus converter rev 1.1 vicorpower.com page 2 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz typical application nbm6123x46c15a6yzz+ point of load nbm vaux en +v pri sgnd +v sec v pri enable/disable switch fuse primary secondary source_rtn c i_nbm_elec tm pol pgnd
nbm ? bus converter rev 1.1 vicorpower.com page 3 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz pin configuration 1 2 a b c d e f g h +v pri +v sec top view 6123 chip package i pgnd1 pgnd1 +v sec +v sec pgnd1 +v sec pgnd1 +v pri j +v pri k +v pri l a b c d e f g h i j k l +v sec pgnd2 pgnd2 +v sec +v sec pgnd2 +v sec pgnd2 sgnd tm en vaux pin descriptions pin number signal name type function i1, j1, k1, l1 +v pri primary power positive primary transformer power terminal i?2 tm output temperature monitor; primary side referenced signals j?2 en input enables and disables power supply; primary side referenced signals k?2 vaux output auxilary voltage source; primary side referenced signals l?2 sgnd signal return signal return terminal only. do not connect to pgnd a1, d1, e1, h1, a?2, d?2, e?2, h?2 +v sec secondary power positive secondary transformer power terminal b1, c1, f1, g1 b?2, c?2, f?2, g?2 pgnd* secondary power return transformer power return terminal *for proper operation an external low impedance connection must be made between listed -pgnd1 and pgnd2 terminals.
nbm ? bus converter rev 1.1 vicorpower.com page 4 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz absolute maximum ratings the absolute maximum ratings below are stress ratings only. operation at or beyond these maximum ratings can cause permanent da mage to the device. parameter comments min max unit +v pri_dc to ?v pri_dc -1 60 v v pri_dc or v sec_dc slew rate (operational) 1 v/s +v sec_dc to ?v sec_dc -1 20 v tm to ?v pri_dc -0.3 4.6 v en to ?v pri_dc 5.5 v vaux to ?v pri_dc 4.6 v part ordering information standard models all products shipped in jedec standard high profile (0.400? thick) trays (jedec publication 95, design guide 4.10). product function package size package mounting max primary input voltage range identifier max secondary voltage secondary output current temperature grade option nbm 6123 x 46 c 15 a6 y zz non-isolated bus converter module 61 = l 23 = w t = th s = smt 46 v 36 ? 46 v 15 v no load 160 a t = -40c ? 125c m = -55c ? 125c 00 = analog ctrl 01 = pmbus ctrl 0r = reversible analog ctrl 0p = reversible pmbus ctrl product function package size package mounting max primary input voltage range identifier max secondary voltage secondary output current temperature grade option nbm 6123 t 46 c 15 a6 t 0r
nbm ? bus converter rev 1.1 vicorpower.com page 5 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz electrical specifications specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of -40c t internal 125c (t-grade); all other specifications are at t internal = 25oc unless otherwise noted . attribute symbol conditions / notes min ty p max unit general powetrain primary to secondary specification (forward direction) primary input voltage range, continuous v pri_dc 36 46 v v pri controller v c_active v pri_dc voltage where c is initialized, (ie vaux = low, powertrain inactive) 15 v pri to sec input quiescent current i pri_q disabled, en low, v pri_dc = 42 v 8 ma t internal 100oc 12 pri to sec no load power dissipation p pri_nl v pri_dc = 42 v, t internal = 25oc 12.5 19.5 w v pri_dc = 42 v 5 28 v pri_dc = 36 v to 46 v, t internal = 25 oc 22 v pri_dc = 36 v to 46 v 31 pri to sec inrush current peak i pri_inr_pk v pri_dc = 46 v, c sec_ext = 3000 f, r load_sec = 20% of full load current 30 a t internal 100oc 75 dc primary input current i pri_in_dc at i sec_out_dc = 160 a, t internal 100oc 53.9 a transformation ratio k primary to secondary, k = v sec_dc / v pri_dc , at no load 1/3 v/v secondary output power (continuous) p sec_out_dc specified at v pri_dc = 46 v 2400 w secondary output power (pulsed) p sec_out_pulse specified at v pri_dc = 46 v; 10 ms pulse, 25% duty cycle, p sec_avg = 50% rated p sec_out_dc 2650 w secondary output current (continuous) i sec_out_dc 160 a secondary output current (pulsed) i sec_out_pulse 10 ms pulse, 25% duty cycle, i sec_out_avg = 50% rated i sec_out_dc 176 a pri to sec efficiency (ambient) amb v pri_dc = 42 v, i sec_out_dc = 160 a 97.4 98 % v pri_dc = 36 v to 46 v, i sec_out_dc = 160 a 97.1 v pri_dc = 42 v, i sec_out_dc = 80 a 97.5 98.2 pri to sec efficiency (hot) hot v pri_dc = 42 v, i sec_out_dc = 160 a 96.9 97.4 % pri to sec efficiency (over load range) 20% 32 a < i sec_out_dc < 160 a 90 % pri to sec output resistance r sec_cold v pri_dc = 42 v, i sec_out_dc = 160 a, t internal = -40c 0.8 0.95 1.1 m r sec_amb v pri_dc = 42 v, i sec_out_dc = 160 a 0.9 1.3 1.7 r sec_hot v pri_dc = 42 v, i sec_out_dc = 160 a, t internal = 100c 1.5 1.75 2.0 switching frequency f sw frequency of the output voltage ripple = 2x fsw 1.14 1.20 1.26 mhz secondary output voltage ripple v sec_out_pp c sec_ext = 0 f, i sec_out_dc = 160 a, v pri_dc = 42 v, 20 mhz bw 110 mv t internal 100oc 205 primary input leads inductance (parasitic) l pri_in_leads frequency 2.5 mhz (double switching frequency), simulated lead model 3 nh secondary output leads inductance (parasitic) l sec_out_leads frequency 2.5 mhz (double switching frequency), simulated lead model 0.64 nh
nbm ? bus converter rev 1.1 vicorpower.com page 6 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz electrical specifications (cont.) specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of -40c t internal 125c (t-grade); all other specifications are at t internal = 25oc unless otherwise noted . attribute symbol conditions / notes min ty p max unit general powetrain primary to secondary specification (forward direction) cont. effective primary capacitance (internal) c pri_int effective value at 42 v pri_dc 16.8 f effective secondary capacitance (internal) c sec_int effective value at 14 v sec_dc 140 f effective secondary output capacitance (external) c sec_out_ext excessive capacitance may drive module into sc protection 3000 f effective secondary output capacitance (external) c sec_out_aext c sec_out_aext max = n * 0.5 * c sec_out_ext max , where n = the number of units in parallel protection primary to secondary (forward direction) auto restart time t auto_restart startup into a persistent fault condition. non-latching fault detection given v pri_dc > v pri_uvlo+ 940 1010 ms primary overvoltage lockout threshold v pri_ovlo+ 48 50 52 v primary overvoltage recovery threshold v pri_ovlo- 46 48 50 v primary overvoltage lockout hysteresis v pri_ovlo_hyst 2 v primary overvoltage lockout response time t pri_ovlo 30 s primary undervoltage lockout threshold v pri_uvlo- 28 30 32 v primary undervoltage recovery threshold v pri_uvlo+ 30 32 34 v primary undervoltage lockout hysteresis v pri_uvlo_hyst 2 v primary undervoltage lockout response time t pri_uvlo 100 s primary undervoltage startup delay t pri_uvlo+_delay from v pri_dc = v pri_uvlo+ to powertrain active, en floating, (i.e one time startup delay form application of v pri_dc to v sec_dc ) 30 ms primary soft-start time t pri_soft-start from powertrain active. fast current limit protection disabled during soft-start 1 ms secondary output overcurrent trip threshold i sec_out_ocp 177 200 240 a secondary output overcurrent response time constant t sec_out_ocp effective internal rc filter 4 ms secondary output short circuit protection trip threshold i sec_out_scp 240 a secondary output short circuit protection response time t sec_out_scp 1 s overtemperature shutdown threshold t otp+ temperature sensor located inside controller ic 125 c overtemperature recovery threshold t otp? 105 110 115 c undertemperature shutdown threshold t utp temperature sensor located inside controller ic; protection not available for m-grade units. -45 c undertemperature restart time t utp_restart startup into a persistent fault condition. non-latching fault detection given v pri_dc > v pri_uvlo+ 3 s
nbm ? bus converter rev 1.1 vicorpower.com page 7 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz attribute symbol conditions / notes min ty p max unit general powetrain secondary to primary specification (reverse direction) secondary input voltage range, continuous v sec_dc 12 15.3 v sec to pri no load power dissipation p sec_nl v sec_dc = 14 v, t internal = 25oc 12.5 20 w v sec_dc = 14 v 5 29 v sec_dc = 12 v to 15.3 v, t internal = 25oc 22 v sec_dc = 12 v to 15.3 v 31 dc secondary input current i sec_in_dc at i pri_dc = 53.3 a, t internal 100oc 162 a primary ouptut power (continuous) p pri_out_dc specified at v sec_dc = 15.3 v 2400 w primary output power (pulsed) p pri_out_pulse specified at v sec_dc = 15.3 v; 10 ms pulse, 25% duty cycle, p pri_avg = 50% rated p pri_out_dc 2650 w primary output current (continuous) i pri_out_dc 53.3 a primary output current (pulsed) i pri_out_pulse 10 ms pulse, 25% duty cycle, i pri_out_avg = 50% rated i pri_out_dc 58.7 a sec to pri efficiency (ambient) amb v sec_dc = 14 v, i pri_out_dc = 53.3 a 97 98 % v sec_dc = 12 v to 15.3 v, i pri_out_dc = 53.3 a 96.7 v sec_dc = 14 v, i pri_out_dc = 26.7 a 97.6 98.3 sec to pri efficiency (hot) hot v sec_dc = 14 v, i pri_out_dc = 53.3 a 96.6 97 % sec to pri efficiency (over load range) 20% 10.66 a < i pri_out_dc < 53.3 a 90 % sec to pri output resistance r pri_cold v sec_dc = 14 v, i pri_out_dc = 53.3 a, t internal = -40c 10 12 14 m r pri_amb v sec_dc = 14 v, i pri_out_dc = 53.3 a 12 16 20 r pri_hot v sec_dc = 14 v, i pri_out_dc = 53.3 a, t internal = 100c 16 19 22 primary output voltage ripple v pri_out_pp c pri_out_ext = 0 f, i pri_out_dc = 53.3 a, v sec_dc = 14 v, 20 mhz bw 330 mv t internal 100oc 615 electrical specifications (cont.) specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of -40c t internal 125c (t-grade); all other specifications are at t internal = 25oc unless otherwise noted .
nbm ? bus converter rev 1.1 vicorpower.com page 8 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz attribute symbol conditions / notes min ty p max unit protection secondary to primary (reverse direction) effective primary output capacitance (external) c pri_out_ext excessive capacitance may drive module into sc protection when starting from secondary to primary 300 f secondary overvoltage lockout threshold v sec_ovlo+ 16 16.7 17.4 v secondary overvoltage recovery threshold v pri_ovlo- 15.3 16 16.7 v secondary overvoltage lockout response time t pri_ovlo 30 s secondary undervoltage lockout threshold v sec_uvlo- 9.3 10 10.7 v secondary undervoltage recovery threshold v pri_uvlo+ 10 10.7 11.4 v secondary undervoltage lockout response time t sec_uvlo 100 s primary output overcurrent trip threshold i pri_out_ocp powertrain is stopped but current can flow from secondary to primary through mosfet body diodes 59 66.7 80 a primary output overcurrent response time constant t pri_out_ocp effective internal rc filter 4 ms primary short circuit protection trip threshold i pri_scp powertrain is stopped but current can flow from secondary to primary through mosfet body diodes 80 a primary short circuit protection response time t pri_scp 1 s electrical specifications (cont.) specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of -40c t internal 125c (t-grade); all other specifications are at t internal = 25oc unless otherwise noted .
nbm ? bus converter rev 1.1 vicorpower.com page 9 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz secondary output current (a) primary input voltage (v) i sec_out_dc i sec_out_pulse 65 80 95 110 125 140 155 170 185 200 215 36 37 38 39 40 41 42 43 44 45 46 secondary output power (w) primary input voltage (v) p sec_out_dc p sec_out_pulse 800 1050 1300 1550 1800 2050 2300 2550 2800 3050 3300 36 37 38 39 40 41 42 43 44 45 46 figure 1 ? specified thermal operating area figure 2 ? specified electrical operating area using rated r sec_hot secondary output capacitance (% rated c sec_ext_max ) secondary output current (% i sec_out_dc ) 0 10 20 30 40 50 60 70 80 90 100 110 0 20 40 60 80 100 secondary output current (a) case temperature (c) top only at temperature leads at temperature top and leads at temperature top, leads, & belly at temperature 0 20 40 60 80 100 120 140 160 180 200 25 50 75 100 125 figure 3 ? specified primary start-up into load current and external capacitance
nbm ? bus converter rev 1.1 vicorpower.com page 10 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz signal characteristics specifications apply over all line, load conditions, unless otherwise noted; boldface specifications apply over the temperature range of -40c t internal 125c (t-grade); all other specifications are at t internal = 25oc unless otherwise noted. temperature monitor ? the tm pin is a standard analog i/o configured as an output from an internal c. ? the tm pin monitors the internal temperature of the controller ic within an accuracy of 5c. ? c 250 khz pwm output internally pulled high to 3.3 v. signal type state attribute symbol conditions / notes min typ max unit digital output startup powertrain active to tm time t tm 100 s regular operation tm duty cycle tm pwm 18.18 68.18 % tm current i tm 4 ma recommended external filtering tm capacitance (external) c tm_ext recommended external filtering 0.01 f tm resistance (external) r tm_ext recommended external filtering 1 k specifications using recommended filter tm gain a tm 10 mv / c tm voltage reference v tm_amb 1.27 v tm voltage ripple v tm_pp r tm_ext = 1 k ohm, c tm_ext = 0.01 uf, v pri_dc = 42 v, i sec_dc = 160 a 28 mv t internal 100oc 40 enable / disable control ? the en pin is a standard analog i/o configured as an input to an internal c. ? it is internally pulled high to 3.3 v. ? when held low the nbm? internal bias will be disabled and the powertrain will be inactive. ? in an array of nbms, en pins should be interconnected to synchronize startup. ? unit must not be disabled if a load is present on +vpri while in reverse operation. signal type state attribute symbol conditions / notes min typ max unit analog input startup en to powertrain active time t en_start v pri_dc > v pri_uvlo+ , en held low both conditions satisfied for t > t pri_uvlo+_delay 250 s regular operation en voltage threshold v en_th 2.3 v en resistance (internal) r en_int internal pull up resistor 1.5 k en disable threshold v en_disable_th 1 v
nbm ? bus converter rev 1.1 vicorpower.com page 11 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz auxiliary voltage source ? the vaux pin is a standard analog i/o configured as an output from an internal c. ? vaux is internally connected to c output as internally pulled high to a 3.3 v regulator with 2% tolerance, a 1% resistor of 1.5 k . ? vaux can be used as a "ready to process full power" flag. this pin transitions vaux voltage after a 2 ms delay from the start of powertrain activating, signaling the end of softstart. ? vaux can be used as "fault flag". this pin is pulled low internally when a fault protection is detected. signal type state attribute symbol conditions / notes min typ max unit analog output startup powertrain active to vaux time t vaux powertrain active to vaux high 2 ms regular operation vaux voltage v vaux 2.8 3.3 v vaux available current i vaux 4 ma vaux voltage ripple v vaux_pp 50 mv t internal 100oc 100 vaux capacitance (external) c vaux_ext 0.01 f vaux resistance (external) r vaux_ext v pri_dc < v c_active 1.5 k fault vaux fault response time t vaux_fr from fault to v vaux = 2.8 v, c vaux = 0 pf 10 s signal characteristics (cont.) specifications apply over all line, load conditions, unless otherwise noted; boldface specifications apply over the temperature range of -40c t internal 125c (t-grade); all other specifications are at t internal = 25oc unless otherwise noted. signal ground ? signal ground is internally connect to pgnd through a zero ohm resistor. ? internal sgnd traces are not designed to support high current.
nbm ? bus converter rev 1.1 vicorpower.com page 12 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz nbm? forward direction timing diagram en tm +v pri bidir input +v sec output v pri_ d c inp u t tu r n- o n s eco nda ry o utpu t tu rn-on prim a ry i nput o v er voltage v p r i _ d c input rest a rt enable pulled low ena b l e p u lled h i g h s h o rt circ u i t ev ent p rim a r y in pu t v o l ta g e tu r n -o ff output output v aux en & v a u x interna l p u ll -u p startup over voltage enable control over current shutdown c initializ e v pri_ovlo- v pri_ovlo+ v pri_uvlo+ v c_active v nom v pri_uvlo- t sec_out_scp t pri _ uvlo+_delay t vaux t auto-restart > t pri _ uvlo+_delay
nbm ? bus converter rev 1.1 vicorpower.com page 13 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz nbm? reverse direction timing diagram en tm +v sec bidir input +v pri output v se c _dc input turn- o n p r imary o utput turn-on s e cond a ry ove r voltage v s ec _dc i npu t re s t art e na bl e p ul led low e nab l e pulle d h i gh over current / s h or t cir c u i t e v ent sec o n d ar y input voltage turn-off output output v aux e n & va ux in te rna l p u l l -u p startup over voltage enable control over current shutdown c ini t ializ e v sec_ovlo- v sec_ovlo+ v sec_uvlo+ v c_active v nom v sec_uvlo- t pri_out_ocp t pri _ uvlo+_delay t vaux t auto-restart > t pri _ uvlo+_delay v pri =+v sec ?~1.4v) not supported condition, permanent damage may occur red line: load must not be present to prenevent damage to unit
nbm ? bus converter rev 1.1 vicorpower.com page 14 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz fault sequence tm low en high vaux low powertrain stopped v c_active < v pri_dc < v pri_uvlo+ v pri_dc > v pri_uvlo+ or v sec_dc > v sec_uvlo+ t pri_uvlo+_delay expired one time delay initial startup fault auto- recovery enable falling edge, or otp detected input ovlo or uvlo, output ocp, utp, ovlo or uvlo, or input ocp detected enable falling edge, or otp detected input ovlo or uvlo, output ocp, utp, ovlo or uvlo, or input ocp detected short circuit detected sustained operation tm pwm en high vaux high powertrain active startup sequence tm low en high vaux low powertrain stopped standby sequence tm low en high vaux low powertrain stopped note: during reverse direction operation a load must not be present if the powertrain is in any stopped state while the supply voltage is present on +vsec. v c_active < v sec_dc < v pri_uvlo+ k application of input voltage to v pri_dc application of input voltage to v sec_dc high level functional state diagram conditions that cause state transitions are shown along arrows. sub-sequence activities listed inside the state bubbles.
nbm ? bus converter rev 1.1 vicorpower.com page 15 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz application characteristics product is mounted and temperature controlled via top side cold plate, unless otherwise noted. all data presented in this secti on are collected data form primary sourced units processing power in forward direction.see associated figures for general trend data. pri to sec, power dissipation (w) primary input voltage (v) - 40? 25? 80? t top surface case : 6 8 10 12 14 16 18 20 36 37 38 39 40 41 42 43 44 45 46 case temperature (oc) 36 v 42 v 46 v pri to sec, full load efficiency (%) v pri : 97.0 97.5 98.0 98.5 -40 -20 0 20 40 60 80 100 pri to sec, efficiency (%) secondary output current (a) 36 v 42 v 46 v v pri : pri to sec, power dissipation 0 8 16 24 32 40 48 56 64 72 80 88 88 89 90 91 92 93 94 95 96 97 98 99 0 16 32 48 64 80 96 112 128 144 160 p d figure 4 ? no load power dissipation vs. v pri_dc figure 5 ? full load efficiency vs. temperature; v pri_dc figure 6 ? efficiency and power dissipation at t case = -40c pri to sec, efficiency (%) secondary output current (a) 36 v 42 v 46 v v pri : pri to sec, power dissipation 0 8 16 24 32 40 48 56 64 72 80 88 88 89 90 91 92 93 94 95 96 97 98 99 0 16 32 48 64 80 96 112 128 144 160 p d secondary output current (a) 36 v 42 v 46 v v pri: pri to sec, efficiency (%) pri to sec, power dissipation 0 8 16 24 32 40 48 56 64 72 80 88 88 89 90 91 92 93 94 95 96 97 98 99 0 16 32 48 64 80 96 112 128 144 160 p d figure 7 ? efficiency and power dissipation at t case = 25c case temperature (c) 160 a i sec_out : pri to sec, output resistance (m) 0.5 1.0 1.5 2.0 -40 -20 0 20 40 60 80 100 figure 8 ? efficiency and power dissipation at t case = 80c figure 9 ? r out vs. temperature; nominal v pri_dc i sec_dc = 160 a at t case = 80c
nbm ? bus converter rev 1.1 vicorpower.com page 16 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz figure 12 ? 0 a? 160 a transient response: c pri_out_ext = 270 f, no external c sec_out_ext figure 11 ? full load ripple, 270 f c pri_out_ext ; no external c sec_out_ext . board mounted module, scope setting : 20 mhz analog bw secondary output current (a) 42 v v pri : secondary output voltage ripple (mv) 0 20 40 60 80 100 120 140 0 16 32 48 64 80 96 112 128 144 160 figure 10 ? v sec_out_pp vs. i sec_dc ; no external c sec_out_ext . board mounted module, scope setting : 20 mhz analog bw figure 13 ? 160 a ? 0 a transient response: c in = 270 f, no external c sec_out_ext figure 14 ? start up from application of v pri_dc = 42 v, 20% i out , 100% c sec_out_ext figure 15 ? start up from application of en with pre-applied v pri_dc = 42 v, 20% i sec_dc , 100% c sec_out_ext
nbm ? bus converter rev 1.1 vicorpower.com page 17 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz general characteristics specifications apply over all line, load conditions, unless otherwise noted; boldface specifications apply over the temperature range of -40c t internal 125c (t-grade); all other specifications are at t internal = 25oc unless otherwise noted. attribute symbol conditions / notes min ty p max unit mechanical length l 60.87 / [2.396] 61.00 / [2.402] 61.13 / [2.407] mm/[in] width w 24.76 / [0.975] 25.14 / [0.990] 25.52 / [1.005] mm/[in] height h 7.21 / [0.284] 7.26 / [0.286] 7.31 / [0.288] mm/[in] volume vol without heatsink 11.13 / [0.679] cm 3 /[in 3 ] weight w 41 / [1.45] g/[oz] lead finish nickel 0.51 2.03 m palladium 0.02 0.15 gold 0.003 0.051 thermal operating temperature t internal nbm6123t46c15a6t0r (t-grade) -40 125 c thermal resistance top side int-top estimated thermal resistance to maximum temperature internal component from isothermal top 1.36 c/w thermal resistance leads int-leads estimated thermal resistance to maximum temperature internal component from isothermal leads 1.36 c/w thermal resistance bottom side int-bottom estimated thermal resistance to maximum temperature internal component from isothermal bottom 1.24 c/w thermal capacity 34 ws/c assembly storage temperature nbm6123t46c15a6t0r (t-grade) -40 125 c esd withstand esd hbm human body model, "esda / jedec jds-001-2012" class i-c (1kv to < 2 kv) esd cdm charge device model, "jesd 22-c101-e" class ii (200v to < 500v)
nbm ? bus converter rev 1.1 vicorpower.com page 18 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz [1] product is not intended for reflow solder attach. general characteristics specifications apply over all line, load conditions, unless otherwise noted; boldface specifications apply over the temperature range of -40c t internal 125c (t-grade); all other specifications are at t internal = 25oc unless otherwise noted. soldering [1] peak temperature top case 135 c safety isolation voltage / dielectric test v hipot primary to secondary n/a v primary to case 2250 secondary to case 2250 isolation capacitance c pri_sec unpowered unit n/a n/a n/a pf insulation resistance r pri_sec at 500 vdc 0 m mtbf mil-hdbk-217plus parts count - 25c ground benign, stationary, indoors / computer 3.34 mhrs telcordia issue 2 - method i case iii; 25c ground benign, controlled 5.26 mhrs agency approvals / standards ctuvus; en 60950-1 curus; ul 60950-1 ce marked for low voltage directive and rohs recast directive, as applicable
nbm ? bus converter rev 1.1 vicorpower.com page 19 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz q03 c04 current flow detection + forward i pri_dc sense sepic en cr +v pri signal pins sgnd en tm pwm primary stage fast current limit analog controller digital controller cntrl on/off q04 +v cc1 sgnd slow current limit modulator gate drive transformer 1.5 k 1.5 k soft-start vaux over-temp under-temp over voltage undervoltage startup / re-start delay temperature sensor c02 +v sec pgnd2 half-bridge synchronous rectification secondary stage q07 q08 q01 q02 lr current sense 0 full bridge differential current sensing pgnd1 c01 +v sec vaux en tm sgnd +v cc2 sepic +v sec c03 pgnd1 +v pri 3.3v linear regulator q05 q06 pgnd2 -v cc nbm? module block diagram
nbm ? bus converter rev 1.1 vicorpower.com page 20 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz the sine amplitude converter (sac?) uses a high frequency resonant tank to move energy from primary to secondary and vice versa. (the resonant tank is formed by cr and leakage inductance lr in the power transformer windings as shown in the nbm? module block diagram). the resonant lc tank, operated at high frequency, is amplitude modulated as a function of input voltage and output current. a small amount of capacitance embedded in the primary and secondary stages of the module is sufficient for full functionality and is key to achieving high power density. the nbm6123x46c15a6yzz sac can be simpli?ed into the preceeding model. at no load: v sec = v pri ? k (1) k represents the turns ratio of the sac. rearranging eq (1): k= v sec (2) v pri in the presence of load, v out is represented by: v sec = v pri ? k C i sec ? r sec (3) and i out is represented by: i sec = i pri Ci pri_q (4) k r out represents the impedance of the sac, and is a function of the r dson of the input and output mosfets and the winding resistance of the power transformer. i q represents the quiescent current of the sac control, gate drive circuitry, and core losses. the use of dc voltage transformation provides additional interesting attributes. assuming that r sec = 0 and i pri_q = 0 a, eq. (3) now becomes eq. (1) and is essentially load independent, resistor r is now placed in series with v in . the relationship between v pri and v sec becomes: v sec = (v pri Ci pri ? r in ) ? k (5) substituting the simpli?ed version of eq. (4) (i pri_q is assumed = 0 a) into eq. (5) yields: v sec = v pri ? k C i sec ? r in ? k 2 (6) +v sec +v pri v?i k + + ? pgnd 220 ma 1/3 ? i sec 1/3 ? v pri c pri_int_esr 0.5 m 1.8 nh 140 f i pri_q l pri_in_leads = 3 nh i sec r sac k = 1/32 vin vout + ? v pri v sec r in sac? k = 1/3 figure 17 ? k = 1/3 sine amplitude converter with series input resistor figure 16 ? nbm module ac model c sec_int l sec_out_leads = 0.64 nh c pri_int 16.8 f 1.3 m r sec c sec_int_esr 60.4 sine amplitude converter? point of load conversion 1.3 m
nbm ? bus converter rev 1.1 vicorpower.com page 21 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz this is similar in form to eq. (3), where r sec is used to represent the characteristic impedance of the sac?. however, in this case a real r on the primary side of the sac is effectively scaled by k 2 with respect to the secondary. assuming tha tr=1,the effective r as seen from the secondary side is 111 m, with k = 1/3 . a similar exercise should be performed with the additon of a capacitor or shunt impedance at the primary input to the sac. a switch in series with v pri is added to the circuit. this is depicted in figure 18. a change in v pri with the switch closed would result in a change in capacitor current according to the following equation: i c (t) = c dv pri (7) dt assume that with the capacitor charged to v pri , the switch is opened and the capacitor is discharged through the idealized sac. in this case, i c =i sec ? k (8) substituting eq. (1) and (8) into eq. (7) reveals: i sec = c ? di sec (9) k 2 dt the equation in terms of the output has yielded a k 2 scaling factor for c, speci?ed in the denominator of the equation. a k factor less than unity results in an effectively larger capacitance on the secondary output when expressed in terms of the input. with a k = 1/3 as shown in figure 18, c = 1 f would appear as c = 9 f when viewed from the secondary. low impedance is a key requirement for powering a high-current, low- voltage load efficiently. a switching regulation stage should have minimal impedance while simultaneously providing appropriate ?ltering for any switched current. the use of a sac between the regulation stage and the point of load provides a dual bene?t of scaling down series impedance leading back to the source and scaling up shunt capacitance or energy storage as a function of its k factor squared. however, the bene?ts are not useful if the series impedance of the sac is too high. the impedance of the sac must be low, i.e. well beyond the crossover frequency of the system. a solution for keeping the impedance of the sac low involves switching at a high frequency. this enables small magnetic components because magnetizing currents remain low. small magnetics mean small path lengths for turns. use of low loss core material at high frequencies also reduces core losses. the two main terms of power loss in the nbm? module are: n no load power dissipation (p pri_nl ): de?ned as the power used to power up the module with an enabled powertrain at no load. n resistive loss (r sec ): refers to the power loss across the nbm module modeled as pure resistive impedance. p dissipated = p pri_nl + p r sec (10) therefore, p sec_out = p pri_in Cp dissipated = p ri_in Cp pri_nl Cp r sec (11) the above relations can be combined to calculate the overall module efficiency: h = p sec_out = p pri_in Cp pri_nl Cp r sec (12) p in p in = v pri ? i pri Cp pri_nl C(i sec ) 2 ? r sec v in ? i in =1 C ( p pri_nl + (i sec ) 2 ? r sec ) v pri ? i pri c s sac k = 1/32 vin vout + ? v pri v sec c sac? k = 1/3 figure 18 ? sine amplitude converter with input capacitor s
nbm ? bus converter rev 1.1 vicorpower.com page 22 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz input and output filter design a major advantage of sac? systems versus conventional pwm converters is that the transformer based sac does not require external ?ltering to function properly. the resonant lc tank, operated at extreme high frequency, is amplitude modulated as a function of input voltage and output current and efficiently transfers charge through the non-isolated transformer. a small amount of capacitance embedded in the primary and secondary stages of the module is sufficient for full functionality and is key to achieving power density. this paradigm shift requires system design to carefully evaluate external ?lters in order to: n guarantee low source impedance: to take full advantage of the nbm? modules dynamic response, the impedance presented to its input terminals must be low from dc to approximately 5 mhz. the connection of the bus converter module to its power source should be implemented with minimal distribution inductance. if the interconnect inductance exceeds 100 nh, the input should be bypassed with a rc damper to retain low source impedance and stable operation. with an interconnect inductance of 200 nh, the rc damper may be as high as 1 f in series with 0.3 . a single electrolytic or equivalent low-q capacitor may be used in place of the series rc bypass. n further reduce input and/or output voltage ripple without sacri?cing dynamic response: given the wide bandwidth of the module, the source response is generally the limiting factor in the overall system response. anomalies in the response of the source will appear at the output of the module multiplied by its k factor. n protect the module from overvoltage transients imposed by the system that would exceed maximum ratings and induce stresses: the module primary/secondary voltage ranges shall not be exceeded. an internal overvoltage lockout function prevents operation outside of the normal operating input range. even when disabled, the powertrain is exposed to the applied voltage and power mosfets must withstand it. total load capacitance at the output of the nbm module shall not exceed the speci?ed maximum. owing to the wide bandwidth and low output impedance of the module, low-frequency bypass capacitance and signi?cant energy storage may be more densely and efficiently provided by adding capacitance at the input of the module. at frequencies <500 khz the module appears as an impedance of r sec between the source and load. within this frequency range, capacitance at the input appears as effective capacitance on the output per the relationship de?ned in eq. (13). c sec_ext = c pri_ext (13) k 2 this enables a reduction in the size and number of capacitors used in a typical system. thermal considerations the chip package provides a high degree of ?exibility in that it presents three pathways to remove heat from internal power dissipating components. heat may be removed from the top surface, the bottom surface and the leads. the extent to which these three surfaces are cooled is a key component for determining the maximum power that is available from a chip, as can be seen from figure 1. since the chip has a maximum internal temperature rating, it is necessary to estimate this internal temperature based on a real thermal solution. given that there are three pathways to remove heat from the chip, it is helpful to simplify the thermal solution into a roughly equivalent circuit where power dissipation is modeled as a current source, isothermal surface temperatures are represented as voltage sources and the thermal resistances are represented as resistors. figure 19 shows the thermal circuit for a nbm module 6123 in an application where the top, bottom, and leads are cooled. in this case, the nbm power dissipation is pd total and the three surface temperatures are represented as t case_top , t case_bottom , and t leads . this thermal system can now be very easily analyzed using a spice simulator with simple resistors, voltage sources, and a current source. the results of the simulation would provide an estimate of heat ?ow through the various pathways as well as internal temperature. alternatively, equations can be written around this circuit and analyzed algebraically: t int C pd 1 ? 1.24 = t case_top t int C pd 2 ? 1.24 = t case_bottom t int C pd 3 ? 7 = t leads pd total = pd 1 + pd 2 + pd 3 where t int represents the internal temperature and pd 1 , pd 2 , and pd 3 represent the heat ?ow through the top side, bottom side, and leads respectively. + ? + ? + ? max internal temp t case_bottom (?) t leads (?) t case_top (?) power dissipation (w) thermal resistance top thermal resistance bottom thermal resistance leads + ? + ? max internal temp t case_bottom (?) t leads (?) t case_top (?) power dissipation (w) thermal resistance top thermal resistance bottom thermal resistance leads figure 19 ? top case, bottom case and leads thermal model figure 20 ? top case and leads thermal model 1.36c / w 1.24c / w 1.36c / w 1.36c / w 1.24c / w 1.36c / w
nbm ? bus converter rev 1.1 vicorpower.com page 23 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz figure 20 shows a scenario where there is no bottom side cooling. in this case, the heat ?ow path to the bottom is left open and the equations now simplify to: t int C pd 1 ? 1.24 = t case_top t int C pd 3 ? 7 = t leads pd total = pd 1 + pd 3 figure 21 shows a scenario where there is no bottom side and leads cooling. in this case, the heat ?ow path to the bottom is left open and the equations now simplify to: t int C pd 1 ? 1.24 = t case_top pd total = pd 1 please note that vicor has a suite of online tools, including a simulator and thermal estimator which greatly simplify the task of determining whether or not a nbm? thermal con?guration is valid for a given condition. these tools can be found at: http://www.vicorpower.com/powerbench . current sharing the performance of the sac? topology is based on efficient transfer of energy through a transformer without the need of closed loop control. for this reason, the transfer characteristic can be approximated by an ideal transformer with a positive temperature coefficient series resistance. this type of characteristic is close to the impedance characteristic of a dc power distribution system both in dynamic (ac) behavior and for steady state (dc) operation. when multiple nbm modules of a given part number are connected in an array they will inherently share the load current according to the equivalent impedance divider that the system implements from the power source to the point of load. some general recommendations to achieve matched array impedances include: n dedicate common copper planes within the pcb to deliver and return the current to the modules. n provide as symmetric a pcb layout as possible among modules n an input ?lter is required for an array of nbms in order to prevent circulating currents. for further details see an:016 using bcm bus converters in high power arrays . fuse selection in order to provide ?exibility in con?guring power systems vi chip? modules are not internally fused. input line fusing of vi chip products is recommended at system level to provide thermal protection in case of catastrophic failure. the fuse shall be selected by closely matching system requirements with the following characteristics: n current rating (usually greater than maximum current of nbm module) n maximum voltage rating (usually greater than the maximum possible input voltage) n ambient temperature n nominal melting i 2 t n recommend fuse: 60 a littelfuse tls series startup and reverse operation the nbm6123t46c15a6t0r is capable of startup in forward and reverse direction once the applied voltage is greater than the undervoltage lockout threshold. the non-isolated bus converter modules are capable of reverse power operation. once the unit is enabled, energy can be transferred from secondary back to the primary whenever the secondary voltage exceeds v pri ? k. the module will continue operation in this fashion for as long as no faults occur. startup loading could be set to no greater than 20% of rated max current respectively in forward or reverse direction. a load must not be present on the +v pri pin if the powertrain is not actively switching. remove +v pri load prior to disabling the module using en pin. primary moseft body diode conduction will occur if unit stops switching while a load is present on the +v pri and +v sec voltage is two diodes drop higher than +v pri . nbm1 r 0_1 z in_eq1 z out_eq1 z out_eq2 v sec z out_eqn z in_eq2 z in_eqn r 0_2 r 0_n nbm2 nbmn load dc v pri + figure 22 ? nbm module array + ? max internal temp t case_bottom (?) t leads (?) t case_top (?) power dissipation (w) thermal resistance top thermal resistance bottom thermal resistance leads figure 21 ? top case thermal model 1.36c / w 1.24c / w 1.36c / w
nbm ? bus converter rev 1.1 vicorpower.com page 24 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz nbm? module through hole package mechanical drawing and recommended land pattern tm en vaux +v pri +v pri +v pri +v pri sgnd +v sec +v sec +v sec +v sec pgnd1 pgnd1 pgnd1 pgnd1 +v sec pgnd2 pgnd2 +v sec +v sec pgnd2 pgnd2 +v sec
nbm ? bus converter rev 1.1 vicorpower.com page 25 of 26 09/2015 800 927.9474 nbm6123x46c15a6yzz revision history revision date description page number(s) 1.0 09/08/15 initial release n/a 1.1 09/28/15 changed pri to sec input quiescent current 5
vicor?s comprehensive line of power solutions includes high density ac-dc and dc-dc modules and accessory components, fully configurable ac-dc and dc-dc power supplies, and complete custom power systems. information furnished by vicor is believed to be accurate and reliable. however, no responsibility is assumed by vicor for its use. vicor makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. vicor reserves the right to make changes to any products, specifications, and product descriptions at any time without notice. information published by vicor h as been checked and is believed to be accurate at the time it was printed; however, vicor assumes no responsibility for inaccuracies. testing and other quality controls are used to the extent vicor deems necessary to support vicor?s product warranty. except where mandated by government requirements , testing of all parameters of each product is not necessarily performed. specifications are subject to change without notice. vicor?s standard terms and conditions all sales are subject to vicor?s standard terms and conditions of sale, which are available on vicor?s webpage or upon request. product warranty in vicor?s standard terms and conditions of sale, vicor warrants that its products are free from non-conformity to its standard specifications (the ?express limited warranty?). this warranty is extended only to the original buyer for the period expiring two (2) years after t he date of shipment and is not transferable. unless otherwise expressly stated in a written sales agreement signed by a duly authorized vicor signatory, vicor disclaims all representations, liabilities, and warranties of any kind (whether arising by implication or by operation of law) with respect to the products, including, without limitation, any warranties or representations as to merchantability, fitness for particular purpose, infringement of any patent, copyright, or other intellectual property right, or any other matter. this warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. vico r shall not be liable for collateral or consequential damage. vicor disclaims any and all liability arising out of the application or use of any pro duct or circuit and assumes no liability for applications assistance or buyer product design. buyers are responsible for their products and applications us ing vicor products and components. prior to using or distributing any products that include vicor components, buyers should provide adequate design, testing and operating safeguards. vicor will repair or replace defective products in accordance with its own best judgment. for service under this warranty, the buyer must contact vicor to obtain a return material authorization (rma) number and shipping instructions. products returned without prior author ization will be returned to the buyer. the buyer will pay all charges incurred in returning the product to the factory. vicor will pay all re shipment charges if the product was defective within the terms of this warranty. life support policy vicor?s products are not authorized for use as critical components in life support devices or systems without the express prior written approval of the chief executive officer and general counsel of vicor corporation. as used herein, life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and wh ose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a s ignificant injury to the user. a critical component is any component in a life support device or system whose failure to perform can be reasonably expec ted to cause the failure of the life support device or system or to affect its safety or effectiveness. per vicor terms and conditions of sale, the user of vicor products and components in life support applications assumes all risks of such use and indemnifies vicor against all liability and damag es. intellectual property notice vicor and its subsidiaries own intellectual property (including issued u.s. and pending patent applications) relating to the pr oducts described in this data sheet. no license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is g ranted by this document. interested parties should contact vicor's intellectual property department. the products described on this data sheet are protected by the following u.s. patents numbers: 6,911,848; 6,930,893; 6,934,166; 7,145,786; 7,782,639; 8,427,269 and for use under 6,975,098 and 6,984,965. vicor corporation 25 frontage road andover, ma, usa 01810 tel: 800-735-6200 fax: 978-475-6715 email customer service: custserv@vicorpower.com technical support: apps@vicorpower.com nbm6123x46c15a6yzz nbm ? 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