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cmos 8-bit single chip microcomputer description the CXP826P16 microcomputer is composed of a cpu, rom, ram, and i/o ports. these chips feature many other high-performance circuits in a single-chip cmos design, including an a/d converter, serial interface, timer/counter, time-base timer, fluorescent display controller/driver, remote control receiver and 32khz timer/counter. this device also includes a power-on reset function and sleep/stop functions which can be used to achieve low power consumption. the CXP826P16 is the prom-incorporated version of the cxp82616 with built-in mask rom, and it is able to write directly into the program. thus, it is most suitable for evaluation use during system development and for small-quantity production. features instruction set which supports a wide array of data types ?213 types of instructions which include 16-bit calculations, multiplication and division arithmetic, and boolean bit operations. minimum instruction cycle 400ns for 10mhz, 122s for 32khz operation on-chip prom 16k bytes on-chip ram 448 bytes (including fluorescent display data area) peripheral functions ?a/d converter 8-bit, 8-channel, successive approximation system (conversion rate 32s/10mhz) ?serial interface on-chip 8-bit, 8-stage fifo (1 to 8 bytes auto transfer), 1 circuit 2-channel ?timers 8-bit timer 8-bit timer/counter 19-bit time base timer 32khz timer/counter ?fluorescent display controller/driver maximum of 336 segments display available 1 to 16 digits dynamic display dimmer function high voltage tolerance output (40v) on-chip pull-down resistor (mask option) hardware key scan function (maximum of 8 x 16 key matrix available) ?remote control receiver circuit on-chip 6-stage fifo 8-bit pulse measurement counter interrupts 13 factors, 13 vectors, multi-interruption possible standby mode sleep/stop package 80-pin plastic qfp structure silicon gate cmos ic ?1 e94413b1y-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP826P16 80 pin qfp (plastic)
a/d converter fdp controller/ driver remocon serial interface unit 8 bit timer/counter 0 fifo fifo interrupt controller spc700 cpu core prom 16k bytes prescaler/ time base timer 32khz timer/counter ram 448 bytes 8 pa0/an0 to pa7/an7 t0 to t7 pe4/rmc pb1/cs0 pb3/si0 pb4/so0 pb2/sck0 pb6/si1 pb7/so1 pb5/sck1 pe0/ec pe0/int0 pe1/int1 pe2/int2 pe3/int3 port c 8 pc0 to pc7 port f 8 pf0 to pf7 port b 8 pb0 to pb7 port e 6 2 pe0 to pe5 pe6 to pe7 8 8 21 t8/s28 to t15/s21 s0 to s20 v fdp 8 bit timer 1 ram 80 bytes port a 8 pa0 to pa7 pb0/cs1 2 pe7/adj pe7/to 2 pe3/nmi 2 8 pd0 to pd7 port d 2 ph0 to ph1 port h 2 ph2 to ph3 ph2/tex ph3/tx extal xtal v dd vss rst vpp clock gen./ system control 2 CXP826P16 block diagram
pe3/int3/nmi pe4/rmc pe5 pe6 pe7/to/adj pb0/cs1 pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pc0/kr0 pc1/kr1 pc2/kr2 pc3/kr3 pc4/kr4 pc5/kr5 pc6/kr6 pc7/kr7 pa0/an0 pa1/an1 pa2/an2 t6 t7 t8/s28 t9/s27 t10/s26 t11/s25 t12/s24 t13/s23 t14/s22 t15/s21 s20 s19 s18 s17 s16 pf7/s15 pf6/s14 pf5/s13 pf4/s12 pf3/s11 pf2/s10 pf1/s9 pf0/s8 pd7/s7 pa3/an3 pa4/an4 pa5/an5 pa6/an6 pa7/an7 rst extal xtal vss pd0/s0 pd1/s1 pd2/s2 pd3/s3 pd4/s4 pd5/s5 pd6/s6 pe2/int2 pe1/int1 pe0/ec/int0 ph0 ph1 vpp ph2/tex ph3/tx v dd v fdp t0 t1 t2 t3 t4 t5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 1 3 CXP826P16 pin assignment (top view) note) 1. vpp (pin 75) is always connected to v dd . 2. ph3/tx (pin 73) is input port during port selection; oscillation output during oscillation selection
4 CXP826P16 pin description symbol i/o functions i/o/analog input pa0/an0 to pa7/an7 (port a) 8-bit i/o port. i/o can be set in a bit unit. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) analog inputs to a/d converter. (8 pins) i/o/input pc0/kr0 to pc7/kr7 pe0/int0/ ec0 pe1/int1 pe2/int2 pe3/int3/ nmi pe4/rmc pe5 pe6 pe7/to/ adj input/input/ input input/input input/input input/input/ input input/input input input output/output (port c) 8-bit i/o port. i/o can be set in a bit unit. capable of driving 12ma sync current. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (port e) 8-bit port. upper 6 bits are for inputs; lower 2 bits are for outputs. (8 pins) key return input for fdp segment signal which performs key scanning. external event input to timer/counter. (1 pin) external interrupt request inputs. (4 pins) non-maskable interruption request input. input for remote control receiver circuit. output for timer/counter rectangular waveform and 32khz oscillation frequency division. i/o/input i/o/input i/o/i/o i/o/input i/o/output i/o/i/o i/o/input i/o/output pb0/cs1 pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 (port b) 8-bit i/o port. i/o can be set in a bit unit. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) chip select input for serial interface (ch1). chip select input for serial interface (ch0). serial clock i/o (ch0). serial data input (ch0). serial data output (ch0). serial clock i/o (ch1). serial data input (ch1). serial data output (ch1).
5 CXP826P16 symbol i/o functions i/o ph0 to ph1 (port h) 2-bit i/o port. i/o can be set in a bit unit. incorporation of pull-up resistor can be set through the software in a unit of 2 bits. (2 pins) output/output t8/s28 to t15/s21 output for fdp timing and segment signals. output/output pf0/s8 to pf7/s15 (port f) 8-bit output port. (8 pins) output s16 to s20 segment signal output for fdp. output t0 to t7 timing signal output for fdp. output/output pd0/s0 to pd7/s7 input crystal connectors for system clock oscillation. when the clock is supplied externally, input to extal; opposite phase clock should be input to xtal. extal provides voltage for fdp when on-chip resistor is selected under mask option. v fdp output xtal input/input crystal connectors for 32khz timer/counter clock oscillation circuit. connect a 32khz crystal oscillator between tex and tx. for usage as event input, connect clock oscillation source to tex, and leave tx open. ph2/tex input/output ph3/tx input low-level active. system reset. rst is input pin. rst positive power supply pin for writing of built-in prom. under normal operating conditions, connect to v dd . vpp vcc supply. v dd gnd vss (port d) 8-bit output port. (8 pins) (port h) 2-bit input port. (2 pins) segment signal output for fdp. segment signal output for fdp.
6 CXP826P16 port b data bus rd (port b) aaaa aa port b direction ip aa aa aaaa aaaa port b data "0" when reset "0" when reset ? schmitt input cs0 cs1 si0 si1 ? pull-up transistors approx. 100k ? aaaa pull-up resistor si0 and si1 are not schmitt input. 8 pins hi-z hi-z when reset pa0/an0 to pa7/an7 pb0/cs1 pb1/cs0 pb3/si0 pb6/si1 port b data bus rd (port b) aa ip aa aa aaaa port b output selection "0" when reset ? schmitt input sck in aaaa aaaa port b data aaaa aaaa port b direction "0" when reset "0" when reset sck out output enable ? pull-up transistors approx. 100k ? aaaa aaaa pull-up resistor 4 pins 2 pins hi-z pb2/sck0 pb5/sck1 data bus rd (port a) aaaa aa port a direction ip aa aa aaaa aaaa port a data aaaa pull-up resistor aaaa port a input selection input protection circuit "0" when reset "0" when reset "0" when reset input multiplexer a/d converter ? pull-up transistors approx. 100k ? ? i/o circuit format for pins port a pin circuit format
7 CXP826P16 2 pins hi-z hi-z pin when reset circuit format pb4/so0 pb7/so1 pc0/kr0 to pc7/kr7 8 pins 5 pins 1 pin hi-z high level hi-z pe0/ec/int0 pe1/int1 pe2/int2 pe3/int3/nmi pe4/rmc a ip aa aa schmitt input rd (port e) data bus ec/int0 int1 int2 int3/nmi rmc data bus rd (port c) aaa aaa aa aa port c direction ip aa aaa port c data "0" when reset "0" when reset ? 2 ? 1 ? 2 pull-up transistors approx. 100k ? ? 1 large current drive of 12ma possible aaa aaa pull-up resistor key input signal data bus rd (port b) aa aa ip aa aaaa aaaa port b output selection "0" when reset ? aaaa port b data aaaa port b direction "0" when reset so output enable ? pull-up transistors approx. 100k ? aaaa aaaa pull-up resistor "0" when reset port e pe5 1 pin pe6 a ip aa aa rd (port e) data bus port e data bus rd (port e) * aaaa aaaa port e data "1" when reset aa aa port e port c port b
8 CXP826P16 1 pin pe7/to/adj data bus aa aaa aaa port e output selection "0" when reset aaa aaa port e data "1" when reset rd (port e) ? adj signals are frequency division outputs for 32khz oscillation frequency adjustment. adj2k provides usage as buzzer output. aaa port e output selection "00" when reset aaa aaa port e output selection aa aa output enable to adj16k adj2k mpx port e 2 pins hi-z ph0 to ph1 data bus rd aa aa ip aa aaaa port data "0" when reset ? aaaa aaaa port direction "0" when reset ? pull-up transistors approx. 100k ? aaaa aaaa pull-up resistor port h 16 pins hi-z or low level (when pd resistor is connected) pd0/s0 to pd7/s7 pf0/s8 to pf7/s15 data bus rd (port d or port f) a aaaa aaaa port d data or port f data ("0" when reset) ? segment output data output selection control signal op a a mask option pull-down resistor v fdp ? high voltage tolerance transistor port d port f high level high level with 150k ? resistor when reset () when reset pin circuit format
9 CXP826P16 21 pins hi-z or low level (when pd resistor is connected) s16 to s20 t15/s21 to t8/s28 t0 to t7 aa aa ? segment output data output selection control signal ("0" when reset) op aa aa mask option pull-down resistor v fdp ? high voltage tolerance transistor 2 pins oscillation extal xtal aa aa a a ip aa aa extal xtal diagram shows circuit construction for oscillation. during stop feedback resistor is disconnected, and xtal becomes "h" level. aa aa ip 2 pins oscillation halted port input ph2/tex ph3/tx aa aa aa aa ip aa aa ph2/tex ph3/tx a a ip 32khz oscillation circuit control "1" when reset data bus rd data bus rd clock input 1 pin low level rst aa aa schmitt input pull-up resistor mask option op aa ip when reset pin circuit format
10 CXP826P16 ? 1 v in and v out must not exceed v dd + 0.3v. ? 2 specifies output current of general-purpose i/o ports. ? 3 the large current drive transistor is an n-ch transistor of port c (pc). note) if the absolute maximum ratings are exceeded, the lsi could reach permanent breakdown. also, observing recommended operating conditions is desirable; otherwise, the lsi's reliability could be affected. supply voltage input voltage output voltage v dd vpp v in v out v od i oh i odh1 i odh2 i oh i odh i ol i olc i ol topr tstg p d v dd 40 to v dd + 0.3 5 15 35 40 100 15 20 100 10 to +75 55 to +150 600 display output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation 0.3 to +7.0 0.3 to +13.0 0.3 to +7.0 ? 1 0.3 to +7.0 ? 1 v v v v v ma ma ma ma ma ma ma ma c c mw other than display output pins ? 2 : per pin display output s0 to s20: per pin display output t0 to t7 , t8/s28 to t15/s21: per pin total of other than display output pins total of display output pins port 1 pin large current port pin ? 3 entire pin toral as p channel transistor is open drain, v dd voltage is determined as standard. item symbol rating unit remarks absolute maximum ratings (vss = 0v) incorporated prom
11 CXP826P16 high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v v v v v c item symbol min. max. unit remarks 4.5 3.5 2.7 2.5 0.7v dd 0.8v dd v dd 0.4 0 0 0.3 10 v ih v ihs v ihex v il v ils v ilex topr high speed mode (1/2, 1/4 clock) guaranteed operation range low speed mode (1/16 clock) guaranteed operation range guaranteed operation range with tex clock guaranteed data hold operation range during stop ? 4 ? 1 hysteresis input ? 2 extal pin ? 3 ? 1 hysteresis input ? 2 extal pin ? 3 v dd ? 1 all regular input port (pa, pb3, pb4, pb6, pb7, pc, pe5, ph). ? 2 for pins rst, cs0, cs1, sck0, sck1, ec/int0, int1, int2, int3/nmi, rmc. ? 3 specifies only for external clock input. ? 4 vpp should be the same voltage as v dd . recommended operating conditions (vss = 0v) vpp vpp = v dd
12 CXP826P16 v dd = 4.5v, i oh = 0.5ma v dd = 4.5v, i oh = 1.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 0.4v v dd = 4.5v, v il = 4.0v v dd = 4.5v v oh = v dd 2.5v v dd = 5.5v v ol = v dd 35v v fdp = v dd 35v v dd = 5v v od v fdp = 30v v dd = 5.5v v i = 0, 5.5v high level output voltage display output current open drain output leak current (p-ch tr off state) pull down resistor ? 3 input/output leak current 4.0 3.5 0.5 0.5 0.1 0.1 1.5 3.3 8 20 60 v v v v v a a a a a a a ma ma a k ? a pc pa, pb, pc, pe6, pe7, ph0, ph1 extal tex rst ? 1 pa to pc ? 2 ph0 ? 2 , ph1 ? 2 item symbol pin condition min. pa to pc ? 2 , ph0 ? 2 , ph1 ? 2 , rst ? 2 s0 to s20 s21/t15 to s28/t8 t0 to t7 i iz i il i oh i lol r l v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current 100 typ. 0.4 0.6 1.5 40 40 10 10 400 50 20 270 10 max. unit dc characteristics electrical characteristics (ta = 10 to +75 c, vss = 0v) s0 to s20 s21/t15 to s28/t8 t0 to t7 s21/t15 to s28/t8 t0 to t7 s0 to s20
13 CXP826P16 supply current ? 4 item symbol pin codition min. 20 400 9 1000 30 a a 40 ma ma a 1.2 8 30 for pins other than s0 to s28, t0 to t7, pe6, pe7, v dd , vss, v fdp 1mhz clock 0v other than the measured pins v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) high-speed mode operation (1/2 frequency divider clock) v dd i dd1 i dd2 i dds1 i dds2 i dds3 c in typ. max. unit ? 1 rst specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. ? 2 pins pa to pc, ph0, and ph1 specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. ? 3 applies when the on-chip pull-down resistor is selected under the mask option. ? 4 all output pins are left open. v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) sleep mode stop mode, v dd = 5.5v, termination of 10mhz and 32khz crystal oscillation. input capacitance pf 20 10
14 CXP826P16 ? t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control registor (address: 00fe h ). t sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") extal t xh t xl t cf t cr 0.4v v dd 0.4v 1/fc aaaa aaaa aaaa aaaa crystal oscillation ceramic oscillation extal xtal external clock extal xtal 74hc04 c 1 c 2 aaaa aaaa 32khz clock applied condition crystal oscillation tex tx c 1 c 2 ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise and fall time event count input clock pulse width event count input clock rise and fall time system clock frequency event count input clock input pulse width event count input clock rise and fall time f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal extal extal ec ec tex tx tex tex mhz ns ns ns ms khz s ms item symbol pins conditions min. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock application condition) fig. 3 fig. 3 1 37.5 t sys + 50 ? 10 typ. 32.768 max. 10 200 20 20 (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) fig. 2. clock applied conditions fig. 1. clock timing tex ec t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr fig. 3. event count clock timing
15 CXP826P16 (2) serial transfer (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item cs0 sck0 (cs1 sck1) delay time cs0 sck0 (cs1 sck1) float delay time cs0 so0 (cs1 so1) delay time cs0 so0 (cs1 so1) float delay time cs0 (cs1) high level width sck0 (sck1) cycle time sck0 (sck1) high and low level widths si0 (si1) input setup time (for sck0 (sck1 ) ) si0 (si1) input hold time (for sck0 (sck1 ) ) sck0 so0 (sck1 so1) delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 (sck1) sck0 (sck1) so0 (so1) so0 (so1) cs0 (cs1) sck0 (sck1) sck0 (sck1) si0 (si1) si0 (si1) so0 (so1) input mode output mode input mode output mode sck0 (sck1) input mode sck0 (sck1) output mode sck0 (sck1) input mode sck0 (sck1) output mode sck0 (sck1) input mode sck0 (sck1) output mode ns ns ns ns ns symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc 50 100 200 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns t sys + 200 100 max. unit chip select transfer mode (sck0 (sck1) = output mode) chip select transfer mode (sck0 (sck1) = output mode) chip select transfer mode chip select transfer mode chip select transfer mode condition note 1) t sys indicates the three values below according to the upper two bits (cpu clock selection) of the control clock registor (address: 00fe h ). t sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") note 2) the load condition for the sck0 (sck1) output mode, so0 (so1) output delay time is 50pf + 1ttl.
16 CXP826P16 fig. 4. serial transfer ch0 timing cs0 (cs1) sck0 (sck1) 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 (si1) t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0 (so1)
17 CXP826P16 t conv t samp v ian v zt ? 1 v ft ? 2 ta = 25 c v dd = 5.0v v ss = 0v s s v v dd + 0.3 an0 to an7 160/f adc ? 3 12/f adc ? 3 0.3 item symbol pin condition min. typ. max. unit bits (3) a/d converter characteristics (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) 8 3 lsb 70 mv 5030 10 4970 10 4910 mv analog input linearity error v ft v zt 00 h 01 h fe h ff h digital conversion value ? 1 v zt : value at which the digital conversion value changes from 00 h to 01 h and vice versa. ? 2 v ft : value at which the digital conversion value changes from fe h to ff h and vice versa. ? 3 f adc indicates the below values due to the bit6 (cks) of a/d control register (address: 00f9 h ) and the bit7 (pck1) and bit6 (pck0) of clock control register (address: 00fe h ) 00 ( = f ex /2) 01 ( = f ex /4) 11 ( = f ex /16) f adc = f c /2 f adc = f c /4 f adc = f c /16 f adc = f c cks pck1, 0 0 ( /2 selection) 1 ( selection) f adc = f c /2 f adc = f c /8 conversion time sampling time analog input voltage linearity error zero transition voltage full-scale transition voltage resolution fig. 5. definition of a/d converter terms
18 CXP826P16 external interruption high and low level widths reset input low level width int0 int1 int2 int3 nmi rst 1 32/fc s s item symbol pin condition min. max. unit t ih t il t rsl (4) interruption, reset input (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) 0.2v dd 0.8v dd t ih t il int0 int1 int2 int3 nmi (nmi specifies only for the falling edge) t il t ih fig 6. interruption input timing t rsl 0.2v dd rst fig. 7. rst input timing
19 CXP826P16 appendix fig. 8. recommended oscillation circuit c 1 aaaa a aa a aaaa extal xtal c 2 rd aaaa a aa a aaaa extal xtal rd (i) main clock aaaa a aa a aaaa extal xtal c 1 c 2 rd xtal (ii) main clock aaaa a aa a aaaa extal xtal c 1 c 2 rd aaaa a aa a aaaa tex tx (iii) sub clock manufacturer murata mfg co., ltd. river eletec corporation kinseki ltd. model csa4.19mg csa8.00mtz cst4.19mgw ? cst8.00mtw ? hc-49/u03 hc-49/u (-s) p3 fc (mhz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 20 20 50 22 1m (iii) 32.768khz 30 12 27 30 12 27 0 0 0 c 1 (pf) c 2 (pf) rd ( ? ) circuit example (i) csa10.0mtz (ii) cst10.0mtw ? (i) those marked with an asterisk ( ? ) signify types with built-in ground capacitance (c 1 , c 2 ). option item mask product package rom capacitance reset pin pull-up resistor high voltage drive output pin pull-down resistor 80-pin plastic qfp 12kbyte/16kbyte existent/non-existent existent/non-existent 80-pin plastic qfp prom 16kbyte existent non-existent (pd0/s0 to pf7/s15) existent (t0 to s16) selection guide CXP826P16q-1-
20 CXP826P16 0 15 10 5 51015 20 (100a) 3 45 6 0.1 5.0 1.0 7 2 0.05 (50a) 0.01 (10a) 0.5 10.0 20.0 v dd supply voltage [v] i dd supply current [ma] i dd vs. v dd (fc = 10mhz, ta = 25 c, typical) fc system clock [mhz] i dd supply current [ma] i dd vs. fc (v dd = 5v, ta = 25 c, typical) 32khz sleep mode sleep mode 32khz mode (instruction) 1/16 dividing mode 1/2 dividing mode 1/16 dividing mode sleep mode 1/2 dividing mode 0 charactreistics curves
21 CXP826P16 package outline unit : mm package structure sony code eiaj code jedec code qfp-80p-l01 qfp080-p-1420 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 1.6g 23.9 0.4 20.0 ?0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 ?0.1 + 0.15 14.0 ?0.1 + 0.4 17.9 0.4 16.3 0.1 ?0.05 + 0.2 2.75 ?0.15 + 0.35 0.8 0.2 0.15 ?0.05 + 0.1 80pin qfp (plastic) m 0.2 0.15 0? to 10? detail a a package structure sony code eiaj code jedec code qfp-80p-l01 qfp080-p-1420 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 1.6g 23.9 0.4 20.0 0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 0.1 + 0.15 14.0 0.1 + 0.4 17.9 0.4 16.3 0.1 0.05 + 0.2 2.75 0.15 + 0.35 0.8 0.2 0.15 0.05 + 0.1 80pin qfp (plastic) m 0.2 0.15 0 ? to 10 ? detail a a lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. sony corporation

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