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this is information on a product in full production. may 2013 docid023624 rev 1 1/13 13 STFI5N95K3 n-channel 950 v, 3 typ., 4 a zener-protected supermesh3? power mosfet in i 2 pakfp package datasheet ? production data figure 1. internal schematic diagram features ? fully insulated and low profile package with increased creepage path from pin to heatsink plate ? 100% avalanche tested ? extremely large avalanche performance ? gate charge minimized ? very low intrinsic capacitances ? zener-protected applications ? switching applications description this supermesh3? power mosfet is the result of improvements applied to stmicroelectronics? supermesh? technology, combined with a new optimized vertical structure. this device boasts an extremely low on- resistance, superior dynamic performance and high avalanche capability, rendering it suitable for the most demanding applications. ' * 6 am01476v1 1 2 3 i 2 pakfp (to-281) order code v ds r ds(on) max i d p tot STFI5N95K3 950 v 3.5 4 a 25 w table 1. device summary order code marking package packaging STFI5N95K3 5n95k3 i 2 pakfp (to-281) tube www.st.com
contents STFI5N95K3 2/13 docid023624 rev 1 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 docid023624 rev 1 3/13 STFI5N95K3 electrical ratings 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v gs gate- source voltage 30 v i d drain current (continuous) at t c = 25 c 4 (1) 1. limited by maximum junction temperature a i d drain current (continuous) at t c = 100 c 3 (1) a i dm (2) 2. pulse width limited by safe operating area drain current (pulsed) 16 (1) a p tot total dissipation at t c = 25 c 25 w i ar avalanche current, repetitive or not- repetitive (pulse width limited by t j max) 4a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 100 mj dv/dt (3) 3. i sd 4 a, di/dt 100 a/s, peak v ds v (br)dss peak diode recovery voltage slope 5 v/ns v iso insulation withstand voltage (rms) from all three leads to external heat sink (t = 1 s,t c = 25 c) 2500 v t j t stg operating junction temperature storage temperature -55 to 150 c table 3. thermal data symbol parameter value unit r thj-case thermal resistance junction-case max 5 c/w r thj-amb thermal resistance junction-ambient max 62.5 c/w electrical characteristics STFI5N95K3 4/13 docid023624 rev 1 2 electrical characteristics (tcase =25 c unless otherwise specified) table 4. on /off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 1 ma, v gs = 0 950 v i dss zero gate voltage drain current (v gs = 0) v ds = 950 v v ds = 950 v, t c =125 c 1 50 a a i gss gate-body leakage current (v ds = 0) v gs = 20 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 100 a 3 4 5 v r ds(on) static drain-source on- resistance v gs = 10 v, i d = 2 a 3 3.5 table 5. dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 25 v, f = 1 mhz, v gs = 0 - 460 - pf c oss output capacitance - 38 - pf c rss reverse transfer capacitance -1-pf c o(tr) (1) 1. time related is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss equivalent capacitance time related v ds = 0 to 760 v, v gs = 0 - 970 - pf c o(er) (2) 2. energy related is defined as a constant equival ent capacitance giving the same stored energy as c oss when v ds increases from 0 to 80% v dss equivalent capacitance energy related v ds = 0 to 760 v, v gs = 0 - 15 - pf r g gate input resistance f=1 mhz open drain - 5.5 - q g total gate charge v dd = 760 v, i d = 4 a, v gs = 10 v (see figure 16) -19-nc q gs gate-source charge - 4.7 - nc q gd gate-drain charge - 12 - nc docid023624 rev 1 5/13 STFI5N95K3 electrical characteristics the built-in back-to-back zener diodes have specifically been designed to enhance not only the device?s esd capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. in this respect the zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device?s integrity. these integrated zener diodes thus avoid the usage of external components. table 6. switching times symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time v dd = 475 v, i d = 2 a, r g = 4.7 , v gs = 10 v (see figure 15) -17 -ns t r rise time - 7 - ns t d(off) turn-off delay time - 32 - ns t f fall time - 18 - ns table 7. source drain diode symbol parameter test conditions min. typ. max. unit i sd source-drain current - 4 a i sdm (1) 1. pulse width limited by safe operating area source-drain current (pulsed) - 16 a v sd (2) 2. pulsed: pulse duration = 300 s, duty cycle 1.5% forward on voltage i sd = 4 a, v gs = 0 - 1.6 v t rr reverse recovery time i sd = 4 a, di/dt = 100 a/s v dd = 60 v (see figure 17) -410 ns q rr reverse recovery charge - 3.5 c i rrm reverse recovery current - 17 a t rr reverse recovery time i sd = 4 a, di/dt = 100 a/s v dd = 60 v t j = 150 c (see figure 17) -516 ns q rr reverse recovery charge - 4.1 c i rrm reverse recovery current - 16 a table 8. gate-source zener diode symbol parameter test conditions min. typ. max. unit v (br)gso gate-source breakdown voltage i gs = 1 ma, i d =0 30 - - v electrical characteristics STFI5N95K3 6/13 docid023624 rev 1 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance , ' 9 ' 6 9 $ 2 s h u d w l r q l q w k l v d u h d l v / l p l w h g e \ p d [ 5 ' 6 r q ? v ? v p v p v 7 m ? & 7 f ? & 6 l q o j h s x o v h $ 0 y figure 4. output characteristics figure 5. transfer characteristics figure 6. gate charge vs gate-source voltage figure 7. static drain-source on-resistance , ' 9 ' 6 9 $ 9 9 9 * 6 9 $ 0 y , ' 9 * 6 9 $ 9 ' 6 9 $ 0 y 9 * 6 4 j q & |