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| november 2013 doc id 023670 rev 1 1/24 UM1575 user manual spice model tutorial for power mosfets introduction this document describes st?s spice model versions available for power mosfets. this is a guide designed to support user choosing the best model for his goals. in fact, it explains the features of different model versions both in terms of static and dynamic characteristics and simulation performance, in order to find the right compromise between the computation time and accuracy. for example, the self-heating model (v3 version), which accurately reproduces the thermal response of all electrical parameters, requires a considerable simulation effort. finally, an example shows how the self-heating model works. spice models describe the characteristics of typical devices and don't guarantee the absolute representation of product specifications and operating characteristics; the datasheet is the only document providing product specifications. although simulation is a very important tool to evaluate the device?s performance, the exact device?s behavior in all situations is not predictable, therefore the final laboratory test is necessary. www.st.com
spice model versions UM1575 2/24 doc id 023670 rev 1 1 spice model versions st provides 6 model versions on each part number: ? partnumber_v1c ? partnumber_v1t ? partnumber_v2 ? partnumber_v3 ? partnumber_v4 ? partnumber_tn v1c version it is the basic model (level =3) enclosing c oss and c rss modeling through capacitance profile tables. it is an empirical model, and it assumes a 27 c constant temperature. v1t version it comes directly from v1c version and it also includes the package thermal modeling through a thermal equivalent network and presents two additional external thermal nodes t j and t case . this version hasn't the dynamic link between power mosfet temperature and internal parameters. v2 version it is more advanced than v1c, in fact it takes into account the temperature dependence and capacitance profiles too. it allows the static and dynamic behavior to be reproduced by user at fixed temperatures. by using this version, the simulation of self-heating effects isn't possible. v3 version it comes directly from v2 version and includes the package thermal model through a thermal equivalent network and presents two additional external thermal nodes: t j and t case . in this version, during each transient, the current power dissipation is calculated and a current proportional to this power is fed into the thermal network. in this way, the voltage at t j node contains all the information about the junction temperature, which changes internal device?s parameters. since it is a monitoring node, usually t j pin is not connected (however, to avoid warning messages on this node, the user has to add a floating wire - see figure 1 ). on contrary, t case node has to be connected, either to a constant voltage source vdc representing the ambient temperature or to a heat sink modeled by its own thermal network ( figure 1 ). v4 version it comes directly from v3 version considering the device sited in free air. it includes the package thermal modeling through a thermal equivalent network and presents three additional external thermal nodes: t j , t case and t amb . the voltage at t j node and t case node contains all the information about the junction temperature and case temperature which change internal device?s parameters. since they are monitoring nodes, usually t j and t case pins are not connected (however, to avoid warning messages on this node, the user has to add a floating wire - see figure 1 ). conversely, t amb node has to be connected: to a constant voltage source vdc, representing the ambient temperature. doc id 023670 rev 1 3/24 UM1575 spice model versions 24 tn version it includes the rc thermal network only, which represents the thermal model of the package. its symbol has two pins: t j and t case . figure 1. self-heating model (v3 version) note: t j is a monitoring node and it is not connected; t case is connected either by using a vdc, representing the ambient temperature (on the left-side), or by heat-sink thermal network (on the right-side). c1 r2 r1 tcase d s g tj zth 25 tcase d s g tj zth 25 c2 0 0 tamb tamb gipd081020130954fsr spice model symbol UM1575 4/24 doc id 023670 rev 1 2 spice model symbol for each model version, st provides the appropriate symbol as shown below: figure 2. model symbols tj tcase tcase d s g tj zth tamb tj 1 tcase 2 tcase d s g tj zth v1c version v2 version v1t version v3 version v4 version tn version gipd081020131007fsr doc id 023670 rev 1 5/24 UM1575 spice models - instructions to simulate 24 3 spice models - instructions to simulate in spice simulator, user has to upload the device symbol (.olb file) and the spice model (.lib file) to simulate transistors in the schematic. 3.1 installation in the package model, there are the following files: ? name.lib text file representing the model library written as a spice code; ? name.olb symbol file to use the model into orcad capture user interface. in capture open the menu dialog window "pspice" "edit simulation profile". go to "configuration files" tab and "library" category. select the library (*.lib) path by "browse?" button and click to "add to design" (see figure 3 ) figure 3. capture dialog window to select the library (*.lib) to include the symbol *.olb in the schematic view, open the menu dialog window "place" "part" (or simply pressing "p" key in keyboard) and click the "add library?" button (or pressing alt+"a") to select the file (see figure below). gipd081020131721fsr spice models - instructions to simulate UM1575 6/24 doc id 023670 rev 1 figure 4. capture dialog window to include the symbol (*.olb) finally, you can simulate your circuit choosing the simulation type and parameters. 3.2 typical simulation parameters / options as our models contain many non-linear elements, the standard simulation parameters are often not suitable. the following values can facilitate convergence (set them in dialog window "pspice" "edit simulation profile" "options" tab): note: if the following error message appears during the simulation of one of device models: ==> internal error -- overflow in device..... <== you have to edit the 'pspice.ini' file by inserting the following line behind the headline [pspice] as follows: [pspice] mathexceptions = off ...... do not change any other lines already present gipd081020131724fsr abstol= 1na (best accuracy of currents) chgtol= 1 pc..10 pc (best accuracy of charges) itl1= 150 (dc and bias 'blind' iteration limit) itl2= 20...150 (dc and bias 'best guess' iteration limit) itl4= 20...150 (transient time point iteration limit) reltol= 0.001...0.01 (relative accuracy of voltages and currents) doc id 023670 rev 1 7/24 UM1575 a brief description of self-heating model (v3 version) 24 4 a brief description of sel f-heating model (v3 version) power mosfet?s spice models are behavioral and achieved by fitting simulated data with static and dynamic characterization results. the behavioral model is the best approach because it reproduces the electrical and thermal behavior of the power device through a simplified physical description of the device consisting in a set of equations ruling its behavior at terminal level. the self-heating model (v3 version) includes different analog behavioral models (abm) to describe resistors, voltage and current generator, which are temperature-dependent. a curve fit optimization algorithm extracts the mathematical expression for abm, which yields a good representation of power mosfet?s static and dynamic characteristics. in figure 5 , the self-heating spice model (v3 version) schematic is shown. a brief description of self-heating model (v3 version) UM1575 8/24 doc id 023670 rev 1 figure 5. power mosfet self-heating model schematic rtj6 v_sense3 0vdc g_power in- out+ out- in+ g_rs in- out+ out- in+ rdd11 rtj14 e22 in+ in- out+ out- r_g3 1 1 2 2 g63 g_rmos in- out+ out- in+ rg6 ecap (table) in+ in- out+ out- rdd9 e_e001 in+ in- out+ out- gcdg2 in- out+ out- in+ vread2 0vdc gcdg in- out+ out- in+ 1 2 g_bvdss in- out+ out- in+ g59 g_r_did in- out+ out- in+ rtj15 e_e001 in+ in- out+ out- e2 in+ in- out+ out- rdd10 g60 g_r_did in- out+ out- in+ rtj13 1 1 2 2 g_rmos in- out+ out- in+ rtj16 ecap2 (table) in+ in- out+ out- 0 0 0 0 gate drain source 0 0 0 0 tj 0 0 tc a s e cj6 cref 40 d1x d1y 50 g 3 v2 d1z d1 dd ss r_rmos r_ds sx d d1bvdss1 r_cgs rx1 cgs cref2 402 502 v22 alfa2 rcap2 r_gdiode rd alfa rls rcap ls lg r_gbdss 2g2 ld s r_edep rld 1 d1k r_gpower edep c_cds cj5 cj4 cj3 aa r_r001 ba cj2 r_r003 c cj1 d d_dedep t1 t2 t3 t4 gipd081020131034fsr c rss modeling c rss modeling dc modelling dc diode modeling c oss modeling c oss modelling bvdss modelling recovery diode modelling thermal impedance modeling doc id 023670 rev 1 9/24 UM1575 a brief description of self-heating model (v3 version) 24 4.1 thermal network thermal impedance network represents the basic element, which is featured inside the macro-model. it is used to transform the power dissipated inside the junction into a voltage representing the temperature (t j ). figure 6. physical structure the voltage drop across the network is detected and used as emitter value inside behavioral equations used to model other parameters. thermal impedance is the experimental data required to obtain the cauer model (see figure 6 ). figure 7. thermal impedance profile and cauer model ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * , 3 ' ) 6 5 * , 3 ' ) 6 5 5 7 m * b s r z h u , 1 2 8 7 2 8 7 , 1 5 7 m 5 7 m 5 7 m 5 7 m 7 m 7 f d v h & m 5 b * s r z h u & m & m & m & m & m 7 7 7 7 ( ( ( ( ( ( ( ( . w l p h v 6 l p x o d w l r q ( [ s h u l p h q w d o a brief description of self-heating model (v3 version) UM1575 10/24 doc id 023670 rev 1 4.2 experimental data used to fit the model the model implementation requires the following experimental data: ? typ. output characteristics at different temperatures ? typ. transfer characteristics at different temperatures ? typ. drain source breakdown voltage at different temperatures ? typ. drain source on state resistance vs temperature ? typ. gate threshold voltage vs temperature ? typ. forward diode characteristics ? typ. capacitances profile vs vds ? typ. gate charge ? typ. switching on resistive load ? typ. switching on inductive load ? typ. free-wheeling diode characteristics ? unclamped inductive switching ? switching losses vs gate resistance ? equivalent capacitance time related (c o(tr) ) ? equivalent capacitance energy related (c o(er) ) ? max. transient thermal impedance figure 8. simulated and measured output characteristics figure 9. simulated curves at v gs = 10 v * , 3 ' ) 6 5 , ' $ 9 ' 6 9 v l p x o d w h g p h d v x u h g * , 3 ' ) 6 5 , ' $ 9 ' 6 9 5 ' 6 r q # ? & 5 ' 6 r q # ? & 5 ' 6 r q # ? & doc id 023670 rev 1 11/24 UM1575 a brief description of self-heating model (v3 version) 24 4.3 c oss and c rss model charge and current formulas for a linear capacitor are: for a non linear (voltage-dependent) time-independent capacitor these formulas become: the c(v) function is obtained by lookup table. figure 12. capacitance profiles figure 10. normalized r ds(on) vs temperature figure 11. normalized gate threshold voltage vs temperature r ds(on) 1.9 1.3 0.9 0.5 -50 0 t j (c) (norm) -25 75 25 50 100 0.7 1.1 1.5 1.7 2.1 am06484v1 i d =2.5a v gs(th) 1.00 0.90 0.80 0.70 -50 0 t j (c) (norm) -25 1.10 75 25 50 100 i d =250a am06483v1 qcv ? = it () c dv dt ------- ? = qcv () v d ? = it () cv () dv dt ------- ? = c 1000 100 10 1 0.1 10 v ds (v) (pf) 1 100 ciss coss crss am06481v1 a brief description of self-heating model (v3 version) UM1575 12/24 doc id 023670 rev 1 4.4 example of dynamic characteristics 4.4.1 gate charge figure 13. gate charge - schematic figure 14. gate charge - simulated waveforms ipulse1 vdd1 rload1 r127 0 0 0 0 gipd251020131424fsr * , 3 ' ) 6 5 9 ' 6 9 9 * 6 9 , ' $ 9 ' 6 9 , ' $ 4 * q & doc id 023670 rev 1 13/24 UM1575 a brief description of self-heating model (v3 version) 24 figure 15. gate charge - experimental waveforms 4.4.2 switching on inductive load figure 16. switching on inductive load - schematic gipd251020131457fsr iload1 vdd1 rgate1 vpulse1 r127 l33 lpar1 0 gipd251020131432fsr a brief description of self-heating model (v3 version) UM1575 14/24 doc id 023670 rev 1 figure 17. switching on inductive load - simulated waveforms figure 18. switching on inductive load - experimental waveforms * , 3 ' ) 6 5 ( ( ( ( ( ( 9 ' 6 9 , ' $ w l p h v gipd251020131502fsr doc id 023670 rev 1 15/24 UM1575 a brief description of self-heating model (v3 version) 24 4.4.3 e off vs r gate figure 19. e off vs r gate - schematic figure 20. e off vs r gate - experimental waveforms iload1 vdd1 rgate1 vpulse1 r127 l33 lpar1 0 gipd251020131432fsr gipd251020131506fsr a brief description of self-heating model (v3 version) UM1575 16/24 doc id 023670 rev 1 4.4.4 recovery diode figure 21. recovery diode - schematic table 1. e off (comparison simulated/measured) r g ( ) measured e off (j) simulated e off (j) 4.7 4.1 3.9 10 4.31 4.4 47 6.8 7.1 200 27 29 iload1 vdd1 rgate1 vpulse1 r127 l33 lpar1 0 gipd251020131432fsr doc id 023670 rev 1 17/24 UM1575 a brief description of self-heating model (v3 version) 24 figure 22. recovery diode - simulated waveforms * , 3 ' ) 6 5 ( ( ( ( ( ( ( ( ( ( ( , ' $ w l p h v ? & ? & a brief description of self-heating model (v3 version) UM1575 18/24 doc id 023670 rev 1 4.4.5 unclamped inductive switching figure 23. unclamped inductive switching - schematic figure 24. unclamped inductive switching - simulated waveforms (test 1) table 2. simulated test conditions test t c energy i drain t j 1 110 c 0.3 j 83 a 83 c 2 110 c 0.3 j 203 a 133 c 5 d b t f % 4 ( 5 + ; u i 3 5 d b t f 3 h b u f 7 e e - p b e * , 3 ' ) 6 5 gipd251020131511fsr doc id 023670 rev 1 19/24 UM1575 a brief description of self-heating model (v3 version) 24 figure 25. unclamped inductive switching - simulated waveforms (test 2) figure 26. unclamped inductive switching - experimental waveforms gipd251020131513fsr gipd251020131518fsr a brief description of self-heating model (v3 version) UM1575 20/24 doc id 023670 rev 1 4.4.6 short-circuit test figure 27. short-circuit test - schematic figure 28. short-circuit test - waveforms 5 d b t f % 4 ( 5 + ; u i 3 5 d b t f 3 h b u f 7 e e - p b e * , 3 ' ) 6 5 ( ( ( ( ( ( ( m x q f w l r q 7 h p s h u d w x u h ? & ' u d l q & x u u h q w $ w l p h v : , 7 + 6 ( / ) + ( $ 7 , 1 * 0 2 ' ( / : , 7 + 2 8 7 6 ( / ) + ( $ 7 , 1 * 0 2 ' ( / - 8 1 & 7 , 2 1 7 ( 0 3 ( 5 $ 7 8 5 ( * , 3 ' ) 6 5 doc id 023670 rev 1 21/24 UM1575 a brief description of self-heating model (v3 version) 24 4.4.7 flyback simulated by self-heating model figure 29. flyback simulated by self-heating model - schematic figure 30. flyback simulated by self-heating model - simulated waveforms 7 ; 9 5 5 5 $ 5 6 7 3 6 ' ' / & / 8 / 5 $ 5 5 5 8 ' 6 7 - 7 d p e 5 & ' 5 & 3 u l p d u \ o h d n d j h 7 u d q v i r u p h u & o d p s ( o h p h q w v , q w h u q d o ' u l y h u 5 h v l v w d q f h 6 h q v h 5 h v l v w r u 3 d u d v l w l f , q g x f w d q f h 3 d u d v l w l f , q g x f w d q f h * , 3 ' ) 6 5 gipd251020131521fsr a brief description of self-heating model (v3 version) UM1575 22/24 doc id 023670 rev 1 where: ? blue line = (tx current sec)/10 ? black line = (tx current pri) ? red line = mosfet drain current if you have further questions, feel free to contact us via our local sale offices. doc id 023670 rev 1 23/24 UM1575 revision history 24 5 revision history table 3. document revision history date revision changes 25-nov-2013 1 initial release. UM1575 24/24 doc id 023670 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com |
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