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DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 1 of 90 ? 2016 dialog semiconductor general d escription DA9210 is a multi - phase synchronous step - down converter suitable for suppl y ing the cpu power in smartphones, tablets, u ltrabooks tm , and other handheld applications, which require high currents to run the processor core. DA9210 is designed to operate with four phases, each phase using a small external 0.47 h inductor. the buck is capable of delivering up to 12 a continuous output current with an output voltage of 0.3 v to 1.57 v. the input voltage range of 2.8 v to 5.5 v makes it suited for a wide variety of low voltage systems, including all li - ion battery supplied applications. two DA9210 s can be used in parallel to deliver an output current of up to 24 a. the DA9210 point - of - load remote - sensing feature guara ntees the highest accuracy while supporting multiple pcb routing scenario s without loss of performance. the highly - integrated design removes the need for external switching fets or schottky diodes. a programmable soft start - up can be enabled, which limits the inrush current from the input node and ensures a slope controlled activation of the rail. the dynamic voltage control (dvc) supports adaptive adjustment of the supply voltage dependent on the processor load . this is done via direct register write throu gh the communication interface (i 2 c or spi co mpatible) , via the dedicated dvc control i nterface , or via a programmable input pin. DA9210 integrate s over - temperature and over - current protection for increased system reliability, without the need for external sensing components. a power good and over - current alarm output informs the cpu of an out range voltage output and if the current exceeds a programmable limit, thereby enabling the processor to reduce its consumpti on before the supply rail collapse s . key f eatures 2.8 v to 5.5 v i nput voltage 0.3 v to 1.57 v o utput voltage 12 a output c urrent 24 a output current in parallel c onfiguration 3 mhz nominal switching f requency enables use of low - profile inductors output vo ltage accuracy 2.5 % dynamic voltage control (dvc) automatic phase s hedding integrated power s witches remote s ensing at p oint - of - l oad power good and over - current alarm signal interface s: i 2 c and spi d edicated dvc gpio adjustable soft - s tart - 40 oc to + 125 oc junction temperature operation regulator supervision with automatic under - voltage and over - voltage protection aec q100 g rade 3 automotive option package 48 wlcsp (route easy tm , equivalent to 0.8 mm pitch) package 42 vfbga 0.8 mm pitch (automotive) a pplications high performance multi - core system - on - chip (soc) applications smartphones mobile phones u ltrabooks tm tablet pcs in - c ar i nfotainment /dashboard portable navigation devices tv and m edia players embedded industrial systems
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 2 of 90 ? 2016 dialog semiconductor contents general description ................................ ................................ ................................ ............ 1 key features ................................ ................................ ................................ ...................... 1 applications ................................ ................................ ................................ ....................... 1 contents ................................ ................................ ................................ ............................ 2 figures ................................ ................................ ................................ .............................. 4 tables ................................ ................................ ................................ ................................ 5 1 block diagram ................................ ................................ ................................ .............. 6 2 pinout ................................ ................................ ................................ ........................... 7 2.1 pin configuration (48 wlcsp) ................................ ................................ ................. 7 2 .2 pin configuration (42 vfbga) ................................ ................................ .................. 9 3 absolute maximum ratings ................................ ................................ ......................... 12 4 recommended operating conditions ................................ ................................ ........... 12 5 typical current consumptions ................................ ................................ ..................... 13 6 electrical characteristics ................................ ................................ ............................. 13 6.1 dc/dc buck converter ................................ ................................ ......................... 15 6.2 2 - wire control bus ................................ ................................ ............................. 16 6.3 4 - wire control bus ................................ ................................ ............................. 18 6.4 dvc interface ................................ ................................ ................................ ...... 19 6.5 power good and temperature supervision ................................ .............................. 19 7 typical characteristics ................................ ................................ ................................ 20 8 functional description ................................ ................................ ................................ . 33 8.1 dc/dc buck converter ................................ ................................ ......................... 34 8.1.1 switching frequency ................................ ................................ ............... 35 8.1.2 operation modes and phase selection ................................ ....................... 36 8.1.3 output voltage selection ................................ ................................ .......... 36 8.1. 4 soft start - up ................................ ................................ ........................... 37 8.2 ports description ................................ ................................ ................................ .. 38 8.2.1 vdd_io rail ................................ ................................ .......................... 38 8.2.2 en_chip ................................ ................................ ............................... 38 8.2.3 gpio0 ................................ ................................ ................................ ... 38 8.2.4 verror / gpio1 ................................ ................................ ................... 38 8.2.5 i phase / gpio2 ................................ ................................ ..................... 38 8.2.6 buck_clk / gpio3 ................................ ................................ ............... 39 8.2.7 digital external clock input / gpio4 ................................ .......................... 39 8.2.8 oc_pg / nirq ................................ ................................ ....................... 39 8.3 DA9210 operating modes ................................ ................................ ..................... 44 8.3.1 on mode ................................ ................................ ............................... 44 8.3.2 off mode ................................ ................................ ............................. 44 8.3.3 dual parallel mode ................................ ................................ .................. 44 8.4 gpio extender ................................ ................................ ................................ .... 46
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 3 of 90 ? 2016 dialog semiconductor 8.5 control interfaces ................................ ................................ ................................ . 48 8.5.1 4 - wire communication ................................ ................................ ........... 48 8.5.2 2 - wire communication ................................ ................................ ........... 53 8.5.3 dvc interface ................................ ................................ ........................ 55 8.6 internal temperature supervision ................................ ................................ ........... 58 9 register definitions ................................ ................................ ................................ ..... 59 9.1 register map ................................ ................................ ................................ ....... 59 9.2 register page control ................................ ................................ ........................... 60 9.3 register page 0 ................................ ................................ ................................ ... 60 9.3.1 system control and event ................................ ................................ ........ 60 9.3.2 gpio control ................................ ................................ ......................... 63 9.3.3 regulator control ................................ ................................ .................... 65 9.4 register page 1 ................................ ................................ ................................ ... 67 9.4.1 regulators settings ................................ ................................ ................. 67 9.5 register page 2 ................................ ................................ ................................ ... 71 9.5.1 interface and otp settings (shared with da9063) ................................ ....... 72 9.5.2 application configuration settings ................................ ............................. 73 10 application information ................................ ................................ ............................... 77 10.1 capacitor selection ................................ ................................ .............................. 77 10.2 inductor selection ................................ ................................ ................................ 78 10.3 layout guidelines ................................ ................................ ................................ 79 10.3.1 general recommendations ................................ ................................ ...... 79 10.3.2 switched mode supplies ................................ ................................ .......... 79 10.3.3 DA9210 thermal connection, land pad and stencil design .......................... 79 11 package information ................................ ................................ ................................ .... 80 11.1 package outline drawing (48 wlcsp) ................................ ................................ .... 8 0 11.1.1 routeeasy tm technology chart ................................ ................................ 81 11.2 package outline drawing (42 vf - bga) ................................ ................................ ... 82 11.3 soldering information ................................ ................................ ............................ 83 12 ordering information ................................ ................................ ................................ ... 84 appendix a definitions ................................ ................................ ................................ ..... 85 a.1 power dissipation and thermal design ................................ ................................ ... 85 a.2 regulator parameter - dropout voltage ................................ ................................ ... 86 a.3 regulator parameter C power supply rejection ................................ ........................ 86 a.4 regulator parameter C line regulation ................................ ................................ ... 86 a.5 regulator parameter C load regulation ................................ ................................ .. 87 revision history ................................ ................................ ................................ ............... 88
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 4 of 90 ? 2016 dialog semiconductor figures figure 1: block diagram ................................ ................................ ................................ ........ 6 figure 2: connection diagram (48 wlcsp) ................................ ................................ .............. 7 figure 3: connection diagram (42 vfbga) ................................ ................................ .............. 9 figure 4: 4 - wire bus timing ................................ ................................ ............................... 18 figure 5: efficiency vs output current v out = 1.0 v ................................ ................................ . 20 figure 6: efficiency vs output current v out = 1.2 v ................................ ................................ . 20 figure 7: efficiency vs output current v out = 0.9 v ................................ ................................ . 21 figure 8: efficiency vs output current v out = 1.0 v, dual parallel mode (24 a max) ...................... 21 figure 9: efficiency vs output current v out = 1.2 v, dual parallel mode (24 a max) ...................... 22 figure 10: efficiency vs output current v out = 0.9 v, dual parallel mode (24 a max) .................... 22 figure 11: efficiency vs input voltage i out = 100 ma ................................ ................................ 23 figure 12: efficiency vs input voltage i out = 2 ma ................................ ................................ ... 23 figure 13: efficiency vs input voltage i out = 10 a ................................ ................................ .... 24 figure 14: start - up no load, startup_ctrl = 000 (slowest), vdd = 3.6 v, v out = 1.0 v ............ 24 figure 15: start - up no load, startup_ctrl = 100, v dd = 3.6 v, v out = 1.0 v ........................... 25 figure 16: start - up no load, startup_ctrl = 111 (fastest), v dd = 3.6 v , v out = 1.0 v ............... 25 figure 17: start - up 1 a load, startup_ctrl = 000 (slowest), v dd = 3.6 v, v out = 1.0 v ............ 26 figure 18: start - up 1 a load, startup_ctrl = 100, v dd = 3.6 v, v out = 1.0 v .......................... 26 figure 19: start - up 1 a load, startup_ctrl = 111 (fastest), v dd = 3.6 v, v out = 1.0 v .............. 27 figure 20: start - up from en_chip, no load, startup_ctrl = 100, v dd = 3.6 v, v out = 1.0 v .... 27 figure 21: switching waveforms, pwm, no load, v dd = 3.6 v, v out = 1.0 v ................................ . 28 figure 22: voltage and current ripple, pwm, no load, v dd = 3.6 v, v out = 1.0 v ........................... 28 figure 23: switching waveforms, pfm, no load, v dd = 3.6 v, v out = 1.0 v ................................ .. 29 figure 24: transient load, pwm, dual mode, 8 - phases 5 a to 17 a (12 a/s), v dd = 3.7 v, v out = 1.0 v ................................ ................................ ................................ ...................... 29 f igure 25: transient load, pwm, dual mode, 8 - phases ................................ ............................ 30 figure 26: transient load, auto, dual mode, 8 - phases 1 to 10 a in 12 a/s, v dd = 3.7 v, v out = 1.0 v ................................ ................................ ................................ ................................ ........ 30 figure 27: transient load, auto, 4 - phases 1 to 5 a in 10 a/s, v dd = 3.7 v, v out = 1.0 v .............. 31 figure 28: transient load, auto, dual mode, 8 - phases, 0.22 h 1 to 10 a in 12 a/s, v dd = 3.7 v, v out = 1.0 v ................................ ................................ ................................ ....................... 31 figure 29: transient load, auto, 4 - phases, 10 ma to 5 a in 10 a/s, v dd = 3.7 v, v out = 1.0 v ...... 32 figure 30: control ports and interface ................................ ................................ .................... 34 figure 31: concept of control of DA9210s buck output voltage ................................ ............... 37 figure 32 : configuration of oc_pg pin functionality ................................ ............................... 42 figure 33: oc_pg timing diagram (config_a = 0x16) ................................ .......................... 43 figure 34: dual parallel mode configuration ................................ ................................ ........... 45 figure 35: gpio principal block diagram with nirq signal (example paths) ............................... 47 figure 36: 4 - wire host write and r ead timing (ncs_pol = 0, cpol = 0, cpha = 0) ............ 50 figure 37: 4 - wire host write and read timing (ncs_pol = 0, cpol = 0, cpha = 1) ............ 50 figure 38: 4 - wire host write and read timing (ncs_pol = 0, cpol = 1, cpha = 0) ............ 51 figure 39: 4 - wire host write and read timing (ncs_pol = 0, cpol = 1, cpha = 1) ............ 51 figure 40: timing of the start and stop conditions ................................ ............................ 54 figure 41: byte write operation ................................ ................................ ............................ 54 figure 42: examples of byte read operations ................................ ................................ ........ 54 figure 43: 2 - wire page read ................................ ................................ ............................. 55 figure 44: 2 - wire page writ e ................................ ................................ ............................. 55 figure 45: 2 - wire repeated write ................................ ................................ ....................... 55 figure 46: dvc control interface ................................ ................................ .......................... 57 figure 47: register map ................................ ................................ ................................ ...... 59 figure 48: package outline drawing (48 wlcsp) ................................ ................................ ... 80 figure 49: package outline drawing (42 vf - bga) ................................ ................................ .. 82 figure 50: line regulation ................................ ................................ ................................ ... 86 figure 51: load regulation ................................ ................................ ................................ .. 87
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 5 of 90 ? 2016 dialog semiconductor tables table 1 pin description (48 wlcsp) ................................ ................................ ....................... 7 table 2: pin type definition ................................ ................................ ................................ ... 8 table 3: pin list (42 vfbga) ................................ ................................ ................................ . 9 table 4: pin type definition ................................ ................................ ................................ . 11 table 5: absolute maximum ratings ................................ ................................ ..................... 12 table 6: recommended operating conditions ................................ ................................ ........ 12 table 7: typical current consumption ................................ ................................ ................... 13 table 8: dc characteristics ................................ ................................ ................................ . 13 table 9: dc/dc buck converter characteristics ................................ ................................ ...... 15 table 10: 2 - wire interface electrical characteristics ................................ ............................... 17 table 11: 4 - wire interface electrical characteristics ................................ ............................... 18 table 12: dvc interface ................................ ................................ ................................ ...... 19 table 13: power good and temperature supervision ................................ .............................. 19 table 14: selection of buck current limit from coil parameters ................................ ................ 37 table 15: 4 - wire clock configurations ................................ ................................ ................. 49 table 16: 4 - wire interface summary ................................ ................................ .................... 51 table 17: page_con (0x00) ................................ ................................ ............................... 60 table 18: page_con (0x50) ................................ ................................ ............................... 60 table 19: status_b (0x51) ................................ ................................ ................................ 61 table 20: event_a (0x52) ................................ ................................ ................................ .. 61 table 21: event_b (0x053) ................................ ................................ ................................ 61 table 22: mask_a (0x54) ................................ ................................ ................................ ... 62 table 23: mask_ b (0x55) ................................ ................................ ................................ ... 62 table 24: control_a (0x56) ................................ ................................ ............................. 62 table 25: gpio0 - 1 (0x58) ................................ ................................ ................................ .... 63 table 26: gpio2 - 3 (0x59) ................................ ................................ ................................ .... 64 table 27: gpio4 - 5 (0x54) ................................ ................................ ................................ .... 64 table 28: gpio6 (0x5b) ................................ ................................ ................................ ...... 65 table 29: buck_con (0x5d) ................................ ................................ .............................. 65 table 30: page_con (0x80) ................................ ................................ ............................... 67 table 31: buck_ilim (0xd0) ................................ ................................ ............................... 67 table 32: buck_conf1 (0xd1) ................................ ................................ .......................... 68 table 33: buck_conf2 (0xd2) ................................ ................................ .......................... 69 table 34: vbuck_au to (0xd4) ................................ ................................ .......................... 69 table 35: vbuck_base (0xd5) ................................ ................................ ........................... 69 table 36: vbuck_max (0xd6) ................................ ................................ ............................ 70 table 37: vbuck_dvc (0xd7) ................................ ................................ ............................ 70 table 38: vbuck_a (0xd8) ................................ ................................ ................................ . 71 table 39: vbuck_b (0xd9) ................................ ................................ ................................ . 71 table 40: page_con (0x100) ................................ ................................ ............................. 71 table 41: interface (0x105) note 1 ................................ ................................ .................. 72 table 42: interface2 (0x106) ................................ ................................ ........................... 73 table 43: config_a (0x143) ................................ ................................ .............................. 73 table 44: config_b (0x144) ................................ ................................ .............................. 74 table 45: config_c (0x145) ................................ ................................ .............................. 74 table 45: config_d (0x146) ................................ ................................ .............................. 75 table 46: config_e (0x147) ................................ ................................ .............................. 75 table 47: misc_supp (0x14f) ................................ ................................ ............................ 76 table 48: device_id (0x201) ................................ ................................ .............................. 76 table 49: device_id (0x203) ................................ ................................ .............................. 76 table 50: device - id (0x203) ................................ ................................ .............................. 76 table 51: config_id (0x204) ................................ ................................ ............................. 76 table 52: r ecommended capacitor types ................................ ................................ ............. 77 table 53: recommended inductor types (including only typical values for the parts ..................... 78 table 54: ord ering information ................................ ................................ ............................. 84
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 6 of 90 ? 2016 dialog semiconductor 1 block d iagram figure 1 : block d iagram v s y s v o u t _ s e n s e d v s d a c v s s _ q u i e t r e g i s t e r s p a c e v d d c o r e o t p m e m o r y d i g i t a l c o r e 2 / 4 - w i r e / d v c c t r l i n t e r f a c e e n _ c h i p v d d _ i o c t r l + d r i v e b i a s s u p e r v o s c v s s _ n o i s y v e r r o r / g p i o 1 o u t o c _ p g / n i r q 2 2 0 n f 4 x 0 . 4 7 h 4 x 4 7 f 4 x 1 0 f a c _ o k / g p i o 4 n c s / s y n c g p i o 5 s i / d a t a s k / c l k s o / i n p u t g p i o 6 i n i n g p i o g p i o g p i o g p i o v s s _ s e n s e l / c / r p c b - c p u b u c k _ c l k / g p i o 3 g p i o g p i o 0 g p i o i p h a s e / g p i o 2 g p i o t p 1 f v d d 1 v d d 2 v d d 3 v d d 4
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 7 of 9 0 ? 2016 dialog semiconductor 2 pin out 2.1 pin c onfiguration (48 wl csp) figure 2 : connec tion d iagram (48 wlcsp) table 1 pin description (48 wl csp) pin no. pin n am e alter nate f unction type description a1, b2, b4 lx1 ao sw itching node for phase 1 j1, h2, h4 lx2 ao sw itching node for phase 2 a13, b10, b12 lx3 ao sw i tching node for phase 3 j13, h10, h12 lx4 ao sw itching node for phase 4 a3, a5 vdd1 ps supply voltage for phase 1 to be connected to vsys j3, j5 vdd2 ps supply voltage for phase 2 to be connected to vsys a9, a11 vdd3 ps supply voltage for phase 3 t o be connected to vsys j9, j11 vdd4 ps supply voltage for phase 4 to be connected to vsys c13 en_chip di ic enable signal c1 oc_pg nirq do output for over current alarm and pow er good signal, irq line tow ards the host g13 vdd_io ps i/o voltage r ail e1 vout_sense ai output and s ense node for the buck
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 8 of 90 ? 2016 dialog semiconductor pin no. pin n am e alter nate f unction type description d2 vss_sense ai ground s ense node for the buck f2 vddcore ao regulated supply for internal circuitry 2.5 v (decouple w ith 220 nf) f12 gpio0 ai/dio general purpose i/o d12 verror gpio1 aio/dio err or amplifier v oltage s ignal for dual parallel mode, general purpose i/o e13 iphase gpio2 aio/dio current distribution s ignal for dual parallel mode, general purpose i/o g1 buck_clk gpio3 dio buck clock input/o utput (depending on slave/master function in dual parallel mode), general purpose i/o b8 ac_ok gpio4 dio input from safe charger out to oc_pg signalling, general purpose i/o, input of external 6 mhz clock h8 ncs/sync gpio5 dio 4 - wire chip se lect, dvc interface input clock , general purpose i/o j7 s o/input gpio6 dio 4 - wire d ata o utput, dvc i nterface input data, general purpose i/o b6 si data dio 4 - wire d ata i nput, 2 - wire d ata a7 sk clk di 4 - wire/2 - wire clock c7 tp dio test pin connect to vss e3, e11 nc vss electrically not connected connect to vss h6 vsys ps supply for ic and input for voltage supervision g7 vss_quiet vss c3, c5, g3, g5, c9, c11, g9, g11 vss_noisy vss table 2 : pin type d efinition pin type description pin type description di digital input ai anal og input do digital output ao analog output dio digital input/output aio analog input/output diod digital input/output o pen drain bp backdrive protection pu fixed pull - u p resistor spu sw itchable p ull - u p resistor pd fixed pull - d ow n resistor spd sw itch able p ull - dow n resistor
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 9 of 90 ? 2016 dialog semiconductor 2.2 pin c onfiguration (42 vf bga) figure 3 : connection d iagram (42 vf bga) table 3 : pin list (42 vfbga) pin no. pin nam e alternate function type description b1, b2 lx1 ao sw itching no de for phase 1 e1, e2 lx2 ao sw itching node for phase 2 b6, b7 lx3 ao sw itching node for phase 3 e6, e7 lx4 ao sw itching node for phase 4 a1, a2 vdd1 ps supply voltage for phase 1 to be connected to vsys f1, f2 vdd2 ps supply voltage for phase 2 to be connected to vsys a6, a7 vdd3 ps supply voltage for phase 3 to be connected to vsys
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 10 of 90 ? 2016 dialog semiconductor pin no. pin nam e alternate function type description f6, f7 vdd4 ps supply voltage for phase 4 to be connected to vsys a5 en_chip di ic enable signal c5 oc_pg nirq do output for over current alarm and pow er good signal, irq line tow ards the host a4 vdd_io ps i/o voltage r ail d4 vout_sense ai output and sense node for the buck c4 vss_sense ai ground sense node for the buck f5 vddcore ao regulated supply for internal circuitry (decouple w ith 220 nf) b5 gpio 0 ai/dio general purpose i/o b4 verror gpio1 aio/dio error amplifier voltage s ignal for dual parallel mode, general purpose i/o e4 iphase gpio2 aio/dio current distribution s ignal for dual parallel mode, general purpose i/o e5 buck_clk gpio3 dio buck c lock input/o utput (depending on slave/master function in dual parallel mode), general purpose i/o c3 ac_ok gpio4 dio input from safe charger out to oc_pg signalling, general purpose i/o, input of external 6 mhz clock d3 ncs/sync gpio5 dio 4 - wire chip sel ect, dvc interface input clock , general purpose i/o e3 so/input gpio6 dio 4 - wire data o utput, dvc interface input data, general purpose i/o b3 si data dio 4 - wire d ata i nput, 2 - wire d ata
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 11 of 90 ? 2016 dialog semiconductor pin no. pin nam e alternate function type description a3 sk clk di 4 - wire/2 - wire c lock d5 tp dio test pin, connect to vss f3 vsys ps supply for ic and input for voltage supervision f4 vss_quiet vss c1, c2, d1, d2, c6, c7, d6, d7 vss_noisy vss table 4 : pin type d efinition pin type description pin type description di digital input ai analo g input do digital output ao analog output dio digital input/output aio analog input/output diod digital input/output o pen drain bp backdrive protection pu fixed pull - u p resistor spu sw itchable pull - u p resistor pd fixed pull - d ow n resistor spd sw itcha ble pull - d ow n resistor
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 12 of 90 ? 2016 dialog semiconductor 3 absolute m aximum r atings table 5 : absolute m aximum r atings param eter description conditions ( note 1 ) min max unit t stg storage temperature - 65 +1 50 c t j ope rating junction temperature - 40 + 150 note 2 c v sys supply v oltage - 0.3 5.5 v a ll pins except above - 0.3 v sys + 0.3 v esd protection hbm 2000 v note 1 stre sses beyond those listed under a bsolute m aximum ra tings may cause permanent damage to the device. these are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. exposure to abso lute maximum rating conditions for extended periods may affect device reliability. note 2 see s ection s 11.1 and 8 .6 for more detail 4 recommended operating c onditions table 6 : recommended operating c onditions param eter description conditions min typ max unit v sys supply v oltage 2.8 5.5 v v dd_io supply v oltage io 1.2 3.6 note 1 v maximum pow er d issip ation note 2 derating factor above t a = 70 c: 33 mw/c 48 wl - csp 1815 2310 mw derating factor above t a = 70c: 28 mw/c 42 vf - bga 1540 1960 mw note 1 vdd_io must not exceed vsys note 2 obtain from simulation on a 2s2p 4l jedec board. influenced by pcb technology and layout. all v oltages are referenced to v ss unless otherwise stated. currents flowing into DA9210 are deemed positive, curr ents flowing out are deemed negative. all parameters are valid over the recommended temperature range and power supply range unless otherwise noted. please note that power dissipation must be limited to avoid overheating of DA9210 . m aximum power dissipation should not be reached with maximum ambient temperature.
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 13 of 90 ? 2016 dialog semiconductor 5 typical current c onsumptions table 7 : typical c urrent c onsumption operating mode conditions ba ttery (typ) unit off m ode en_chip low <1 a on m ode en_chip high, buck_en = 0 (excluding the current consumption of the buck) 45 a 6 electrical characteristics table 8 : dc c haracteristics param eter description conditions min typ max unit en_on en_chip level on 1.1 v en_off en_chip level off 0.35 v en_hyst en_chip hysteresis 100 mv i en_chip en_chip input current v en_chip ? 1.1 v 100 na t en ic control start - up time 750 s v ddco re v ddcore voltage 2.5 v v ih gpi0 - 6, sync, input, clk, data, (2 - wire mode) input high voltage vddcore mode vdd_io mode 0.7*v ddcore 0.7*v dd_io v v il gpi0 - 6, sync, input, clk, data, (2 - wire mode) input low voltage vddcore mode vdd_io mode 0.3*v ddco re 0.3*v dd_io v v ih sk, ncs, si (4 - wire mode) input high voltage 0.7*v dd_io v v il sk, ncs, si (4 - wire mode) input low voltage 0.3*v dd_io v
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 14 of 90 ? 2016 dialog semiconductor param eter description conditions min typ max unit v oh gpo0 - 6, oc_pg, so (4 - wire ode) output high voltage push - pull m ode @1 ma v dd_io 1.5 v 0.8*v dd_io v v ol @1 ma gpo0 - 6, oc_pg, data (2 - wire mode) so (4 - wire mode) output low voltage 0.3 v v ol @3 ma data (2 - wire mode) output 0.24 v v ol @20 ma data (2 - wire mode) output low voltage 0.4 v c in clk, data (2 - wire mode) input capa citance 2.5 10 pf t sp clk, data (2 - wire mode) spike suppression fast/fast+ mode high speed mode 50 10 ns t fda data (2 - wire m ode) fast @ cb<550 pf hs @ 10 DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 15 of 90 ? 2016 dialog semiconductor 6.1 dc/dc b uck c onverter unless otherwise noted, the following is valid for v dd = 2.8 v to 5.5 v, c out = 4x 47 f, local sensing , f = 3 mhz . table 9 : dc/dc b uck c onvert e r c haracteristics param eter description conditions min typ max unit v dd input voltage v dd = v sys 2.8 5.5 v c out output capacitor including voltage and temperature coefficient 100 200 (4x47) (8x22) 400 f l buck inductor value (per phase) including cur rent and temperature dependence - 50 % 0.47 +30 % h v out output voltage note 1 i out = 0 ma to i max 0.3 1.57 v output voltage accuracy v dd = 3.8 v v out = 0.9 v t a = 25 c no load - 0.5 +0.5 % v dd = 3.8 v v out = 0.9 v t a = - 25 c to +85 c no load - 1.0 +1.0 % including static line/load regulation and voltage ripple v out 1 v - 2.5 +2.5 % including static line/load regulation and voltage ripple v out < 1 v 25 mv vtr load load regulation transient note 2 i out = 0 / 5 a di/dt = 10 a/s 4 - phase operation v out = 1 v 2 % vtr line line regulation transient v dd = 3.0 to 3.6 v i out = i max tr = tf = 10 s 10 mv max resistance pcb for remote sensing note 3 f rom output capacitor to sense connection at point of load 10 m? max inductance pcb for remote sensing note 4 f rom output capacitor to sense connection at point of load 10 nh r fb feedback c omparator input impedance 500 k? i max output current 4 - phase operation 12000 ma
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 16 of 90 ? 2016 dialog semiconductor param eter description conditions min typ max unit i lim current li mit per phase (programmable) note 5 buck_ilim = 0010 - 20 % 2000 note 6 20 % ma buck_ilim = 1111 - 20 % 4 600 20 % ma i alarm current a larm t hreshold (programmable) b uck_ialarm = 0 and buck_ilim 1010 ilim - 600 ilim C 300 ilim - 100 ma b uck_ialarm = 1 and buck_ilim 1010 ilim - 1000 ilim C 600 ilim - 300 ma iq on quie scent current in synchronous rectification mo de 4 - phase operation no load v dd = 3.7 v 60 ma i min_pfm minimum o utput c urrent in pfm m ode static output voltage, no dvc note 7 2 ma f sw itching frequency 2.79 3 3.21 mhz minimum on time 20 ns t on t urn - on time startup_ctrl = 01 1 50 s output pull - dow n resistor can be sw itched off via buck_pd_dis 150 200 ? note 1 programmable in 10 mv increments note 2 additional to the dc accuracy. the value is intended measured directly at c out . in case of remote sensing, parasitics of pcb and external components may affect this value. note 3 10 m? equivalent to a 5 inch (ca 13 cm) copper t race ( ? = 1.7x10 - 8 ?/m), w idth 6 mm, thickness 35 m note 4 10 nh equivalent to a 5 inch (ca 13 cm) trace routed over a ground plane (approx. 1.2 nh/cm) note 5 peak current on the inductor note 6 minimum value of the a ccuracy is 400 ma under all conditions note 7 for dvc , see a pplic ation note an - pm - 052 6.2 2 - wire c ontrol b us figure 4: 2 - w ire i nterface t iming s t o p s d a s c l t f t r t f s t a r t t h _ s t a t h _ d 1 / f s c l v i h v i l v i h v i l t s u _ d t l o w t h i g h t v d _ d a c k t v d _ a c k t s u _ s t o
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 17 of 90 ? 2016 dialog semiconductor table 10 : 2 - w ire i nterface e lectrical c haracteristics param eter description test conditions min typ max unit t buf bus free time stop to start 0.5 s c b bus line capacitive load 150 pf standard/fast/fast m ode f scl scl clock frequency note 1 0 1000 khz t su_sta start condition set - up time 0.26 s t h_sta start condition hold time 0.26 s t w_cl scl low time 0.5 s t w_ch scl high time 0.26 s t r 2 - wire scl and sda rise time (input requirement) 1000 ns t f 2 - wire scl and sda fall time (input requirement) 300 ns t su_d data set - up time 50 ns t h_d data hold time 0 ns t vd_d data valid time 0.45 s t vd_ack data valid time acknow ledge 0.45 s t su_sto stop condition set - up time 0.26 s high s peed m ode f scl scl clock frequency requires v ddio 1.8 v note 1 0 3400 khz t su_sta start condition set - up time 160 ns t h_sta start condition hold time 160 ns t w_cl scl low time 160 ns t w_ch scl high time 60 ns t r 2 - w ire scl and sda rise time (input requirem ent) 160 ns t f 2 - w ire scl and sda fall time (input requirement) 160 ns t su_d data set - up time 10 ns t h_d data hold - time 0 ns t su_sto start condition hold time 160 ns note 1 minimum clock frequency is 10 khz if 2wire_to is enabled
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 18 of 90 ? 2016 dialog semiconductor 6.3 4 - wire c ontrol b us figure 4 : 4 - wire b us t iming note the above timing is valid for active low and high cs. table 11 : 4 - w ire interface electrical c haracteristics param eter description label in plot min typ max unit c ld bus l ine c apacitive load 100 pf t c cycle time 1 70 ns t css enable lead time 2, from cs active to first sk edge 20 ns t scs enable lag time 3, from last sk edge to cs idle 20 ns t cl clock low time 4 0.4 x tc ns t ch clock high time 5 0.4 x t c ns t sis data i n setup time 6 5 ns t sih data i n hold time 7 5 ns t sov data o ut valid time 8 22 ns t soh data o ut hold time 9 6 ns t wcs cs inactive time 11 20 ns
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 19 of 90 ? 2016 dialog semiconductor 6.4 dvc i nterface table 12 : dvc interface param eter des cription conditions min typ max unit t sync clock period at sync port 40 300 ns t pwh high pulse w idth at sync port 12 180 ns t pwl low pulse w idth at sync port 12 180 ns d sync duty cycle at sync port 40 60 % t setup set - up t ime input to rising ed ge of sync 10 ns t hold hold t ime input from rising edge of sync 2 ns t rise rise t ime input and sync ports 1 ns t fall fall t ime input and sync ports 1 ns 6.5 power g ood and t emperature s upervision table 13 : power g ood and t em perature s upervision param eter description conditions min typ max unit vgood pow er good low threshold v out (typ) - 0.05 v vgood _hyst pow er good low threshold hyst 50 mv temp_wa rn note 2 thermal w arning 110 125 140 c temp_crit thermal shutdow n threshold 125 140 155 c temp_por thermal por threshold 135 150 165 c note 2 thermal thresholds are non - overlapping
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 20 of 90 ? 2016 dialog semiconductor 7 typical c haracteristics figure 5 : efficiency vs output current v out = 1.0 v figure 6 : efficiency vs output current v out = 1.2 v
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 21 of 90 ? 2016 dialog semiconductor figure 7 : efficiency vs output current v out = 0.9 v figure 8 : efficiency vs output current v out = 1.0 v, dual parall el mode (24 a m ax)
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 22 of 90 ? 2016 dialog semiconductor figure 9 : efficiency vs output current v out = 1.2 v, dual parallel mode (24 a m ax) figure 10 : efficiency vs output current v out = 0.9 v , dual parallel mode (24 a m ax)
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 23 of 90 ? 2016 dialog semiconductor figure 11 : efficiency vs input voltage i out = 100 ma figure 12 : efficiency vs input voltage i out = 2 ma
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 24 of 90 ? 2016 dialog semiconductor figure 13 : efficiency vs input voltage i out = 10 a figure 14 : start - up no load, startup_ctrl = 000 (slowest), vdd = 3.6 v, v out = 1.0 v
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 25 of 90 ? 2016 dialog semiconductor figure 15 : start - up no load, startup_ctrl = 100, v dd = 3.6 v, v out = 1.0 v figure 16 : start - up no load, startup_ctrl = 111 (fa stest), v dd = 3.6 v, v out = 1.0 v
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 26 of 90 ? 2016 dialog semiconductor figure 17 : start - up 1 a load, startup_ctrl = 000 (slowest), v dd = 3.6 v, v out = 1.0 v figure 18 : start - up 1 a load, startup_ctrl = 100, v dd = 3.6 v, v out = 1.0 v
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 27 of 90 ? 2016 dialog semiconductor figu re 19 : start - up 1 a load, startup_ctrl = 111 (fastest), v dd = 3.6 v, v out = 1.0 v figure 20 : start - up from en_chip, no load, startup_ctrl = 100, v dd = 3.6 v, v out = 1.0 v
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 28 of 90 ? 2016 dialog semiconductor figure 21 : switching waveforms, pwm, no load, v dd = 3.6 v, v out = 1.0 v figure 22 : voltage and current ripple, p w m, no load, v dd = 3.6 v, v out = 1.0 v
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 2 9 of 90 ? 2016 dialog semiconductor figure 23 : switching waveforms, pfm, no load, v dd = 3.6 v , v out = 1.0 v figure 24 : transient l oad , pwm, dual mode, 8 - phases 5 a to 17 a ( 12 a/s ) , v dd = 3. 7 v, v out = 1. 0 v
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 30 of 90 ? 2016 dialog semiconductor figure 25 : transient load, pwm, dual mode, 8 - phases 5 to 17 a in 12 a/s, v dd = 3.7 v, v out = 1.0 v figure 26 : transient load, auto, dual mode, 8 - phases 1 to 10 a in 12 a/s, v dd = 3.7 v, v out = 1.0 v
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 31 of 90 ? 2016 dialog semiconductor figure 27 : transient load, auto, 4 - phases 1 to 5 a in 10 a/s, v dd = 3.7 v, v out = 1.0 v figure 28 : transient load, auto, dual mode, 8 - phases, 0.22 h 1 to 10 a in 12 a/s, v dd = 3.7 v, v out = 1.0 v
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 32 of 90 ? 2016 dialog semiconductor figure 29 : transient load, auto, 4 - phases, 10 ma to 5 a in 10 a/s, v dd = 3.7 v, v out = 1.0 v
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 33 of 90 ? 2016 dialog semiconductor 8 functional d escription the DA9210 quad - phase buck converte r has been designed to operate either as a high - performance stand - alone regulator or as a sub - pmic that extends the functionality of an integrated syst em pmic such as the dialog da9063. in stand - alone operation , the DA9210 provides: ? h igh performance, 12 a output current capability ? h igh efficiency , q uad - phase operation with phase - shedding ? a s mall footprint ? a n ov er - current alarm/ power good signal to provide real - time status information to the host processor. in the case of an over - current event or loss of power, the host processor is able to react to maximise system integrity when operated with a dialog system pm ic such as the da9063, the system also benefits from the following: ? t he DA9210 can be enabled as part of the system start - up sequence by utili z ing one of the da9063 sequenced gpio signals . ? t he DA9210 has been designed to operate seamlessly with the da9063 by sharing the same control interface (same spi chip select or i 2 c address) . ? t he DA9210 register map has been designed to interlea ve with the da9063 register map. when operated in this way, the two devices appear as a single power management solution to the host processor, thereby simplifying system power control . by using the general 2 - wire interface, the DA9210 can easily be integrated into power management systems using system pmics other than da9063. section 8.1 provides details of the individual blocks of the DA9210 and the configurability available to optimize its performance in any application.
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 34 of 90 ? 2016 dialog semiconductor figure 30 : control ports and interface as shown in figure 30 , a typical application cas e in cludes a host processor, a m ain pmic ( for example da9063) and the DA9210 used as companion ic for the high power core supply. the easiest way of controlling the DA9210 is through the c ontrol i nterface. the host processor is the master that initia tes communication and reads and writes to and from the main pmics and DA9210 s registers. to poll the status of DA9210 , the host processor must access the dedicated registers area through the c ontrol i nterface. a dditionally , DA9210 can be controlled by means of hardware inputs. a dedicated hardware signal from the DA9210 to the external host processor is implemented through the oc/pg line. 8.1 dc/dc b uck c onverter the buck converter is a fou r - phase , high efficiency , synchronous step down dvc regulator, typically operating at 3 mhz . the buck converter supports the sensing of the configured voltage directly at the point of load (see vout_sense and vss_sense pins , not supported in tracking mode ) . the d efault output voltage is loaded from otp. dvc operates in pwm mode (synchronous rectification). the completion of a dvc transition is signalled by gpio3, assuming the port is configured as gpo and the control bit ready_en is asserted. the buck converter has two voltage registers for output voltage a and b. the appropriate values are stored in the registers vbuck_a and vbuck_b . the specific output voltage is selected with the bit buck_sel in register buck_conf . this can be operated either via gpi or via the control interface, according to the configuration of vbuck_gpi . a dvc transition occurs:
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 35 of 90 ? 2016 dialog semiconductor w hen the selected voltage vbuck_a / vbuck_b is updated to a new target value w hen the voltage selection is changed via buck_sel from vbuck_a to vbuck_b or vice versa the slew rate of the dvc transition is programmed at 10 mv per (4, 2, 1 or 0.5 ) s via slew_rate control bits . the typical input current when four phases are enabled is in the order of 60 ma and drops to < 1 a when the buck output is disabled. 8.1.1 switching f requency the 3 mhz switching frequency has been chosen to allow the use of a small 0.47 h inductor (see the complete list of inductors i n s ection 10 ). the buck switching frequency can be tuned via register bit s osc_tune . th is tunes the internal 6 mhz oscillator frequency in steps of 180 khz. this impacts the buck converter frequency in steps of 90 khz. this is used to avoid possible disturbances to other hf systems in the application. if a digital input clock is applied at gpio4 and the port is configured accordingly on register bit gpio4_pin it i s possible to apply an external oscillator delivering 6 mhz to the system, thereby allowing multiple devices to be synchroni z ed to the same clock source.
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 36 of 90 ? 2016 dialog semiconductor 8.1.2 operation m odes and p hase s election the operating mode of the b uck converte r is selected via bits buck_mode in register buck_conf1 . the b uck converter can be forced to operate in either normal mode, where all four phases are enabled, or in low - p ower mode, where the efficiency is optimized for output currents lower than 1 a. in low - power mode, the buck can be forced to operate either with one (default), two, or four phases active, or in pfm mode where the operating frequency varies with the output load current. note the low - pow er mode configur ation is programmed in the device otp and cannot be changed during normal operation. please contact your local dialog semiconductor support for more information. the buck_mode bits also allow an a utomatic m ode based o n the output voltage to be selected. with the buck_mode configured this way t he buck will operate in low - power mode as long as the target voltage is lower than the threshold defined in vbuck_auto , or in n ormal mode otherwise . if buck_mode bits = 00, the operatin g mode is selected dependent on the register bit buck_s l_a/b , so the operatin g mode is set simultaneously with the output voltage . in low - power mode, the buck operates according to different options as previously described. the number of active phases can be selected by register bits phase_sel in register buck_conf2 . this optimi zes the efficiency acc ording to the specific output current needed for the application. if the bit phase_sel is asserted, automatic phase shedding based on the output current load is enabled. the buck automatically changes between 1 - phase , 2 - phase , and 4 - phase operation, thereby optimizing the efficiency in a wide range of output currents. a utomatic phase shedding works only in normal mode and the phase_sel field configuration is ignored. an automatic t ransition to pfm m ode (including automatic phase shedding) can be configured via auto_def . when th is bit is set, in addition to the phase shedding , pfm m ode is entered when the output load current becomes low ensuring m aximum efficiency . when operati ng in dual parallel mode , the master and the slave device will have up to a total of 8 phases enabled. if a phase is never selected for a certain application, the corresponding lx output pin should be left floating and not co nnected to any external inductor . 8.1.3 output v oltage s election the switching converter can be configured using the 2 - wire or 4 - wire interface, or via the dedicated dvc i nterface. the DA9210 provides the capability to set two output voltage levels via registers vbuck_a and vbuck_b . it is then possible to transition between these two voltages by toggling the register bit buck_sel, or by using a gpi, selected from gpi0, gpi3, or gpi4 in register bit vbuck_gpi. in addition to setting the output voltage, the vbuck_a/b registers include the buck_mode setting which allows the selection between normal and low power mod es. when triggered, the transition will ramp between the set voltages following the slew rate set by the slew_rate setting in register control_a . the register vbuck_max will limit the output voltage that can be set for the buck converter. in addition to triggering an a to b voltage transition, the host is able to modify the output voltage by writing to the currently active vbuck_a/b voltage setting. the current slew_rate setting wi ll be applied to any change triggered by this method. for security reasons the re - programming of registers that may cause damage if wrongly programmed ( for example, voltage settings) can be disabled by asserting the control v _ lock in the control_a register. when v_lock is asserted, reprogramming the registers 0xd0 to 0x14f from control interfaces is disabled.
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 37 of 90 ? 2016 dialog semiconductor DA9210 implements a dedicated control interface supporting direct dvc requests to the buck converter (see also t he detailed description in section 8.5.3 ) . when the bu ck is disabled a 150 (typ) pull - down resistor is activated for each phase depend ent o n the value stored in register bit buck_pd_dis . phases disabled via phase_sel will n ot have any pull - down. the pull - down resistor is always disabled on all phases when DA9210 is in off mode. figure 31 : concept of c ontrol of DA9210s b uck o utput v oltage the buck current limit should be configu red to be at least 40 % higher than the required maximum continuous output current. table 14 : selection of buck current limit from coil parameters min. isat (m a) frequency (mhz) buck current lim it (m a) average current (m a) 5060 3 4 600 3300 4180 3 3800 2700 3080 3 2800 2000 1760 3 1600 1100 8.1.4 soft s tart - up to limit the in - rush current from vsys input , the buck converter can perform a soft start after being enabled. the start - up behavior is a trade - off between acceptable in - rush cur rent from the battery and turn - on time. in DA9210 different options can be selected using startup bits in buck_conf1 register. rates faster than 20 mv/s may produce overshoot during the start - up phase, so they sho uld be considered carefully. a ramped power - down can be selected on register bit pwr_down_ctrl . if no ramp is selected, the output node will only be discharged by the pull - down resistor, if enabled via buck_pd_dis .
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 38 of 90 ? 2016 dialog semiconductor 8.2 ports d escription 8.2.1 vdd_io r ail vdd_io is an independent io supply rail input that can be assigned to the power manager interface and to the gpios (see control pm_if_v and gpi_v ). the rail assignment determines the io voltage levels and logical thresholds (see also the digital i/o characteristics). note the m aximum speed of the 4 - wire interface is only available if the selected supply rail is gre ater than 1.6 v. 8.2.2 en_chip en_chip is a general enable signal for DA9210 , turning on and off the internal circuitry ( for example the reference, the digital core, and so on ). the control of this port has a direct inf luence on the quiescent current of the whole application and a low level allows the device to reach the minimum quiescent current state. the voltage at this pin is continuously sensed by a dedicated analog circuit. the en_chip activation threshold is defin ed with a built - in hysteresis to avoid erroneous transitions being triggered by unstable rising or falling edges. the en_chip port has an integrated pull - down current . 8.2.3 gpio0 t he port behaves like a gpio e xtender p in (see section 8.4 ) . in a typical application gpio0 can be used as gpi port enable for the buck converter, as shown in figure 30 . 8.2.4 verror / gpio1 this port is multi - functional depending on the configuration of gpio1_pin . it can be used as an analog pin to support the dual parallel mode operation of DA9210 (input in case of slave, output in case of ma ster operation, see also s ection 8.3.3 ). alternatively it behaves like a standard gpio e xtender p in , see section 8.4 . if gpio1_pin = 01 the port will be configured for verror operation operating as an input or an output, depending on the voltage level on the vout_sense pin , see s ection 8.3.3 . in master mode , the port is an output. in sl ave mode (vout_sense must be ti ed high to vddcore) , the port is an input. if gpio1_pin = 01 and master mode is configured, whenever the buck converter is enabled, the signal at the output of the buck error amplifier is internally routed to the verror pin and is available externally. this allows the DA9210 to operate as a master together with another slave instance of DA9210 in dual DA9210 operation. if gpio1_pin = 01 and slave mode is configured, whenever the buck converter is enabled, the signal applied at the v error pin will be inte r nally routed as a replacement for the buck error amplifier output, thereby overriding the functionality of the amplifier in the regulation loop. this allows the DA9210 to operate as a slave together with another master instance of DA9210 in dual DA9210 operation. 8.2.5 iph ase / gpio2 this port is multi - functional according to the configuration of gpio2_pin . it can be used as a n a nalog pin to support the dual parallel mode operation of DA9210 (input in the case of operation as a slave, output in the case of operation as a master, see s ection 8.3.3 . alternatively it behaves like a standard gpio e xtender p in , see sectio n 8.4 .
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 39 of 90 ? 2016 dialog semiconductor if gpio2_pin = 01 the port will be configured for i phase operation as an input or an output, according to the voltage level on the vout_sense p in , see s ection 8.3.3 . in master mode the port is an output. in slave mode (vout_sense must be ti ed high to vddcore) the port is an input. if gpio2_pin = 01 and master mode is configured, whenever the buck converter is enabled, the signal from the current sense amplifier of one phase is internally routed to the i phase pin and is available externally. this allows the DA9210 to operate as a master together with another slave instance of DA9210 in dual DA9210 operation. if gpio2_pin = 01 and slave mode is configured, whenever the buck converter is enabled, the signal applied at the i phase pin will be internally routed as a replacement for the current sense amplifier of one phase, thereby overriding the function of that cu rrent sense amplifier in the current regulation loop. this allows the DA9210 to operate as a slave together with another master instance of DA9210 in dual DA9210 operation. 8.2.6 buck_clk / gpio3 this port is multi - functional according to the configuration gpio3_pin . it can be used as a digital pin to support the dual parallel mode operation of DA9210 ( input in the case of operation as a slave, output in the case of operation as a master , see s ection 8.3.3 . alternatively it behaves li ke a standard gpio e xtender p in , see section 8.4 . if gpio3_pin = 01 t he port will be configured for buck c lock operation as an input or an output, according to the voltage level at vout_sen se p in , see s ection 8 .3.3 . in master mode the port is an output. in slave mode (vout_sense must be ti ed high to vddcore) the port is an input. if gpio3_pin = 01 and master mode is configured, whenever the buck converter is enabled, the clock signal of the buck converter is internally routed to the buck_clk pin and is available externally . this allows to use DA9210 in dual operation as a master together with another slave instance of da92 10 . if gpio3_pin = 01 and slave mode is configured, whenever the buck converter is enabled, the signal applied at buck_clk pin will be internally routed to the clock generation block of the buck converter, thereby ov erriding the functionality of the internal buck clock. this allows the DA9210 to operate as a slave together with another master instance of DA9210 in dual DA9210 operation. 8.2.7 digital e xternal c lock i nput / gpio4 this port is multi - functional according to the configuration of gpio4_pin . it can be used as digital external clock input for the system, if a signal of typically 6 mhz is applied to the pin. note the clock must already be running and stable before configuring the port via gpio4_pin and before enabling the buck converter. missing pulses or signals applied at different frequen c ies than specified may cause d i sruption of the ic. alternatively it behaves like a standard gpio e xtender pin, see section 8.4 . 8.2.8 oc_pg / nirq the oc_pg (over current alarm and power good) is an output port shared with nirq and can be either push - pull or open - drain (selected via oc_pg_irq_type). the port can be configured as active high or active low via control oc_pg _irq_level. if oc_pg_irq_conf = 0 the port is used as irq line. it indicates that an interrupt causing event has occurred and that the event/status information is available in the related registers 0x50 to 0x53 . s uch information can be a warning o f critical temperature, fault conditions , or status changes on gpi ports. the event registers hold information about the events that have occurred. events are triggered by a status change at the monitored signals. when an event bit is set , the nirq signal is asserted (unless this interrupt is masked by a corresponding bit in the irq mask registers 0x54 and 0x55 ). the nirq is not released until all event registers with asserted bits have been read and cleared. new
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 40 of 90 ? 2016 dialog semiconductor events tha t occur during event register reading are held until the event register has been read and cleared, ensuring that the host processor does not miss them. if oc_pg_irq_conf = 1, the oc_pg functionality is selected. the oc_pg funct ion is valid for li - ion battery voltage rang ing from 2.8 v to 4.4 v. this can be used for a dedicated communication to the host processor. oc_pg remains asserted while as at least one of the status indicators is active (see registers 0x50 an d 0x51 ). this allows the host processor to be immediately informed and to promptly react by, for example, reducing its operating frequency. after the fast reaction, the host processor can then check the status registers to see what is causing the oc_pg por t assertion, if the indicator is still active. if the indicator is not active , the host processor is able to track what has caused the oc_pg port assertion through the event registers. the status indicators causing the assertion of the oc_pg port are repor ted in the following list: not buck power good over current alarm warning temperature vbuck_max voltage gpi status when a status bit is set , the oc_pg signal is asserted, unless the related bit is masked in mask_a and mask_b registers. an event is produced in parallel when the status bit changes from passive to active state. the oc_pg port is automatically released when no status indicators are active . the event bit remains asserted and needs to be cleared by the host processor. when en_chip is low , the oc_ pg port is configured in high impedance state. when en_chip is high and the buck converter is disabled , the oc_pg port is configured to its passive state. th erefore if it is set as open - drain , active low i n config_a reg ister, a pull - up resistor will be required to achieve a high level on the oc_pg port. when disabling the buck converter, if oc_pg_rel = 0 , the oc_pg port is held asserted during power down for t oc_pd after the buck has been disabled. when this time expires , the oc_pg port will be released to its passive state. if oc_pg_rel = 1 , the oc_pg port is held asserted during power down until the down ramp has completed. after that it will be immediately released to its passive state. not buck power good this channel monitors the output voltage of the buck converter and signals an invalid output voltage condition. during power up , the npwrgood indicator is active and is released when the buck output voltage is greater than vgood. during normal operation, the npwrgood indicator is active when the buck output voltage falls below vgood C vgood _ hyst. the indicator is released when the buck output voltage returns above vgood. over current alarm thi s channel monitors the peak current through the pass devices of the buck converter. the indicator is active as long as the b uck_ialarm threshold is hit. this is a pre - warning level information for the host processor. the control oc_pg_mask can be used to mask the assertion of oc_pg due to current alarm during the dvc transition of the buck converter until the power up has completed. if oc_pg_keep control bit is asserted, the ove r current alarm channel is masked for 100 s after the power good condition has been reached, in other words, after the buck rail is valid. this happens when recovering from an out of range condition and during power up of the buck converter. when trigger ed due to an over current condition, the oc_pg port is asserted within t oc_del thereby ensuring fast feedback of information to the host processor.
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 41 of 90 ? 2016 dialog semiconductor after being asserted due to over current, the oc_pg port will be released at least t oc_assert after the cur rent has reduced below the b uck_ialarm threshold. this ensures that very short current spikes triggering the oc_pg will produce pulses with defined minimum width , thereby allowing the host processor to react and take counter - measures . over current alarm is valid only in pwm m ode. when the b uck is operated in pfm mode or auto m ode, the m_ovcurr bit should be set. warning temperature this channel monitors the die temperature of DA9210 and the indicator becomes active as soon as the temp_warn threshold is hit. this is pre - warning level information for the host processor. the indicator returns to inactive onl y after the die temperature has fallen below temp_warn C temp_hyst. vbuck_max v oltage this channel monitors the output voltage configured for the buck converter either via dedicated dvc interface (see status register vbuck_dvc ) or via the vbuck_a and vbuck_b registers. the indicator is active as long as the configured output voltage is greater than or equal to vbuck_max. gpi t oggling and e xternal c h arger p lugged to extend the oc_pg functionality, if additional external inputs need to be monitored and their activity needs to be combined on the oc_pg, all DA9210 gpios can be configured to trigger the assertion of oc_pg port if they are configured as gpi and not overridden by any alternative function or masked. if gpio1, gpio2 and gpio3 are used for dual parallel mode operation ( gpio1_pin = 01, gpio2_pin = 01, gpio3_pin = 01), the configuration of these pins is ignored and no signalling on the oc_pg port is possible. gpio4 is assigned for dedicated communication of a n external charger connection signal. if not masked , it asserts when the charger is disconnected from the system. for this purpose , gpio4 must be configured as gpi, active low. if gpio5 and gp io6 are used as interface ports ( g pio5_pin = 01, gpio6_pin = 01) , the configuration of th e se pins is ignored and no signalling on the oc_pg port is possible. if configured for hw control of the switching regulator, gpio0, gpio 3 or gpio 4 will no t assert oc_pg when their status is active.
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 42 of 90 ? 2016 dialog semiconductor figure 32 : configuration of oc_pg p in f unctionality
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 43 of 90 ? 2016 dialog semiconductor figure 33 : oc_pg t iming d iagram ( config_a = 0x16)
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 44 of 90 ? 2016 dialog semiconductor 8.3 DA9210 o perating m od es 8.3.1 on m ode DA9210 is in on m ode when the en_chip port is higher than en_on. once enabled, the host processor can start communication with DA9210 via c ontrol i nterface after the t en delay needed for internal circuit start - up . if buck_en is asserted when DA9210 is in on m ode , the power up of the buck converter is initiated. if the buck is controlled via gpi (see buck_gpi , vbuck_gpi ) , the level of the controlling ports is checked when entering on mode, so that an active will immediately affects the buck. if buck_en is not asserted and all controlling gpi ports are not active, the buck converter remains off with output pull - down resistor e nabled or disabled according to buck_pd_dis bit . 8.3.2 off m ode DA9210 is in off m ode when the en_chip port is lower than en_off. in off m ode, t he buck is always disabled and the output pull - down resistor is disabled independently of buck_pd_dis . all i/o ports of DA9210 are configu red to be high impedance. 8.3.3 dual p arallel m ode DA9210 is capable of delivering up to 24 a for a high current cpu supply, when operated in dual parallel mode. two instances of DA9210 are needed with parallel connection of vdd and output node, one acting as master and one as slave (see figure 34 ). a DA9210 slave is identified by the connection of vout_sense p in to vddcore, whilst a master has the vout_sense p in in the normal output voltage operational range. a suitable built in filter avoids noise or short spikes on the vout_sense line causing the wrong operatin g mode to be sensed . to operate in dual parallel mode, both master and slave instances of DA9210 must have gpio1, gpio2 , and gpio3 configured respectively as v error , i phase , buck_clk i n the gpiox_pin control field. the configuration of DA9210 in dual parallel mode is transparent to t he host processor and does not require any extra effort in terms of register write and maintenance . only the master device is visible to the host processor. all commands are sent via the c ontrol i nterface by the host processor into the master. in slave mod e , DA9210 will not react to any read command from the c ontrol i nterface. please contact your local dialog semiconductor support for more information and dedicated application not e on the dual parallel mode.
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 45 of 90 ? 2016 dialog semiconductor figure 34 : dual paralle l mode c onfiguration
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 46 of 90 ? 2016 dialog semiconductor 8.4 gpio e xtender DA9210 includes a gpio extender that offers up to seven 5 v tol erant , gpio ports; each controlled via registers from the host processor . the gpio ports are pin - shared with the c ontrol i nterface, dvc interface, and dual operation. for instance, if g pio5_pin = 01, gpio6_pin = 01 (interface selected), the gpio5 and gpio6 ports will be exclusively dedicated to chip select and output signa l ling for 4 - wire purposes or to clock and input for dvc interface, depending on the setting of if_type . if the alternat e function is selected, all gpio configuration s as per registers 0x58 to 0x5a and 0x145 will be ignored. gpis are supplied from the internal rail vddcore or vdd_io (selected via gpi_v and can be configured to be active high or active low in gpiox_type. the input signals can be debounced (debouncing time configurable via control debouncing , 10 ms default) can directly change the state of the as signed status register gpix to high or low, dependent on the setting of gpiox_mode. if oc_pg_irq_conf = 1, as long as the status is at its configured active state (level sensitive), the oc_pg port is asserted (unless this is masked, see also figure 32 ). whenever the status changes to the active state (edge sensitive) , the assigned event register is set (needs to be cleared by the host processor). if oc_pg_irq_conf = 0, whenever the status changes to its configured active state (edge sensitive) , the assigned event register is set and the nirq signal is asserted (unless th e nirq is masked, see figure 35 ). whenever DA9210 is enabled and enters on mode (also when enabled , changing the setting of gpiox_pin) , the gpi status bits are initiated towards their configured passive state. this ensures that already active signals are detected and create an even t immediately after the gpi comparators are enabled. if enabled via buck control buck_gpi , port gpi0, gpi 3 and gpi 4 enable/disable the switching regulator from the rising and falling edges of th ese signals (chang ing buck_en ). if gpi ports must be enables for hw control of the switching regulator , do not generate an event and do not assert oc_pg independently of the oc_pg_irq_conf setting, the relative mask bit should also be set . gpi0 , gpi 3 and gpi 4 can alternatively be selected to toggle the buck_sel bit with rising and falling edges at th ese inputs. in addition to changing the regulator output voltage this also provides a hw control of regulator mode (normal/low power mode) from the settings buck_sl_a , buck_sl_b (enabled via buck_mode = 00). all gpi ports have the additional option of activating a 100 k? pull - down resistor via gpiox_pupd, which ensures a well - defined level in case the input is not actively driven. if defined as an output , gpios can be configured to be open - drain or push - pull. the supply rail in case of push - pull is vdd_io. by disabl ing the internal 120 k? pull - up resistor in open - drain mode , the gpo can also be supplied from an external rail. the output state will be determined by the gpio register bit gpiox_mode. whenever the gpio unit is off (por or off m ode) , all ports are configu red as open - drain active high (pass device switched off, high impedance state). when leaving por , the pull - up or pull - down resistors are configured from register config_c
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 47 of 90 ? 2016 dialog semiconductor figure 35 : gpio p rin cipal b lock d iagram with nirq s ignal (example paths)
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 48 of 90 ? 2016 dialog semiconductor 8.5 control i nterfaces the DA9210 can be sw - controlled by the host. the DA9210 offers access to its registers via a serial control interface. the communication is selectable to be either a 2 - wire (i 2 c compliant) or a 4 - wire (spi compliant) connection via control if_type which is selected during the initial otp read. in both configurations , the DA9210 will act as a slave device, d ata is shifted into or out from DA9210 under the control of t he host processor that also provides the serial clock. the interface is usually only configured once from otp values, which are loaded during the initial start - up of DA9210 . note DA9210 reacts only on read/w rite commands w here the transmitted register address (using the actual page bits as a n msb address range extension) is w ithin 0x50 to 0x6f, 0xd0 to df, 0x140 to 0x14f , or (read only) 0x200 to 0x280. host access to registers outside these range s w ill be ignored (no acknow ledge after receiving the register address in 2 - wire m ode, so stays hi - z in 4 - wire m ode). DA9210 react s only to w rite commands w here the transmitted register address is 0x00, 0x80, 0x100, 0x101, 0x105, 0x106 , or 0x200. if stand_alone is asserted (otp bit), DA9210 also react s t o read commands . if DA9210 is in slave configuration (vout_sense ti ed to vddcore) it does not react to any read command , see section 8.3.3 . DA9210 provides an additional interface supporting direct dvc requests from the host processor to the buck . the dvc interfac e can be enabled via control dvc_ctrl_en, provided that the gpio5_pin, gpio6_pin , and if_type controls are appropriately configured. 8.5.1 4 - wire c ommunication in 4 - wire m ode , the interface uses a chip - select line (ncs/nss), clock line (sk), data input (si) , a nd data output line (so). the DA9210 register map is split into four pages with each page containing up to 128 registers, in order to be transparent to the main pmic (da9063) an d compliant to its register map. the register at address 0x00 on each page is used as a page control register. the default active page after turn on includes registers 0x50 to 0x6f. writing to the page control register changes the active page for all subse quent read/write operations unless an automatic return to page 0 was selected by asserting control revert . unless revert was asserted , after modifying the active page it is recommended t o read back the page control register to ensure that future data exchange is accessing the intended registers. all registers out of the DA9210 range are write only that is the DA9210 will not answer to a read command and the data bus is tri - state (they are implicitly directed to da9063). in particular , the information contained in registers 0x105 and 0x1 06 is used by DA9210 to configure the control interface. they must be the same as the main pmic (da9063), so that a write to those registers configures both the main pmic and DA9210 . the default otp settings need also to be identical for correct operation of the system. the 4 - wire interface features half - duplex operation (data can be transmitted and rece ived within a single 16 bit frame) at an enhanced clock speed (up to 14 mhz). the interface operates at the clock frequenc y provided by the host .
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 49 of 90 ? 2016 dialog semiconductor a transmission begins when initiated by the host. reading and writing is accomplished using an 8 - bit command, sent by the host prior to the exchanged 8 - bit data. the byte from the host begins shifting in on the si pin under the control of the serial clock sk provided from the host. the first 7 bits specify the register address (0x01 to 0x07) which will be written or read by the host. the register address is automatically decoded after receiving the seventh address bit. the command word ends with an r/w bit, this, together with the control bit r/w_pol , specifies the direction of t he following data exchange. during a register writ e , the host continues sending out data during the following eight sk clocks. for a read , the host stops transmitting and the 8 - bit register is clocked out of DA9210 during the following eight sk clocks of the frame. address and data are transmitted msb first. the polarity (active state) of ncs is defined by control bit ncs_pol . ncs resets the int erface when inactive and must be released between successive cycles. the so output from DA9210 is normally in a high - impedance state and is active only during the second half of a read cycle. a pull - up or pull - down resistor may be needed on the so line if a floating logic signal c ould result in unintended current consumption inside other circuits. the da9 210 4 - wire interface offers two further configuration bits. clock polarity ( cpol ) and clock phase ( cpha ) define when the interface will latch the serial data bits. cpol determines whether sk idles high ( cpol = 1) or low cpol = 0). cpha determines on which sk edge data is shifted in and out. with cpol = 0 and cpha = 0 , DA9210 latches data on the sk rising edge. if the cpha is set to 1 , the data is latched on the sk falling edge. cpol and cpha states allow four different combinations of clock polarity and phase; each setting is incompatible with the other three. the host and DA9210 must be set to the same cpol and cpha states to communicate with each other , s ee table 15 . table 15 : 4 - wire clock configurations cpha clock polarity cpol clock phase output data is updated at sk edge input data is registered at sk edge cpha clock polarity 0 (idle low ) 0 falling rising 0 (idle l ow ) 0 (idle low ) 1 rising falling 0 (idle low ) 1 (idle high) 0 rising falling 1 (idle high) 1 (idle high) 1 falling rising 1 (idle high)
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 50 of 90 ? 2016 dialog semiconductor figure 36 : 4 - wire h ost w rite and r ead t iming ( ncs_pol = 0 , cpol = 0, cpha = 0 ) figure 37 : 4 - wire h ost w rite and r ead t iming (ncs_pol = 0, cpol = 0, cpha = 1)
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 51 of 90 ? 2016 dialog semiconductor figure 38 : 4 - wire h ost w rite and r ead t iming (ncs_pol = 0, cpol = 1, cpha = 0) figure 39 : 4 - wire h ost w rite and r ead t iming ( ncs_pol = 0, cpol = 1, cpha = 1 ) table 16 : 4 - wire interface summary param eter signal lines ncs chip select si serial input data master out slave in so serial output data master in sl ave out sk transmission clock interface push - pull w ith tristate supply voltage selected from vdd_io 1.6 v to 3.3 v
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 52 of 90 ? 2016 dialog semiconductor param eter data rage effective read/w rite data up to 7 mbps transmission half - duplex msb first 16 bit cycles 7bit address, 1 bit read/w rite, 8 bit data configuration cpol clock polarity cpha clock phase ncs_pol ncs is active low /high note 1 reading a register at high clock rates directly after w r iting to it does not guarantee a correct value. a delay of one frame is recommended before re - accessing a register that has just been w ritten ( for example by w riting/reading another register address in betw een).
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 53 of 90 ? 2016 dialog semiconductor 8.5.2 2 - wire c ommunication with control if_type , the DA9210 power manager interface can be configured towards a 2 - wire serial data exchange. it has a configurable device write address (default : 0xd0) and a configurable device read address (default: 0xd1). for details of configurable addresses , see control if_base_addr . the sk pin provides the 2 - wire clock (scl), and si carries all the power manager bidir ectional 2 - wire data , ( sda) . the 2 - wire interface is open - drain supporting multiple devices on a single line. the bus lines require external pull - up resistors (2 k? to 20 k? range). the attached devices only drive the bus lines low. as a result , two devices cannot conflict if they drive the bus simultaneously. in standard/fast mode , the highest frequency of the bus is 400 khz . th e exa ct frequency can be determined by the application and does not have any relation to the DA9210 internal clock signals. DA9210 follow s the host clock speed within the described limitations and does not initiate any clock arbitration or slow down. an automatic reset of the interface can be triggered via control 2wire_to if the clock signal stops toggl ing f or more than 35 ms (compatible with smbus). the interface supports operation compatible with standard, fast, fast - plus and high speed mode s of the i2c bus specification rev 4 (um10204_4). operation in high speed mode at 3.4 mhz requires mode changing in or der to change spike suppression and slope control characteristics to be compatible with the i2c bus specification. the high speed mode can be enabled on a transfer by transfer basis by sending the master code (0000 1xxx) at the begin n ing of the transfer. DA9210 does not make use of clock stretching and delivers read data up to 3.4 mhz, without additional delay . communication on the 2 - wire bus always takes place between two devices , one acting as the master and the other as the slave. the DA9210 only operates as a slave . unlike 4 - wire mode , the 2 - wire interface has direct access to two pages of the r egist er map (up to 256 addresses). the register at address 0x00 on each page is used as a page control register (with the 2 - wire bus ignoring the lsb of control reg_page ). writing to the page control register changes the act ive page for all subsequent read/write operations , unless an automatic return to page 0 is selected by asserting control revert . after modifying the active page, unless revert is asserte d , it is recommended to read back the page control register to ensure that future data exchange accesses the intended registers. in 2 - wire operation DA9210 offers an alternative way to access register page 2 and 3. it removes the need for the preceding page selection writes by increasing the device write/read address by one (default 0xd2/0xd3) for any direct access of page 2 and 3 (page 0 and 1 access requires the basic write/read device address with the msb of reg_page 0). details of the 2 - wire c ontrol b us p rotocol the following description uses the standard terms sda for the serial data, pin si , and scl for the serial clock, pin sk. all data is transmitted across the 2 - wire bus in 8 - bit groups. to send a bit, the sda line is driven at the intended state while the scl is low. once the sda has settled, the scl line is brought high and then low. this pulse on scl stores the sda bit in the receiv ers shift register. a 2 - byte serial protocol is used: one address byte and one data byte. the data and address are transmitted msb first for both read and write operations. all transmissions begin with the start condition from the master , during which the bus is in idle state (the bus is free). it is initiated by a high - to - low transition on the sda line while the scl is in high state. a stop condition is indicated by a low - to - high transition on the sda line while the scl is in high state. the start and sto p conditions are illustrated in figure 40 .
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 54 of 90 ? 2016 dialog semiconductor figure 40 : timing of the start and stop c onditions DA9210 monitors the 2 - wire bus for a valid slave address whenev er the interface is enabled. it responds immediately when it receives its own slave address. this is acknowledged by pulling the sda line low during the following clock cycle (white blocks marked with a in the following figures). the protocol for a regis ter write from master to slave consists of a start condition, a slave address, a read/write - bit, 8 - bit address, 8 - bit data, and a stop condition. DA9210 responds to all bytes with an ack. a register write operation is illustrated in figure 41 . figure 41 : byte w rite o peration when the host reads register data , the DA9210 first has to access the target register address with write access and then with read access and a repeated start, or alternatively a second start, condition. after receiving the data, the host sends nack and terminates the transmission with a stop condition, see figur e 42 . figur e 42 : examples of by te r ead o perations consecutive (page) read - out mode is initiated from the master by sending an ack instead of nack after receiving a byte, see figure 43 . the 2 - wire cont rol block then increments the address pointer to the next register address and sends the data to the master. the data bytes are read continuously until the master sends a nack followed by a subsequent stop condition directly after receiving the data. if a non - existent 2 - wire address is read out , then the DA9210 return s code zero. s t a r t s t o p s d a s c l t r a n s a c t i o n slaveadr w regadr a data a p s = start condition a = acknowledge ( low) p = stop condition w = write (low) master to slave slave to master 7 - bits 1 - bit 8 - bits 8 - bits a s s slaveadr w a regadr a slaveadr a s = start condition a = acknowledge ( low) sr = repeated start condition a * = no a cknowledge p = stop condition w = write (low) r = read (high) master to slave 7 - bits 1 - bit 8 - bits 7 - bits data a * sr r 1 - bit 8 - bits slaveadr a 7 - bits data p s r 1 - bit 8 - bits p a * slave to master s slaveadr w a regadr p 7 - bits 1 - bit 8 - bits a
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 55 of 90 ? 2016 dialog semiconductor figure 43 : 2 - w ire p age r ead the slave address after the repeated start condition must be the same as the previous slave addres s. consecutive (page) write mode is supported if the master sends several data bytes after sending the register address. the 2 - wire control block then increments the address pointer to the next 2 - wire address, stores the received data, and sends an ack unt il the master sends a stop condition. the page write mode is illustrated in figure 44 . figure 44 : 2 - w ire p age w rite a repeated write mode can be enabled with writ e_mode control. in this mode, the master can execute back - to - back write operations to non - consecutive addresses by transmitting register addresses and data pairs. the data is stored in the address specified by the preceding byte. the repeated write mode is illustrated in figure 45 . figure 45 : 2 - w ire r epeated w rite if a new start or stop condition occurs within a message, the bus returns to idle mode. 8.5.3 dvc i nterface with control dvc_ctrl_en , gpio5 and gpio6 can be dedicated to an alternative mode of defining the buck output voltage (supporting direct dvc) from the host processor to the buck. this is only enabled if gpio 5 and gpi o6 are configured for i nterface (setting 01) and if_type is asserted. since the logical levels of the i/o are referenced to vdd_io, a valid voltage at this port is needed. after the dvc interface has been activated and s ynchroni z ed, the buck converter target voltage is derived by adding a delta value to the voltage base register configured in vbuck_base . the delta value is decoded by DA9210 from the number of clock rising edges at the sync pin while input is s slaveadr w a regadr a slaveadr a s = start condition a = acknowledge (low) sr = repeat start condition a * = no acknowledge p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 7 - bits data a sr r 1 - bit 8 - bits s slav eadr w a regadr a slaveadr a 7 - bits 1 - bit 8 - bits 7 - bits data p s r 1 - bit 8 - bits p a a * p data data a a * data 8 - bits 8 - bits 8 - bits s sla veadr w a regadr a data a s = start condition a = acknowledge (low) sr = repeat start condition a * = no acknowledge p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 8 - bits data a 1 - bit 8 - bits a p data . a 8 - bits repeated writes s sla veadr w a regadr a data a s = start condition a = acknowledge (low) sr = repeat start condition a * = no acknowledge p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 8 - bits regadr a 1 - bit 8 - bits a p data . a 8 - bits repeated writes
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 56 of 90 ? 2016 dialog semiconductor kept high. during control via the dvc interface, the setting of registers vbuck_a , vbuck_b are ignored and the target output voltage is calculated as: v out = v buck_base + (n x v steps ) where v vsteps is 10 mv and n can range from 0 to 32. t he principle derivation of the target voltage is shown in figure 46 . e xample t he input port is sampled high for 16 of the 32 samples, thus n = 16. if v buck_base = 0.8 v, the target voltage is v out = 0.8 v + (16 x 10 mv) = 0.96 v. once the dvc interface is enabled, DA9210 will maintain the voltage set in vbuck_a / vbuck_b until the valid completion of the first 32 clock sample . the new value of the output voltage is automatically updated after the completion of 32 clock sample. the clocking sync signal can be stopped after a multiple of 32 cycles or it can run continuously. the value used for setting the target voltage is always based on the last 32 clock sample frame . there is no explicit frame sync signal. once the dvc interface is enabled, the frame sync is implicit on the rising edge of the input port, which indicates the start of a 32 clock frame. if a new rising edge occurs before the previous 32 clocks have been sampled, the current accumulated sample is discarded and a new 32 clock sample is started. the previous voltage setting for the buck converter is used as target in the meantime, until a valid sequence is decoded. i f a zero value is sent to the input port, v out will be equal to v buck_base so there is no rising edge and thus no frame sync. DA9210 will keep counting the clock edges at the sync port . in a similar way, i f a high value is continuously sent t o the input port, v out will be equal to v buck_base + (32 x v steps ) although no frame sync takes place. the host processor can monitor the configured target voltage on the (read only) register vbuck_dvc . the dvc interface is interrupted when dvc_ctrl_en is released or the if_type / gpi 4/gpio5 configuration is changed. after disabling the dvc interface , the normal control of t he output voltage via select register vbuck_a , vbuck_b will revert automatically. if force_dvc_if i s not asserted, the dvc interface is disable d when the buck is disabled (this automatically clears dvc_ctrl_en bit). otherwise the dvc interface remain s armed and , at the next enable of the buck converter , the target output value will be derived from the sync and input ports, as soon as a valid completion of the first 32 clock sample take s place. until a valid 32 clock sample is received , the output voltage is set via select register buck_sel and vbuck_a or vbuck_b values . if dvc_step_size is asserted the output voltage will increase by double the amount of consecutive asserted bits ( v vsteps will correspond to 20 mv instead of 10 mv) . example t he in put port is sampled high for 16 of the 32 samples, thus n = 16. if dvc_step_size is asserted and v buck_base = 0.8 v, the target voltage is v out = 0.8 v + (16 x 20 mv) = 1.12 v. to limit the buck output voltage and p revent any failures in case of a communication error, a maximum value for the buck output target voltage can be stored in vbuck_max. this value represents the absolute maximum voltage and it has priority over any value resulting from the addition of v buck_ base and (n x v steps ) as well as over any value set on vbuck_a and vbuck_b , if the dvc interface is disabled. when the output voltage exceeds vbuck_max , an event is generated and the o c_pg port is asserted, if not masked by m_vmax. if the oc_pg port is configured for irq operation, an interrupt is generated instead.
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 57 of 90 ? 2016 dialog semiconductor figure 46 : dvc control interface
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 58 of 90 ? 2016 dialog semiconductor 8.6 internal t emperature s upervision to protect the DA9210 from damage due to excessive power dissipation , the internal temperature is contin u ously monitored. there are three temperature thresholds, temp_warn, temp_crit , and temp_por, respectiv ely at typically 125 c, 140 c , and 150 c. when the junction temperature reaches the temp_warn threshold, DA9210 assert s the bit temp_warn and generate s the event e_temp_warn . if not masked via bit m_temp_warn , the output port oc_pg/nirq is asserted. the status bit temp_warn remain s asserted while the junction temperature is higher than temp_warn. when the junction temperature increases further over temp_crit , the DA9210 immediately disable s the buck converter, assert s the bit temp_crit and generate s the event e_temp_warn . i f not masked via bit m_temp_warn , the output port oc_pg/nirq i s asserted. the status bit temp_crit remain s asserted while the junction temperature is higher than temp_crit. the buck converter is disabled as long as the junction temperature is greater than temp_crit and is automat ically re - enabled after the temperature recover s below the valid threshold (even if the controlling gpi is asserted). a direct write into buck_en or a toggling of the controlling gpi is needed to enable the buck converte r . whenever the junction temperature exceeds temp_por, a power - on reset to the digital core is immediately asserted, which stops all functionali ty in DA9210 . this is needed to pr event possible permanent damage in case of a fast temperature increase.
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 59 of 90 ? 2016 dialog semiconductor 9 register d efinitions 9.1 register m ap all bits loaded from otp are marked in bold . figure 47 : register map
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 60 of 90 ? 2016 dialog semiconductor 9.2 register p age c ontrol table 17 : page_con (0x00) bit type label description 7 r/w revert resets reg_pa ge to 000 after read/w rite access has finished 6 r/w write_mode note 1 2 - wire multiple w rite mode 0: page write m ode 1: repeated write m ode 5:3 r/w ( r eserved) 2 :0 r/w reg_page i 2 c: 00x: selects r egister 0x0 0 to 0x f f 01x: selects r egister 0x10 0 to 0x1 7 f spi: 000: selects r egister 0x0 0 to 0x 7 f 001: selects register 0x80 to 0x f f 100: selects r egister 0x 1 0 0 to 0x 17 f >010: reserved for production and test note 1 not used for 4 - wire - if 9.3 register p age 0 9.3.1 system c ontrol and e vent the status registers report the current value of the various signals at the time th at it is read out. note all the status bits have the same polarity as their corresponding signals. table 18 : page_con (0x50) bit type label description 7 r r eserved 6 r gpi6 gpi6 level 5 r gpi5 gpi5 level 4 r gpi4 gpi4 level 3 r gpi3 gpi3 level 2 r gpi2 gpi2 level 1 r gpi1 gpi1 level 0 r gpi0 gpi0 level
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 6 1 of 90 ? 2016 dialog semiconductor table 19 : status_b (0x51) bit type label description 7:5 r r eserved 4 r vmax asserted as long as the voltage configured for the buck converter is equal or greater than vbuck_max 3 r temp_crit asserted as long as the thermal shutdow n threshold is reached 2 r temp_wa rn asserted as long as the thermal w arning threshold is reached 1 r npwrgood asserted as long as the buck output voltage is out of range 0 r ovcurr asserted as long as the buck is in overcurrent the event registers hold information about events detected by the DA9210 . if the oc_pg port is configured as irq line: the events are triggered by a change in the status register which contains the status of monitored signals. w hen an event bit is set in the event register the irq signal shall be asserted, unless the event is masked by setting the associated bit in the mask register . t he irq triggering event register is cleared from the host by writing back its read value. new events occurring during clearing is delayed before they are passed to the event register, ensuring that the host controller does not mi ss them. if the oc_pg port is configured for dedicated communication to the host processor as described in section 8.2.8 , the port will be asserted according to the status bits and the polarity of the status ind ication (active high/low) can be selected separately (see gpioxx_type control). an event is generated only during transition of the status from inactive to active. table 20 : event_a (0x52) bit type label description 7 r r eserved 6 r e_gpi6 gpi6 event according to active state setting 5 r e_gpi5 gpi5 event according to active state setting 4 r e_gpi4 gpi4 event according to active state setting 3 r e_gpi3 gpi3 event according to active state setting 2 r e_gpi2 gpi2 event accord ing to active state setting 1 r e_gpi1 gpi1 event according to active state setting table 21 : event_b (0x053) bit type label description 7:5 r r eserved 4 r e_vmax vmax caused event 3 r e_temp_crit temp_crit caused event 2 r e_temp_wa rn temp_wa rn caused event 1 r e_npwrgood npwrgood caused event
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 62 of 90 ? 2016 dialog semiconductor bit type label description 0 r e_ovcurr ovcurr caused event table 22 : mask_a (0x54) bit type label description 7 r/w r eserved 6 r/w m_gpi6 gpi6 nirq mask 5 r/w m_gpi5 gpi5 nirq mas k 4 r/w m_gpi4 gpi4 nirq mask 3 r/w m_gpi3 gpi3 nirq mask 2 r/w m_gpi2 gpi2 nirq mask 1 r/w m_gpi1 gpi1 nirq mask 0 r/w m_gpi0 gpi0 nirq mask table 23 : mask_b (0x55) bit type label description 7:5 r/w r eserved 4 r/w m_vmax vmax nirq / oc_pg event mask 3 r/w m_temp_crit mask temp_crit nirq / oc_pg event mask 2 r/w m_temp_warn temp_wa rn nirq / oc_pg event mask 1 r/w m_npwrgood pwrgood nirq / oc_pg event mask 0 r/w m_ovcurr ovcurr irq / oc_pg event mask table 24 : control_a (0x56) bit type label description 7 r/w r eserved 5 r/w v_lock 0: allow s host w rites into registers 0xd0 to 0x14f 1: disables register 0xd0 to 0x14f re - programming from control interfaces 4:3 r/w slew_rate dvc slew ing is execut ed at 00: 10 mv every 4.0 s 01: 10 mv every 2.0 s 10: 10 mv every 1.0 s 11: 10 mv every 0.5 s
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 63 of 90 ? 2016 dialog semiconductor bit type label description 2:0 r/w debouncing gpi debounce time: 000: no debounce time 001: 0.1 ms 010: 1.0 ms 011: 10 ms 100: 50 ms 101: 250 ms 110: 500 ms 111: 1000 ms 9.3.2 gpio c ontrol table 25 : g pio0 - 1 (0x 58) bit type label description 7 r/w gpio1_mode 0: gpi: debounce off gpo: sets output to low level 1: gpi: debounce on gpo: sets output to high level 6 r/w gpio1_ty pe 0: gpi: active low 1: gpi: active high 5: 4 r/w gpio1_pin pin assigned to: 00: gpi 01: verror signal 10: gpo ( o pen - drain) 11: gpo ( p ush - pull) 3 r/w gpio0_mode 0: gpi: debounce off gpo: sets output to low level 1: gpi: debounce on gpo: sets output to high level 2 r/w gpio0_ty pe 0: gpi: active low 1: gpi: active high 1:0 r/w gpio0_pin pin assigned to: 00: gpi 01: reserved 10: gpo ( o pen - drain) 11: gpo ( p ush - pull)
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 64 of 90 ? 2016 dialog semiconductor table 26 : gpio2 - 3 (0x59) bit type label description 7 r/w gpio3_mode 0: gpi: debounce off gpo: sets output to low level 1: gpi: debounce on gpo: sets output to high level 6 r/w gpio3_ty pe 0: gpi: active low 1: gpi: active high 5:4 r/w gpio3_pin pin assigned to: 00: gpi 01: buck_clk signal 10: gpo ( o pen - drain) 11: gpo ( p ush - pull) 3 r/w gpio2_mode 00: gpi: deboun ce off gpo: sets output to low level 1: gpi: debounce on gpo: sets output to high level 2 r/w gpio2_ty pe 0: gpi: active low 1: gpi: active high 1:0 r/w gpio2_pin pin assigned to: 00: gpi 01: iphase signal 10: gpo ( o pen - drain) 11: gpo ( p ush - pull) table 27 : gpio4 - 5 (0x54) bit type label description 7 r/w gpio5_mode 0: gpi: debounce off gpo: sets output to low level 1: gpi: debounce on gpo: sets output to high level 6 r/w gpio5_ty pe 0: gpi: active low 1: gpi: active high 5:4 r/w g pio5_pin pin assigned to: 00: gpi 01: interface 10: gpo (open - drain) 11: gpo (push - pull) 3 r/w gpio4_mode 0: gpi: debounce off gpo: sets output to low level 1: gpi: debounce on gpo: sets output to high level 2 r/w gpio4_ty pe 0: gpi: active low 1: gpi: ac tive high
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 65 of 90 ? 2016 dialog semiconductor bit type label description 1:0 r/w gpio4_pin pin assigned to: 00: gpi (ac_ok) 01: digital external clock input 10: gpo (open - drain) 11: gpo (push - pull) table 28 : gpio6 (0x5b) bit type label description 7 :4 r/w reserved 3 r/w gpio6_mode 0: gpi: debounce off gpo: sets output to low level 1: gpi: debounce on gpo: sets output to high level 2 r/w gpio6_ty pe 0: gpi: active low 1: gpi: active high 1:0 r/w gpio6_pin pin assigned to: 00: gpi 01: interface 10: gpo (open - drain) 11: gpo (push - pull) 9.3.3 r egul ator c ontrol table 29 : buck_con (0x5d) bit type label description 7 r/w dvc_ctrl_en main control of the dedicated dvc interface: 0: disabled 1: enabled 6:5 r/w vbuck_gpi gpio select target voltage vbuck_b on passive to active tran sition, selects target voltage vbuck_a on active to passive transition (ramping) 00: not controlled by gpio 01: gpio0 controlled 10: gpio3 controlled 11: gpio4 controlled 4 r/w vbuck_sel note 1 buck voltage is selected from (ramping): 0: vbuck_a 1: vbuck_b 3 r/w buck_pd_dis 0: enable pull - dow n resistor in disabled mode 1: no pull - dow n resistor in disabled mode
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 66 of 90 ? 2016 dialog semiconductor bit type label description 2:1 r/w buck_gpi gpio enables the buck on passive to active state transition, disables the buck on a ctive to passive state transition 00: not controlled by gpio 01: gpio0 controlled 10: gpio3 controlled 11: gpio4 controlled 0 r/w buck_en 0: buck disabled 1: buck enabled note 1 automatically set to 0 by default w hen the buck converter is enabled, except w hen t he output voltage is controlled via gpi port .
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 67 of 90 ? 2016 dialog semiconductor 9.4 register p age 1 table 30 : p age_con (0x 80) bit type label description 7 r/w revert resets reg_pa ge to 000 after read/w rite access has finished 6 r/w write_mode note 1 2 - wire multiple w rite mode 0: page w rite m ode 1: repeated w rite m ode 5: 3 r/w r eserved 2:0 r/w reg_page i 2 c: 00x: selects r egister 0x0 0 to 0x f f 01x: selects r egister 0x10 0 to 0x1 7 f spi: 000: selects r egister 0x0 0 to 0x 7 f 001: selects register 0x80 to 0x f f 100: selects r egister 0x 1 0 0 to 0x 17 f >010: reserved for production and test note 1 not used for 4 - wire - if . 9.4.1 regulators s ettings table 31 : buck_ilim (0xd0) bit type label description 7:5 r/w r eserved 4 r/w b uck_ialarm current alarm threshold is: 0: buckilim C 300 ma 1: buckilim C 600 ma
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 68 of 90 ? 2016 dialog semiconductor bit type label description 3:0 r/w buck_ilim current limit per phase: 0000: 1600 ma 0001: 1800 ma 0010: 2000 ma 0011: 2200 ma 0100: 2400 ma 0101: 2600 ma 0110: 2800 ma 0111: 3000 ma 1000: 3200 ma 1001 : 3400 ma 1010: 3600 ma 1011: 3800 ma 1100: 4000 ma 1101: 4200 ma 1110: 4400 ma 1111: 4600 ma table 32 : buck_conf1 (0xd1) bit type label description 7:5 r/w pwr_down_ctrl voltage ramping during pow er dow n 000: 1.25 mv/s 001: 2.5 mv/s 010: 5 mv/s 011: 10 mv/s 100: 20 mv/s 101: 30 mv/s 110: 40 mv/s 111: no ramped pow er dow n 4:2 r/w startup_ctrl voltage ramping during start - up 000: 1.25 mv/s soft startup w ith controlled slew rate 001: 2.5 mv/s 010: 5 mv/s 011: 10 mv/s 100: 20 mv/s note 1 101: 30 mv/s 110: 40 mv/s 111: target voltage applied immediately (no soft start) 1:0 r/w buck_mode 00: low pow er/normal mode controlled via voltage a and b registers 01: buck alw ays operates in low pow er mode 10: buck alw ays operates in normal mode 11: automatic mode
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 69 of 90 ? 2016 dialog semiconductor note 1 settings higher than 20 mv/s may cause significant overshoot table 33 : buck_conf2 (0xd2) bit type label description 7:5 r/w reserved 4 r/w auto_def t he buck automatic mode functions: 0: based on the voltage threshold vbuck_auto 1: based on the output current load 3 r/w ph_sh_en enable current dependent phase shedding during normal mode 2:0 r/w phase_sel phase selection of the multi - phase buck in sync hronous mode: 000: 1 phase is selected 001: 2 phases are selected 010: 3 phases are selected (uneven 0/90/180 phase shift) 011: 4 phases are selected 1xx: 8 phases are selected (dual mode only) table 34 : vbuck_auto (0xd4) bit type label description 7 r/w reserved 6:0 r/w vbuck_auto threshold voltage for the automatic mode: 0000000: 0.30 v 0000001: 0.31 v 0000010: 0.32 v 1000110: 1.0 v 1111101: 1.55 v 1111110: 1.56 v 1111111: 1.57 v table 35 : vbuck_ba se (0 xd 5) bit type label description 7 r/w reserved
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 70 of 90 ? 2016 dialog semiconductor bit type label description 6:0 r/w vbuck_base sets the base voltage for the buck output w hen using the dvc interface 0000000: 0.30 v 0000001: 0.31 v 0000010: 0.32 v 1000110: 1.0 v 1111101: 1.55 v 1111110: 1.56 v 1111111: 1. 57 v table 36 : vbuck_max (0xd6) bit type label description 7 r/w reserved 6:0 r/w vbuck_max sets the maximum voltage allow ed for the buck output voltage 0000000: 0.30 v 0000001: 0.31 v 0000010: 0.32 v 1000110: 1.0 v 1111101 : 1.55 v 1111110: 1.56 v 1111111: 1.57 v table 37 : vbuck_dvc (0xd7) bit type label description 7 r reserved 6:0 r vbuck_dvc internal status of actual target voltage configured via dvc interface 0000000: 0.30 v 0000001: 0.31 v 0 000010: 0.32 v 1000110: 1.0 v 1111101: 1.55 v 1111110: 1.56 v 1111111: 1.57 v
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 71 of 90 ? 2016 dialog semiconductor table 38 : vbuck_a (0xd8) bit type label description 7 r/w buck_sl_a 0: configures the buck to normal mode, w henever selecting a voltage settings 1: configures the buck to low pow er mode, w henever selecting a voltage settings 6:0 r/w vbuck_a 0000000: 0.30 v 0000001: 0.31 v 0000010: 0.32 v 1000110: 1.0 v 1111101: 1.55 v 1111110: 1.56 v 1111111: 1.57 v table 39 : vbuck_b (0xd 9) bit type label description 7 r/w buck_sl_b 0: configures the buck to normal mode, w henever selecting b voltage settings 1: configures the buck to low pow er mode, w henever selecting b voltage settings 6:0 r/w vbuck_b 0000000: 0.30 v 0000001: 0.31 v 000 0010: 0.32 v 1000110: 1.0 v 1111101: 1.55 v 1111110: 1.56 v 1111111: 1.57 v 9.5 register p age 2 table 40 : page_con (0x100) bit type label description 7 r/w revert resets reg_pa ge to 000 after read/w rite access has finished 6 r/w write_mode note 1 2 - wire multiple w rite mode 0: page write mode 1: repeated write mode 5:2 r/w r eserved
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 72 of 90 ? 2016 dialog semiconductor bit type label description 2:0 r/w reg_page 000: selects register 0x01 to 0x3f 001: selects register 0x81 to 0xcf 010: selects reg ister 0x101 to 0x1cf >010: reserved for production and test note 1 not used for 4 - wire - if 9.5.1 interface and otp s ettings (shared with da9063) table 41 : interface (0x105) note 1 bit type label descr iption 7:4 r if_base_addr 4 msb of 2 - wire control interfaces base address xxxx0000 11010000 = 0xd0 w rite address of pm 2 - wire interface (page 0 and 1) 11010001 = 0xd1 read address of pm 2 - wire interface (page 0 and 1) 11010010 = 0xd2 w rite address of pm - 2 - wire interface (page 2 and 3) 11010011 = 0xd3 read address of pm - 2 - wire interface (page 2 and 3) code 0000 is reserved for unprogrammed otp (triggers start - up w ith hardw are default interface address) 3 r r/w_pol 4 - wire: read/write bit polarity 0: host indicates reading access via r/w bit = 0 1: host indicates reading access via r/w bit = 1 2 r cpha 4 - wire if clock phase (see table 3: 4 - wire clock configurations) 1 r cpol 4 - wire if clock polarity 0: sk is low during idle 1: sk is high during idle 0 r ncs_pol 4 - wire chip select polarity 0: low , (ncs) 1: high, (cs) note 1 the interface configuration can be w ritten/modified for unmarked samples having the control otp_apps_lock not been asserted/fused. if stand_alone = 0, DA9210 w ill not respond to read commands from the host processor.
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 73 of 90 ? 2016 dialog semiconductor table 42 : interface2 (0x106) bit type label description 7 r22 if_type 0: pow er manager if is 4 - wire 1: pow er manager if is 2 - wire 6 r/w pm_if_hsm enables continuous high speed mode on 2 - wire interface if asserted (no master code required) 5 r/w pm_if_fmp enables 2 - wire interface operating w ith fast mode+ timings if asserted 4 r/w pm_if_v pow er manager if in 2 - wire mo de is supplied from: 0: vddcore 1: vdd_io (4 - wire alw ays from vdd_io) 3:0 r/w r eserved 9.5.2 application c onfiguration s ettings table 43 : config_a (0x143) bit type label description 7:5 r r eserved 4 r/w 2wire_to enables automatic reset of 2 - wire if in case of clock stays low for >35 ms 0: disabled 1: enabled 3 r/w gpi_v gpis (not configured as pow er manager control inputs) are supplied from: 0: vddcore 1: vdd_io 2 r/w oc_pg_irq_conf configuration for the oc_pg port: 0: interrupt line 1: over current and pow er good 1 r/w oc_pg_irq_ty pe oc_pg output port is: 0: push - pull 1: open - drain (requires external pull - up resistor) 0 r/w oc_pg_irq_lev el oc_pg output port is: 0: active low 1: active high
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 74 of 90 ? 2016 dialog semiconductor table 44 : config_b (0x144) bit type label description 7:0 r/w r eserved table 45 : config_c (0x145) bit type label description 7 r/w r eserved 6 r/w gpio6_pupd 0: gpi: pull - dow n resistor disabled gpo (open - drain): pull - up resistor disable d (external pull - up resistor) 1: gpi: pull - dow n resistor enabled gpo (open - drain): pull - up resistor enabled 5 r/w gpio5_pupd 0: gpi: pull - dow n resistor disabled gpo (open drain): pull - up resistor disabled (external pull - up resistor) 1: gpi: pull - dow n resi stor enabled gpo (open - drain): pull - up resistor enabled 4 r/w gpio4_pupd 0: gpi: pull - dow n resistor disabled gpo (open drain): pull - up resistor disabled (external pull - up resistor) 1: gpi: pull - dow n resistor enabled gpo (open - drain): pull - up resistor enab led 3 r/w gpio3_pupd 0: gpi: pull - dow n resistor disabled gpo (open drain): pull - up resistor disabled (external pull - up resistor) 1: gpi: pull - dow n resistor enabled gpo (open - drain): pull - up resistor 2 r/w gpio2_pupd 0: gpi: pull - dow n resistor disabled gp o (open drain): pull - up resistor disabled (external pull - up resistor) 1: gpi: pull - dow n resistor enabled gpo (open - drain): pull - up resistor enabled 1 r/w gpio1_pupd 0: gpi: pull - dow n resistor disabled gpo (open drain): pull - up resistor disabled (external pull - up resistor) 1: gpi: pull - dow n resistor enabled gpo (open - drain): pull - up resistor enabled 0 r/w gpio0_pupd 0: gpi: pull - dow n resistor disabled gpo (open drain): pull - up resistor disabled (external pull - up resistor) 1: gpi: pull - dow n resistor enabled gpo (open - drain): pull - up resistor
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 75 of 90 ? 2016 dialog semiconductor table 46 : config_d (0x146) bit type label description 7 r/w oc_pg_keep 0: normal operation of oc_pg port 1: over current alarm at oc_pg is masked for 100 s after the buck rail is valid (w hen r ecovering from an out of range condition and during pow er up) 6 r/w oc_pg_rel 0: oc_pg port is released 250 s after buck_en goes low 1: oc_pg port is released after the ramp dow n has completed 5:4 r/w oc_pg_mask over current alarm at oc_pg port is: 00: alw ays active during dvc transitions of the buck converter 01: masked during dvc transitions of the buck converter + 2 s extra masking at the end 10: masked during dvc transitions of the buck converter + 10 s extra masking at the end 11: masked during dv c transitions of the buck converter + 50 s extra masking at the end 3 r/w ready_en gpio3 is used as ready signal to inform the host processor of dvc ongoing (the gpio3 needs to be configured as output and any w rite to gpio3_mode w ill be ignored): 0: dis abled 1: enabled 2 r/w force_dvc_if 0: the dvc_ctrl_en is automatically reset w hen the buck converter is disabled 1: the dvc_ctrl_en is not reset w hen the buck converter is disabled 1 r/w dvc_step_siz e 0: v steps is configured to 10 mv w hen using the dvc interface 1: v steps is configured to 20 mv w hen using the dvc interface 0 r/w r eserved table 47 : config_e (0x147) bit type label description 7:6 r/w r eserve d 5:4 r/w osc_tune tune the main 6 mhz oscillator frequency: 00: no tu ne 01: +180 khz 10: +360 khz 11: +540 khz 3:1 r/w r eserved
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 76 of 90 ? 2016 dialog semiconductor bit type label description 0 r/w stand_alone 0: DA9210 is used as companion ic to da9063 or compliant 1: DA9210 is stand alone or as companion ic w ith another pmu not da9063 compliant table 48 : misc_supp (0x14f) bit type label description 7:1 r/w r eserved 0 r/w otp_clk_on forces t he oscillator and the otp clock on if asserted table 4 9 : device_id (0x201) bit type label description 7:0 r dev_id device id table 50 : device_id (0x203) bit type label description 7:4 r mrc mask revision code 3: 0 r vrc chip variant code table 51 : device - id (0x203) bit type label description 7:0 r cust_id customer id table 52 : config_id (0x204) bit type label description 7:0 r config_rev otp settings rev ision
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 77 of 90 ? 2016 dialog semiconductor 10 application information the components recommended in this section are examples selected from requirements of a typical application. 10.1 capacitor selection ceramic capacitors are used as bypass capacitors on all vdd and output rails. when selecting a capacitor, especially for types with high capacitance a nd small physical dimension, the dc bias characteristic has to be taken into account. table 53 : recommended c apacitor t ypes application value size tem p. char. tol rated voltag e type vddcore, output bypass 220 nf 0402 x5r +/ - 15% +/ - 10% 6.3 v murata grm155r60j224ke01( m e01) 220 nf 0201 x5r +/ - 15% +/ - 20% 6.3 v murata grm033r60j224me90 200 nf 0201 x5r +/ - 15% +/ - 10% 16 v semco cl03a224ko3nnnc 220 nf 0402 x7r +/ - 15% +/ - 10% 16 v murata grm155r71c224ka12d (automotive) vout_sense , output bypass 47 f 0805 x5r +/ - 15% +/ - 20% 4 v murata grm21br60g476me15 47 f 0603 x5r +/ - 15% +/ - 20% 4 v semco cl10a476mr8nz n 22 f 0402 x5r +/ - 15% +/ - 20% 4 v semco cl05a226mr5nz nc 47 f 0805 x5r + / - 15% +/ - 20% 10 v murata grm21br61a476me15l (automotive) 22 f 0603 x5r +/ - 15% +/ - 20% 10 v murata grm188r61a226me15d (automotive) 22 f 0805 x6s +/ - 22% +/ - 20% 10 v murata grm21bc81a226me44l (automotive) vddx bypass 10 f 0603 x5r +/ - 15% +/ - 20% 6.3 v m urata grm188r60j106me84 10 f 0805 x7r +/ - 15% +/ - 10% 6.3 v murata grm21br70j106ke76l (automotive) 10 f 0603 x6s +/ - 22% +/ - 20% 10 v murata grm188c81a106ma73d (automotive) vsys bypass 1 f 0402 x5r +/ - 15% +/ - 10% 10 v murata grm155r61a105ke15#
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 78 of 90 ? 2016 dialog semiconductor application value size tem p. char. tol rated voltag e type 1 f 04 02 x6s +/ - 22% +/ - 10% 10 v murata grm155c81a105ka12d (automotive) 10.2 inductor selection inductors should be selected based upon the following parameters: rated max imum current: usually a coil provides two current limits: the isat specifies the maximum current at which the inductance drops by 30 % of the nominal value. the imax is defined by the maximum power dissipation and is applied to the effective current. dc resistance: critical to converter efficiency and should therefore be minimized. inductance: given by converter electrical characteristics; 0. 47 h for all DA9210 phases. table 54 : recommended i nductor t ypes (including only typical values for the parts application value size im ax(dc) isat tolerance dc res. type buck 4x 0.47 h 2.0x1.6x1.0 mm 3.3 a 3.5 a +/ - 30% 48 m? toko dfe201610c 1285as - h - r47m 4x 0.47 h 2.0x1.6x1.2 mm 3.8 a 4.2 a +/ - 30% 40 m? toko dfe201612c 1286as - h - r47m 4x 0.47 h 2.5x2. 0x1.0 mm 3.6 a 3.9 a +/ - 20% 35 m? toko dfe252010c 1269as - h - r47m 4x 0.47 h 2.5x2.0x1.2 mm 4.4 a 4.7 a +/ - 20% 29 m? toko dfe252012c 1239as - h - r47m 4x0.47 h 2.0x1.6x1.0 mm 2.7 a 3.5 a +/ - 20% 38 m? tdk tfm201610a r47m 4x0.47 h 2.5x2.0x1.0 mm 2.8 a 4 .5 a +/ - 20% 34 m? tdk tfm252010a r47m 4x0.47 h 2.0x1.6x1.0 mm 2.7 a 3.56 a +/ - 20% 38 m? cyntec pife20161t 4x0.47 h 2.5x2.0x1.0 mm 3.5 a 4.5 a +/ - 20% 34 m? cyntec pife25201t 4x0.47 h 2.5x2.0x1.2 mm 4.5 a 5.0 a +/ - 20% 23 m? cyntec pife25201b 4x0.4 7 h 2.5x2.0x1.2 mm 3.7 a 3.9 a +/ - 20% 25 m? cyntec pst25201b 4x0.47 h 2.0x2.0x1.2 mm 2.8 a 4.2 a +/ - 30% 30 m? taiyo yuden mdmk2020t r47m 4x0.47 h 2.5x2.0x1.2 mm 3.9 a 4.8 a +/ - 20% 30 m? taiyo yuden mamk2520t r47m 4x0.47 h 2.0x1.6x1.0 mm 3.2 a 3. 6 a +/ - 20% 32 m? murata lqm2mpnr47mgh 4x 0.47 h 4x4x1.2 mm 8.7 a 6.7 a +/ - 20% 14m? coilcraft xfl4012 - 471me
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 79 of 90 ? 2016 dialog semiconductor 10.3 layout guidelines 10.3.1 general r ecommendations appropriate trace width and amount of vias should be used for all power supply paths. too high tra ce resistances can prevent the system operating correctly , for example, efficiency and current ratings of switch mode converters and charger might be degraded. furthermore the pcb might be exposed to thermal hot spots, which can lead to critical overheatin g due to the positive temperature coefficient of copper. special care must be taken with the DA9210 pad connections. the traces of the o uter row should be connected with the same width as the pads and should become wider as soon as possible. for supply pins in the second row , connection to an inner layer is recommended (depending on the maximum current two or more vias might be required). a common ground plane should be used, which allows proper electrical and thermal performance. noise sensitive references like vref should be referred to a silent ground which is connected at a star point underneath or close to the DA9210 main ground connection. generally all power tracks with discontinuous and / or high currents should be kept as short as possible. noise sensitive analog signals like feedback lines should be kept away from traces carrying pulsed analog or digital signals. this can be achieved by separation (distance) or shielding of quiet signals by ground traces. 10.3.2 switched m ode s upplies the placement of the distributed cap acitors at vsys must ensure that all vdd inputs are connected to a bypass capacitor close to the pads. using a local power plane underneath the chip for vsys might be considered. the area of switched mode converter t ransient current loops should be minimiz ed. output capacitor s of the ldocore should be placed close to DA9210 . care must be taken that no current is carried on feedback lines of the buck output voltage vout_sense. the i nductor placement is less critical as parasitic inductances do not matter. 10.3.3 DA9210 t hermal c onnection, la nd p ad a nd s tencil d esign the DA9210 provides a cent er ground area of balls, which are soldered to the pcbs cent er ground pad. this pcb ground pad must be connected with as many vias and as direct as possible to the pcbs main ground plane in order to achieve good thermal performance. solder mask openings for the ball landing pads must be arranged to prohibit solder balls flowing into vias.
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 80 of 90 ? 2016 dialog semiconductor 11 packa ge i nformation 11.1 package o utline d rawing (48 wlcs p) figure 48 : p ackage o utline d rawing (48 wlcsp) the package uses dialogs innovative routeeasy tm technology (patent pending) implementing a high number of ios on a small footprint package without the need for cost intensive pcb technology. all signals can be routed within two signal layers of a standard pcb (single trace between ic lands) and the inter layer connection uses drilled vias (no need for micro - via or via - in - land technology). please contact your local dialog semiconduc tor support for more information about pcb layout guidelines .
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 81 of 90 ? 2016 dialog semiconductor 11.1.1 routeeasy tm technology c hart bga ball d iameter: 0.27 (10 mm ) bga land size: 0.25 (10 mm ) via hole s ize (fhs): ? 0.2 - 0.25 (8 C 10 mm ) via pad s ize: ? 0.45 (18 mm ) anti - pad s ize: ? 0.65 (26 mm ) trace w idth: 0.1 C 0.125 (4 C 5 mm ) trace/trace s pace: 0.1 C 0.125 (4 C 5 mm ) trace/pad/land s pace: 0.1 (4 mm ) note dimensions are in millimeter. the pcb design complexity is compatible w ith 0.8 mm bga pin p itch (similar to ipc 6012b class 2). bet ter thermal relief and improved high current return paths are achieved by using a reduced copper - to - hole distance for the inner layer reference planes (inner anti - pad s ize: 0.55 mm or 0.6 mm).
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 82 of 90 ? 2016 dialog semiconductor 11.2 package o utline d rawing (42 vf - bga) figure 49 : package o utline d rawing (42 vf - bga)
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 83 of 90 ? 2016 dialog semiconductor 11.3 soldering i nformation refer to the jedec standard j - std - 020 for relevant soldering information. this document can be downloaded from http://www.jedec.org .
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 84 of 90 ? 2016 dialog semiconductor 12 ordering i nformation the ordering number consists of the part number followed by a suffix indicating the packing method. for details and availability, please cons ult dialog semiconductor s customer portal or your local sales representative. table 55 : ordering i nformation part num ber package size (m m) sh ipm ent form pack quantity com m ents DA9210 - xxuk2 48 wlcsp tape and reel 5000 DA9210 - x xfn2 - a 42 vfbga tape and real 5000 automotive aec - q100 grade 3
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 85 of 90 ? 2016 dialog semiconductor appendix a definitions a.1 power d i ssipation and t hermal d esign when designing with the DA9210 , consideration must be given to power dissipation as if the device exceeds the package power dissipation, the internal thermal sensor will shut down the device until. until it has cooled sufficiently. the package includes a thermal management paddle to enable improved heat spreading on the pcb. linear regulators operating with a high current and high differential voltage between input and output will dissipate the following power : example C a regulator supplying 150 ma @ 2.8 v from a fully charged lithium battery (vdd = 4.1 v) p diss = (4.1 v - 2.8 v) * 0.15 a = 195 mw for switching regulators p out = p in * efficiency ther efore p diss = p in C p out example C an 85 % efficient buck converter supplying 1.2v@ 400 ma as the DA9210 is a multiple regulator configuration each supply must be considered and summed to give the total device dissipation (current drawn from the reference and control circuitry can be considered negligible in these calculations) . p diss = (v in - v out )*i out p diss = p out - p out efficiency p diss = p out * efficiency 1 - 1 p diss = i out * v out * efficiency 1 - 1 p diss = 1.2v * 0.4a * - 1 1 0.85 = 85mw
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 86 of 90 ? 2016 dialog semiconductor a.2 re gulator p arameter - d ropout v oltage in the DA9210 , a regulators dropout voltage is defined as the minimum voltage differential between the input and output voltages whilst regulation still takes place. within the regulator, voltage control takes place across a pmos pass transistor and when entering the dropout condition the transistor is fully turned on and t herefore cannot provide any further voltage control. when the transistor is fully turned on the output voltage tracks the input voltage and regulation ceases. as the DA9210 is a cmos device and uses a pmos pass transistor, the dropout voltage is directly related to the on resistance of the device. in the device , the pass transistors are sized to provide the optimum balance between required performance and silicon area. by em ploying a 0.25 m process , dialog are able to achieve very small pass transistor sizes for superior performance. v dropout = v in C v out = r dson * i out when defining dropout voltage , it is specified in relation to a minimum acceptable change in output voltag e. for example , all dialog regulators have the dropout voltage defined as the point at which the output voltage drops 10 mv below the output voltage at the minimum guaranteed operating voltage. the worst case conditions for dropout are high temperature (hi ghest on resistance for internal device) and maximum load current . a.3 regulator p arameter C p ower s upply r ejection power supply rejection (psrr) is especially important in the supplies to the rf and audio parts of the telephone. in a tdma system such as gsm, the 217 hz transmit burst from the power amplifier results in significant current pulses being drawn from the battery . these can peak at up to 2 a before rea ching a steady state of 1.4 a (see figure 50 ). due to th e battery having a finite internal resistance (typically 0.5 ? ) , these current peaks induce ripple on the battery voltage of up to 500 mv. as the supplies to the audio and rf are derived from this supply , it is essential that this ripple is removed , otherwise it would show as a 217 hz tone in the audio and could als o affect the transmit signal. power supply rejection should always be specified under worst case conditions when the battery is at its minimum operating voltage, when there is minimum headroom available due to dropout. a.4 regulator p arameter C l ine r egulation static line regulation is a measurement that indicates a change in the regulator output voltage ? vreg (regulator operating with a constant load current) in response to a change in the input voltage ? vin. transient line regulation is a measurement of the peak change ? vreg in regulated voltage seen when the line input voltage changes. figure 50 : line r egulation 4.6ms tdma frame rate ? v r e g s t a t i c ? v i n ? v r e g t r a n s i e n t 5 7 7 s v bat v reg
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 87 of 90 ? 2016 dialog semiconductor a.5 regulator p arameter C l oad r egulation static load regulation is a measurement that indicates a change in the regulator output voltage ? vreg in response to a change in the regulator loading ? l oad whilst the regulator input voltage remains constant. transient load regulation is a measurement of the peak change in regulated voltage ? vreg seen when the regulator load changes. figure 51 : load r e gulation please contact dialog semiconductor for latest application information on the DA9210 and other power management devices. ? v r e g s t a t i c ? v r e g t r a n s i e n t v reg i load max i load min
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 88 of 90 ? 2016 dialog semiconductor revi sion h istory revision date description 1.0 oct 2011 initial release 1.1 to 1. x mar 2015 regular updates for development and specification alignment 2.0 sep 2016 updated and s tandardized to latest publishing guidelines
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 89 of 90 ? 2016 dialog semiconductor status definitions rev ision datasheet status product status definition 1. target development this datasheet contains the design specifications for product development. specifications may be changed in any manner without notice. 2. preliminary qualification this datasheet contains the specifications and preliminary characte rization data for products in pre - production. specifications may be changed at any time without notice in order to improve the design. 3. final production this datasheet contains the final specifications for products in volume production. the specifica tions may be changed at any time in order to improve the design, manufacturing and supply. major specification changes are communicated via customer product notifications. datasheet changes are communicated via www.dialog - semiconductor.com . 4. obsolete archived this datasheet contains the specifications for discontinued products. the information is provided for reference only. disclaimer information in this document is believed to be accurate and reliable. however, dialog semiconductor does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information. dialog semiconductor furthermore takes no responsibility whatsoever for the content in th is document if provided by any information source outside of dialog semiconductor. dialog semiconductor reserves the right to change without notice the information published in this document, including withou t limitation the specification and the design of the related semiconductor products, software and applications. applications, software, and semiconductor products described in this document are for illustrative purposes only. dialog semiconductor makes no representation or warranty that such applicatio ns, software and semiconductor products will be suitable for the specified use without further testing or modification. unless otherwise agreed in writing, such testing or modification is the sole responsibility of the customer and dialog semiconductor exc ludes all liability in this respect. customer notes that nothing in this document may be construed as a license for customer to use the dialog semiconductor products, software and applications referred to in this document. such license must be separately sought by customer with dialog semiconductor. all use of dialog semiconductor products, software and applications referred to in this document are subject to dialog semiconductors standard terms and conditions of sale , available on the company website ( www.dialog - semiconductor.com ) unless otherwise stated. dialog and the dialog logo are trademarks of dialog semiconductor pl c or its subsidiaries. all other product or service names are the property of their respective owners. ? 2016 dialog semiconductor. all rights reserved.
DA9210 DA9210 multi - phase 12 a dc - dc buck converter datasheet revision 2.0 09 - sep - 2016 cfr0011 - 120 - 00 90 of 90 ? 2016 dialog semiconductor rohs c ompliance dialog semiconductors suppliers certify that its products are in compliance with the requirements of directive 2011/65/eu of the european parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. rohs certificates from our suppliers are available on request. contacting dialog semiconductor united kingdom (headquarters) dialog semiconductor (uk) ltd phone: +44 1793 757700 germany dialog semiconductor gmbh phone: +49 7021 805 - 0 the netherlands dialog semiconductor b.v. phone: +31 73 640 8822 north ame rica dialog semiconductor inc. phone: +1 408 845 8500 japan dialog semiconductor k. k. phone: +81 3 5425 4567 taiwan dialog semiconductor taiwan phone: +886 281 786 222 singapore dialog semiconductor singapore phone: +65 64 8499 29 hong kong dialog semicon ductor hong kong phone: +852 3769 5200 korea dialog semiconductor korea phone: +82 2 3469 8200 china (shenzhen) dialog semiconductor china phone: +86 755 2981 3669 china (shanghai) dialog semiconductor china phone: +86 21 5424 9058

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