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data sheet low skew, 1-to-4 differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer IDT8T33FS314I idt8t33fs314pgi revision a march 7, 2014 1 ?2014 integrated device technology, inc. general description the IDT8T33FS314I is a low skew 1-to-4 differential fanout buffer, designed with clock distribution in mind, accepting two clock sources into an input mux. the mux is controlled by a clk_sel pin. this makes the IDT8T33FS314I very versatile, in that, it can operate as both a differential clock buffer as well as a signal-level translator and fanout buffer. the device is designed on a sige process and can operate at frequencies in excess of 2.7ghz. this ensures negligible jitter introduction to the timing budget which makes it an ideal choice for distributing high frequency, high precision clocks across back planes and boards in communication systems. internal temperature compensation guarantees consistent performance across various platforms. features ? four differential ecl/lvpecl level outputs ? one differential ecl/lvpecl or single-ended input (clka) one differential hstl or single-ended input (clkb) ? maximum output frequency: 2.7ghz ? additive phase jitter, rms: 0.114ps (typical) @ 156.25mhz ? output skew: 50ps (maximum) ? lvpecl and hstl mode operat ing voltage s upply range: v cc = 2.5v5% or 3.3v5%, v ee = 0v ? ecl mode operating voltage supply range: v ee = -3.3v5% or -2.5v5%, v cc = 0v ? -40c to 85c ambient operating temperature ? lead-free (rohs 6) packaging block diagram pin assignment 0 1 v cc v cc v ee v ee v ee clkb nclkb clk_sel pulldown pullup/pulldown pulldown clka nclka pullup/pulldown pulldown q0 nq0 q1 nq1 q2 nq2 q3 nq3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v ee nclkb clkb nclka clka clk_sel v cc nc v cc v cc v cc q0 nq0 q1 nq1 q2 nq2 q3 nq3 v cc IDT8T33FS314I 20-lead 209-mil ssop 5.3mm x 7.2mm x 1.75mm body package py package top view 20-lead tssop 4.4mm x 6.5mm x 0.925mm body package pg package top view
idt8t33fs314pgi revision a march 7, 2014 2 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer pin descriptions and characteristics table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 3, 10 11, 20 v cc power positive supply pins. 2 nc unused no connect. 4 clk_sel input pulldown clock select input. when high , selects clkb, nclkb inputs. when low, selects clka, nclka inputs. 5 clka input pulldown default non-inverting differential clock input. lvpecl/ecl interface levels. 6nclkainput pullup/ pulldown default inverting differ ential clock input. lvpecl/ ecl interface levels. 7 clkb input pulldown alternative non-inverting diff erential clock input. hstl interface levels. 8nclkbinput pullup/ pulldown alternative inverting differential cl ock input. hstl interface levels. 9v ee power negative supply pin. 12, 13 nq3,q3 output differe ntial output pair. lvpec l/ecl interf ace levels. 14, 15 nq2,q2 output differe ntial output pair. lvpec l/ecl interf ace levels. 16, 17 nq1,q1 output differe ntial output pair. lvpec l/ecl interf ace levels. 18, 19 nq0,q0 output differe ntial output pair. lvpec l/ecl interf ace levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance clk_sel 2 pf r pullup input pullup resistor 75 k ? r pulldown input pulldown resistor 75 k ?
idt8t33fs314pgi revision a march 7, 2014 3 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are s tress specifications only. functional operation of the product at these conditions or any conditions beyond those listed in the dc ch aracteristics or ac characteristics is not implied. exposure to absolute maxi mum rating conditions for extended periods may affect product relia bility. dc electrical characteristics table 3a. lvpecl dc characteristics, v cc = 2.5v 5% or 3.3v 5%, v ee = 0v, t a = -40c to 85c note 1: v pp is the minimum differential input voltage swing required to maintain device functionality. note 2: v cmr is the crosspoint of the differential in put signal. functional operation is obtained when the crosspoint is within the v cmr range and the input swing lies within the v pp specification. note 3: v dif is the minimum differential hstl input voltage swing required for device functionality. note 4: v x is the crosspoint of the differential hs tl input signal. functional operation is obta ined when the crosspoint is within the v x range and the input swing lies within the v pp specification. item rating supply voltage, v cc 3.9v (lvpecl mode, v ee = 0v) negative supply voltage, v ee -3.9v (ecl mode, v cc = 0v) inputs, v i (lvpecl mode) -0.3v to v cc + 0.3v inputs, v i (ecl mode) 0.3v to v ee ? 0.3v outputs, i o continuous current 50ma package thermal impedance, ? ja 20-lead ssop 20-lead tssop 100.4 ? c/w (0 mps) 115.0 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units control input clk_sel v il input low voltage v cc - 1.810 v cc - 1.475 v v ih input high voltage v cc - 1.165 v cc - 0.880 v i in input current v in = v il or v in = v ih 100 a clock input pair clka, ncl ka (lvpecl differential signals) v pp peak-to-peak input voltage; note 1 0.1 1.3 v v cmr common mode input voltage; note 2 1.0 v cc - 0.3 v i in input current v in = v il or v in = v ih 100 a clock input pair clkb, nclkb (hstl differential signals) v dif differential input voltage; note 3 v cc = 3.3v 0.4 v v cc = 2.5v 0.4 v v x differential crosspoint voltage; note 4 0 0.68 - 0.9 v cc - 1.0 v i in input current v in = v x 0.2v 200 a lvpecl clock outputs (q[0:3], nq[0:3]) v oh output high voltage v cc - 1.2 v cc - 0.808 v cc - 0.7 v v ol output low voltage v cc = 3.3v 5% v cc - 1.9 v cc - 1.689 v cc - 1.5 v v cc = 2.5v 5% v cc - 1.9 v cc - 1.662 v cc - 1.3 v supply current i ee maximum quiescent supply current without output termination current 49 60 ma
idt8t33fs314pgi revision a march 7, 2014 4 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer table 3b. ecl dc characteristics, v cc = 0v, v ee = -3.3v5% or -2.5v5%, t a = -40c to 85c note 1: v pp is the minimum differential input voltage swing required to maintain device functionality. note 2: v cmr is the crosspoint of the differential in put signal. functional operation is obtained when the crosspoint is within the v cmr range and the input swing lies within the v pp specification. symbol parameter test conditio ns minimum typical maximum units control input clk_sel v il input low voltage -1.810 -1.475 v v ih input high voltage -1.165 -0.880 v i in input current v in = v il or v in = v ih 100 a clock input pair clka, ncl ka (lvpecl differential signals) v pp peak-to-peak input voltage; note 1 0.1 1.3 v v cmr common mode input voltage; note 2 v ee + 1.0 -0.3 v i in input current v in = v il or v in = v ih 100 a lvpecl clock outputs (q[0:3], nq[0:3]) v oh output high voltage -1.2 -0.808 -0.7 v v ol output low voltage v ee = -3.3v 5% -1.9 -1.689 -1.5 v v ee = -2.5v 5% -1.9 -1.662 -1.3 v supply current i ee maximum quiescent supply current without output termination current 49 60 ma
idt8t33fs314pgi revision a march 7, 2014 5 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer ac electrical characteristics table 4. ac characteristics, (lvpecl/hstl), v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, or (ecl) v ee = -3.3v 5% or -2.5v 5%, v cc = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: v pp is the minimum differential ecl/lvpecl input voltage swing required to maintain ac characteristics including t pd and device-to-device skew. note 2: v cmr is the crosspoint of the differential ecl/lvpecl input signal. normal ac operation is obtained when the crosspoint is within the v cmr range and the input swing lies within the v pp specification. violation of v cmr or v pp impacts the device propagation delay, device and part-to-part skew. note 3: the idt8t33fs314 is fully operational up to 2.7ghz and is characterized up to 1.5ghz. note 4: propagation delay specified for output rise and fall times less than 5ns. note 5: v dif is the minimum differential hstl input voltage swing required to maintain ac characteristics including t pd and device-to- device skew. note 6: v x is the crosspoint of the differential hstl input signal. normal ac operation is obtained when the crosspoint is within the v x range and the input swing lies within the v dif specification. violation of v x or v dif impacts the device propagation delay, device and part-to-part skew. note 7: output pulse skew is the absolute value of the difference of the propagation delay times: ? t plh ? t phl ? . symbol parameter test conditio ns minimum typical maximum units v pp differential input voltage; note 1 0.15 1.3 v v cmr differential input crosspoint voltage; note 2 v ee + 1.0 v cc - 0.3 v f clk input frequency; note 3 2.7 ghz t pd propagation delay, clka or clkb to output pair; note 4 230 650 ps v dif hstl differential input voltage; note 5 0.4 1.0 v v x hstl input differential crosspoint voltage; note 6 v ee + 0.01 v cc - 1.0 v v o (pp) differential output voltage (peak-to-peak) ? out < 300mhz 0.45 0.88 0.95 v ? out < 1.5ghz 0.3 0.74 0.95 v tsk(o) output skew 50 ps tjit buffer additive phase jitter, rms; refer to additive phase jitter section 156.25mhz, @ 3.3v, 1.875mhz ? 20mhz 0.114 ps 312.5mhz @ 3.3v, 1.875mhz ? 20mhz 0.052 ps tsk(p) output pulse skew; note 7 660mhz 75 ps t r / t f output rise/fall time 20% to 80% 0.05 0.3 ns
idt8t33fs314pgi revision a march 7, 2014 6 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundament al frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications , phase noise measurements have issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device me ets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. a rohde & schartz sma100 was used as input source. ssb phase noise (dbc/hz) offset from carrier frequency (hz)
idt8t33fs314pgi revision a march 7, 2014 7 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer a rohde & schartz sma100 was used as input source. ssb phase noise (dbc/hz) offset from carrier frequency (hz)
idt8t33fs314pgi revision a march 7, 2014 8 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer parameter measureme nt information 3.3v, 2.5v lvpecl output load test circuit output skew output pulse skew differential input level propagation delay output rise/fall time scope qx nqx v ee v cc 2v -0.375v to -1.465v nqx qx nqy qy t plh t phl tsk(p) = |t phl - t plh | nclka, nclkb clka, clkb nq[0:3] q[0:3] v cmr cross points v pp , v dif v cc v ee nclka, nclkb clka, clkb t pd nclka, nclkb clka, clkb nq[0:3] q[0:3] 20% 80% 80% 20% t r t f v o(pp) nq[0:3] q[0:3]
idt8t33fs314pgi revision a march 7, 2014 9 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer applications information recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the use of a differential input, both the clk and nclk pins can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. outputs: lvpecl outputs all unused lvpecl outputs can be le ft floating. we recommend that there is no trace attached. both si des of the differential output pair should either be left floating or terminated. wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. similarly, if the input clock swing is 1.8v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 0.9v. it is recommended to always use r1 and r2 to provide a known v 1 voltage. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that the su m of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, match ed termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be in creased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels
idt8t33fs314pgi revision a march 7, 2014 10 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer 3.3v differential clock input interface clkx/nclkx accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both v o(pp) and v oh must meet the v pp and v cmr input requirements. figure 2a to figure 2e show interface examples for the clkx/nclkx input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of t he driver component to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 2a. clkx/nclkx input driven by an idt open emitter lvhstl driver figure 2c. clkx/nclkx input driven by a 3.3v lvpecl driver figure 2e. clkx/nclkx input driven by a 3.3v hcsl driver figure 2b. clkx/nclkx input driven by a 3.3v lvpecl driver figure 2d. clkx/nclkx input driven by a 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input 3 . 3v c l k n c l k 3 . 3v 3 . 3v lvpe cl differential in p u t h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t clk nclk differential input lvpecl 3.3v zo = 50 zo = 50 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 zo = 50
idt8t33fs314pgi revision a march 7, 2014 11 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer 2.5v differential clock input interface clkx/nclkx accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both v o(pp) and v oh must meet the v pp and v cmr input requirements. figure 3a to figure 3e show interface examples for the clkx/nclkx input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of t he driver component to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. clkx/nclkx input driven by an idt open emitter lvhstl driver figure 3c. clkx/nclkx input driven by a 2.5v lvpecl driver figure 3e. clkx/nclkx input driven by a 2.5v hcsl driver figure 3b. clkx/nclkx input driven by a 2.5v lvpecl driver figure 3d. clkx/nclkx input driven by a 2.5v lvds driver r1 50 ? r2 50 ? 1. 8v zo = 50 ? ? ? ? ? ? ? ? s l * r 333 * r4 33 clk nclk 2.5v 2.5v zo = 50 zo = 50 differenti a l inp u t r1 50 r2 50 * option a l ? r 3 a nd r4 c a n b e 0 ? ? ? ? ? ? ? ?
idt8t33fs314pgi revision a march 7, 2014 12 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are a lo w impedance follower output that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current pa th to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 4a. 3.3v lvpecl output termination figure 4b. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
idt8t33fs314pgi revision a march 7, 2014 13 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer termination for 2.5v lvpecl outputs figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. figure 5a. 2.5v lvpecl driver termination example figure 5c. 2.5v lvpecl driver termination example figure 5b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r1 50 r2 50 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r1 50 r2 50 r3 18 + ?
idt8t33fs314pgi revision a march 7, 2014 14 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer power considerations this section provides information on power dissipati on and junction temperature for the IDT8T33FS314I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the IDT8T33FS314I is the sum of the core power plus the power dissipated due to the load. the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 60ma = 207.9mw ? power (outputs) max = 33.2mw/loaded output pair if all outputs are loaded, the total power is 4 * 33.2mw = 132.8mw total power_ max (3.465v, with all outputs s witching) = 207.9mw + 132.8mw = 340.7mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate va lue is 115c/w per table 5a below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.341w * 115c/w = 124.2c. this is within the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 5a. thermal resistance ? ja for 20-lead tssop, forced convection table 5b. thermal resistance ? ja for 20-lead ssop, forced convection ? ja by velocity meters per second 012 multi-layer pcb, jedec standard test boards 115.0c/w 109.1c/w 103.9c/w ? ja by velocity meters per second 012 multi-layer pcb, jedec standard test boards 100.4c/w 92.7c/w 87.3c/w
idt8t33fs314pgi revision a march 7, 2014 15 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pairs. lvpecl output driver circuit and termination are shown in figure 6. figure 6. lvpecl driver circuit and termination to calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.7v (v cc_max ? v oh_max ) = 0.7v ? for logic low, v out = v ol_max = v cc_max ? 1.5v (v cc_max ? v ol_max ) = 1.5v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.7v)/50 ? ] * 0.7v = 18.2mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l] * (v cc_max ? v ol_max ) = [(2v ? 1.5v)/50 ? ] * 1.5v = 15mw total power dissipation per output pair = pd_h + pd_l = 33.2mw v out v cc v cc - 2v q1 rl 50
idt8t33fs314pgi revision a march 7, 2014 16 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer reliability information table 6a. ? ja vs. air flow table for a 20-lead tssop table 6b. ? ja vs. air flow table for a 20-lead ssop transistor count the transistor count for IDT8T33FS314I is: 882 ? ja by velocity meters per second 012 multi-layer pcb, jedec standard test boards 115.0c/w 109.1c/w 103.9c/w ? ja by velocity meters per second 012 multi-layer pcb, jedec standard test boards 100.4c/w 92.7c/w 87.3c/w
idt8t33fs314pgi revision a march 7, 2014 17 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer 20-lead ssop package outl ine and package dimensions
idt8t33fs314pgi revision a march 7, 2014 18 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer 20-lead ssop package outline an d package dimensions, continued
idt8t33fs314pgi revision a march 7, 2014 19 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer 20-lead ssop package outline an d package dimensions, continued
idt8t33fs314pgi revision a march 7, 2014 20 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer 20-lead tssop package out line and package dimensions
idt8t33fs314pgi revision a march 7, 2014 21 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer 20-lead tssop package outline an d package dimensions, continued
idt8t33fs314pgi revision a march 7, 2014 22 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer 20-lead tssop package outline an d package dimensions, continued
idt8t33fs314pgi revision a march 7, 2014 23 ?2014 integrated device technology, inc. IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer ordering information table 7. ordering information part/order number marking package shipping packaging temperature 8t33fs314pggi idt8t33fs314pggi ? lead-free? 20-lead tssop tube -40 ? c to 85 ? c 8t33fs314pggi8 idt8t33fs314pggi ?lea d-free? 20-lead tssop tape & reel -40 ? c to 85 ? c 8t33fs314pygi idt8t33f s314pygi ?lead-free? 20-lead ssop tube -40 ? c to 85 ? c 8t33fs314pygi8 idt8t33fs314pygi ?lead- free? 20-lead ssop tape & reel -40 ? c to 85 ? c
IDT8T33FS314I data sheet low skew, 1-to-4 differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2014. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contact idt technical support sales netcom@idt.com +480-763-2056 we?ve got your timing solution

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