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73s8014r smart card interface simplifying system integration? data sheet september 2008 rev. 1.0 ? 2008 teridian semiconductor corporation 1 description the teridian 73s8014r is a single smart card (icc) interface circuit, firmware compatible with 8024-type devices for configurations where only asynchronous cards must be supported. it is derived from the 73s8024rn industry- standard electrical interface. the 73s8014r has been optimized to match most of the typical set-top-box / a/v conditional access applications. optimization essentially involved a smaller pin-coun t, support for single i/o, and maximum card current of 65ma (iso-7816 / emv compliance). the 73s8014r interfaces with the host processor through the same bus (digital i/os) as the 73s8024rn, which is compatible with any other 8024-type ic. as a result, the 73s8014r is a very attractive cost-reduction path from traditional 8024 ics. the 73s8014r has been designed to provide full electrical compliance with iso 7816-3 and emv 4.0 specifications. interfacing with the system controller is done through a control bus, composed of digital inputs to control the interface, and one interrupt output to inform the system controller of the card presence and faults. the card clock can be generated by an on-chip oscillator using an external crystal or by connection to an externally supplied clock signal. the 73s8014r incorporates an iso 7816-3 activation/deactivation sequencer that controls the card signals. level-shifters drive the card signals with the selected card voltage (3v or 5v), coming from an internal low drop-out (ldo) voltage regulator. this ldo regulator is powered by a dedicated power supply input v pc . digital circuitry is powered separately by a digital power supply v dd . with its embedded ldo regulator, the 73s8024rn is a cost-effective solution for any application where a 5v (typically -5% +10%) power supply is available. emergency card deactivation is initiated upon card extraction or upon any fault detected by the protection circuitry. the fault can be a card over-current, vcc undervoltage or power supply fault (v dd ). the card over-current circuitry is a true current detection function, as opposed to v cc voltage drop detection, as usually implemented in non-teridian 8024 interface ics. the v dd voltage fault has a threshold voltage that can be adjusted with an external resistor network. it allows automated card deactivation at a customized v dd voltage threshold value. it can be used, for instance, to match the system controller operating voltage range. applications ? set-top-box conditional access and pay-per-view ? general purpose smart card readers advantages ? same advantages as the teridian 73s80xxr family: ? vcc card generated by an ldo regulator ? very low power dissipation (saves up to 1/2w) ? fewer external components are required ? better noise performance ? true card over-current detection ? firmware compatibility with all 8024 ics ? small format 20so package features ? card interface: ? complies with iso 7816-3 and emv 4.0 ? supports 3v / 5v cards ? iso 7816-3 activation / deactivation sequencer ? automated deactivation upon hardware fault (i.e. upon drop on v dd power supply or card overcurrent) ? the v dd voltage supervisor threshold value (fault) can be externally adjusted ? over-current detection 130ma max ? card clk clock frequency up to 20mhz ? system controller interface: ? 3 digital inputs control the card activation / deactivation, card reset and card voltage ? 2 digital inputs control the card clock frequency ? 1 digital output, interrupt to the system controller, reports to the host the card presence and faults ? crystal oscillator or host clock, up to 27mhz ? regulator power supply: ? 4.75v to 5.5v ? digital interfacing: 2.7v to 5.5v ? 6kv esd protection on the card interface ? package: so 20-pin ? rohs compliant (6/6) lead-free package downloaded from: http:///
73s8014r data sheet ds_8014r_012 2 rev. 1.0 functional diagram smart card i/o buffer ldo regulator sc sequencer internal power supply voltage reference xtal osc clock generation controller and registers fault logic reset buffer clock buffer r-c osc. vdd fault vcc fault clock 1.5mhz vdd vpc vcc rst clk pres i/o cm dv cc rstin 5v/ #v ckdiv1 ckdiv2 gnd vpd - internal supply off test bias currents vref vcc circuits vdd ckt vdd circuits vdd circuits gnd vddf_adj xtalin xtalout iouc figure 1: 73s8014r block diagram downloaded from: http:///
ds_8014r_012 73s8014r data sheet rev. 1.0 3 table of contents 1 ? pinout .............................................................................................................................. .................................. 5 ? 2 ? electrical specifications .............................................................................................................................. .... 8 ? 2.1 ? absolute maximum ratings ........................................................................................................................ 8 ? 2.2 ? recommended operating conditions ......................................................................................................... 8 ? 2.3 ? package thermal parameters .................................................................................................................... 9 ? 2.4 ? smart card interface requirements ........................................................................................................... 9 ? 2.5 ? characteristics: digital signals .................................................................................................................. 11 ? 2.6 ? dc characteristics .............................................................................................................................. ...... 12 ? 2.7 ? voltage fault detection circuits ................................................................................................................ 13 ? 3 ? applications information .............................................................................................................................. . 14 ? 3.1 ? example 73s8014r schematics .............................................................................................................. 14 ? 3.2 ? system controller interface ....................................................................................................................... 16 ? 3.3 ? power supply and voltage supervision .................................................................................................... 16 ? 3.4 ? card power supply .............................................................................................................................. ..... 17 ? 3.5 ? on-chip oscillator and card clock ........................................................................................................... 17 ? 3.6 ? activation sequence .............................................................................................................................. ... 18 ? 3.7 ? deactivation sequence ............................................................................................................................. 19 ? 3.8 ? fault detection and off ........................................................................................................................... 20 ? 3.9 ? i/o circuitry and timing ............................................................................................................................ 2 0 ? 4 ? equivalent circuits .............................................................................................................................. ........... 22 ? 5 ? mechanical drawing .............................................................................................................................. ......... 27 ? 6 ? ordering information .............................................................................................................................. ....... 28 ? 7 ? related documentation .............................................................................................................................. ... 28 ? 8 ? contact information .............................................................................................................................. ......... 28 ? downloaded from: http:///
73s8014r data sheet ds_8014r_012 4 rev. 1.0 figures figure 1: 73s8014r block diagram .......................................................................................................................... 2 ? figure 2: 73s8014r 20-sop pin out ........................................................................................................................ 5 ? figure 3: 73s8014r C typical application schematic ............................................................................................ 15 ? figure 4: activation sequence C rstin low when cmdvcc goes low ............................................................. 18 ? figure 5: activation sequence C rstin high when cmdvcc goes low ............................................................. 19 ? figure 6: deactivation sequence ............................................................................................................................ 1 9 ? figure 7: timing diagram C management of the interrupt line off ...................................................................... 20 ? figure 8: i/o and i/ouc state diagram ................................................................................................................... 21 ? figure 9: i/o C i/ouc delays C timing diagram ..................................................................................................... 21 ? figure 10: open drain type C off .......................................................................................................................... 22 ? figure 11: power input/output circuit, vdd, vpc, vcc ........................................................................................ 22 ? figure 12: smart card clk driver circuit ............................................................................................................... 23 ? figure 13: smart card rst driver circuit ............................................................................................................... 23 ? figure 14: smart card io interface circuit .............................................................................................................. 24 ? figure 15: smart card iouc interface circuit ......................................................................................................... 24 ? figure 16: general input circuit .............................................................................................................................. 25 ? figure 17: oscillator circuit .............................................................................................................................. ....... 25 ? figure 18: vddf_adj .............................................................................................................................. ............... 26 ? figure 19: mechanical drawing 20-pin so package .............................................................................................. 27 ? tables table 1: 73s8014r 20-pin sop pin definitions ....................................................................................................... 6 ? table 2: absolute maximum device ratings ............................................................................................................. 8 ? table 3: recommended operating conditions ......................................................................................................... 8 ? table 4: package thermal parameters ..................................................................................................................... 9 ? table 5: dc smart card interface requirements ..................................................................................................... 9 ? table 6: digital signals characteristics ................................................................................................................... 11 ? table 7: dc characteristics .............................................................................................................................. ....... 12 ? table 8: voltage fault detection circuits ................................................................................................................ 13 ? table 9: order numbers and packaging marks ...................................................................................................... 28 ? downloaded from: http:///
ds_8014r_012 73s8014r data sheet rev. 1.0 5 1 pinout the 73s8014r is supplied as a 20-pin so package. 1 1817 16 15 14 1312 11 10 9 8 7 6 5 4 3 2 19 20 clkdiv1 clkdiv2 5v/ #v vpc pres i/o gnd i/ouc xtalin xtalout off vdd rstin cmdvcc vcc rst clk gnd vddf_adj gnd 73s8014r figure 2: 73s8014r 20-sop pin out downloaded from: http:///
73s8014r data sheet ds_8014r_012 6 rev. 1.0 table 1 provides the 73s8014r pin names, pin number s, type, equivalent circuits and descriptions. table 1: 73s8014r 20-pin sop pin definitions pin name pin number type equivalent circuit description card interface i/o 14 io figure 14 card i/o: data signal to/from card. includes an 11k pull-up resistor to v cc. rst 15 o figure 13 card reset: provides reset (rst) signal to card. clk 17 o figure 12 card clock: provides clock signal (clk) to card. the rate of this clock is determined by the external crystal frequency or frequency of the external clock signal applied on xtalin and clkdiv selections. pres 19 i figure 16 card presence switch: active high indicates card is present. includes a high-impedance pull-down current source. vcc 18 pso figure 11 card power supply C logically cont rolled by sequencer, output of ldo regulator. requires an external filter capacitor to the card gnd. gnd 16 gnd C card ground. host processor interface cmdvcc 6 i figure 16 command vcc (negative assertion): logic low on this pin causes the ldo regulator to ramp the v cc supply to the card and initiates a card activation sequence, if a card is present. 5v/ #v 7 i figure 16 5 volt / 3 volt card selection: logic one selects 5 volts for v cc and card interface, logic low selects 3 volt operation. when the part is to be used with a single card voltage, this pin should be tied to either gnd or v dd . however, it includes a high impedance pull-up resistor to default this pin high (selection of 5v card) when not connected. this pin shall not be changed when cmdvcc is low. clkdiv1 clkdiv2 20 5 i figure 16 sets the divide ratio from the xtal oscillator (or external clock input) to the card clock. these pins include a pull-up resistor for clkdiv1 and clkldiv2 to provide a default rate of divide by two. clkdiv1 clkdiv2 clock rate 0 0 xtalin/8 0 1 xtalin/4 1 1 xtalin/2 1 0 xtalin off 1 o figure 10 interrupt signal to the processor. active low - multi-function indicating fault conditions and card presence. open drain output configuration C it includes an internal 20k ? pull-up to v dd. rstin 2 i figure 16 reset input: this signal is the reset command to the card. i/ouc 3 io figure 15 system controller data i/o to/from the card. includes an 11k pull-up resistor to v dd. downloaded from: http:///
ds_8014r_012 73s8014r data sheet rev. 1.0 7 miscellaneous inputs and outputs xtalin 9 figure 17 crystal oscillator input: can either be connected to crystal or driven as a source for the card clock. note: when not using the crystal, the capacitors must be removed. xtalout 10 figure 17 crystal oscillator output: conne cted to crystal. left open if xtalin is being used as external clock input. note: when not using the crystal, the capacitors must be removed. vddf_adj 12 figure 18 v dd fault threshold adjustment input: this pin can be used to adjust the v ddf value (that controls deactivat ion of the card). must be left open if unused. power supply and ground vdd 13 pso figure 11 system interface supply voltage and supply voltage for internal circuitry. vpc 4 pso figure 11 ldo regulator power supply source. gnd 8, 11 gnd C digital ground. downloaded from: http:///
73s8014r data sheet ds_8014r_012 8 rev. 1.0 2 electrical specifications this section provides the following: ? absolute maximum ratings ? recommended operating conditions ? package thermal parameters ? smart card interface requirements ? digital signals characteristics ? dc characteristics ? voltage fault detection circuits 2.1 absolute maximum ratings table 2 lists the maximum operating conditions for the 73s8014r. permanent device damage may occur if absolute maximum ratings are exceeded. exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. the smart card in terface pins are protected against short circuits to v cc , ground, and each other. table 2: absolute maximum device ratings parameter rating supply voltage v dd -0.5 to 6.0 vdc supply voltage v pc -0.5 to 6.0 vdc input voltage for digital inputs -0.3 to (v dd +0.5) vdc storage temperature -60 to 150c pin voltage (except card interface) -0.3 to (v dd +0.5) vdc pin voltage (card interface) -0.3 to (v cc + 0.5) vdc esd tolerance C card interface pins +/- 6kv esd tolerance C other pins +/- 2kv *note: esd testing on smart card pins is hbm condi tion, 3 pulses, each polarity referenced to ground. note: smart card pins are protected against shorts between any combinations of smart card pins. 2.2 recommended operating conditions function operation should be restricted to the recommended operating conditions specified in table 3 . table 3: recommended operating conditions parameter rating supply voltage v dd 2.7 to 5.5 vdc supply voltage v pc 4.75 to 5.5 vdc ambient operating temperature -40c to +85c input voltage for digital inputs 0v to v dd + 0.3v downloaded from: http:///
ds_8014r_012 73s8014r data sheet rev. 1.0 9 2.3 package thermal parameters table 4 lists the 73s8014r smart card interface requirements. table 4: package thermal parameters parameter rating 20 so 50 c / w 2.4 smart card interface requirements table 5 lists the 73s8014r smart card interface requirements. table 5: dc smart card interface requirements symbol parameter condition min nom max unit card power supply (v cc ) regulator general conditions, -40 c < t < 85 c, 4.75v < v pc < 5.5v, 2.7v < v dd < 5.5v v cc card supply voltage including ripple and noise inactive mode -0.1 0.1 v inactive mode, i cc = 1ma -0.1 0.4 v active mode; i cc <65ma; 5v 4.65 5.25 v active mode; i cc <65ma; 3v 2.85 3.15 v active mode; i cc <40ma; 1.8v 1.68 1.92 v active mode; single pulse of 100ma for 2 s; 5 volt, fixed load = 25ma 4.6 5.25 v active mode; single pulse of 100ma for 2 s; 3v, fixed load = 25ma 2.76 3.2 v active mode; current pulses of 40nas with peak |i cc | <200ma, t <400ns; 5v 4.6 5.25 v active mode; current pulses of 40nas with peak |i cc | <200ma, t <400ns; 3v 2.7 3.15 v v ccrip v cc ripple f ripple = 20k C 200mhz 350 mv i ccmax card supply output current static load current, v cc >4.6v or 2.7v as selected 65 ma i ccf i cc fault current 70 130 ma v sr v cc slew rate, rise c f = 1.0 f on v cc 0.06 0.150 0.30 v/ s v sf v cc slew rate, fall c f = 1.0 f on v cc 0.075 0.150 0.60 v/ s c f external filter cap (v cc to gnd) c f should be ceramic with low esr (<100m ). 0.5 1.0 1.5 f downloaded from: http:///
73s8014r data sheet ds_8014r_012 10 rev. 1.0 symbol parameter condition min nom max unit interface requirements C data signals: i/oand host interfaces: i/ouc. i shortl , i shorth , and v inact requirements do not pertain to i/ouc. v oh output level, high (i/o) i oh =0 0.9 v cc v cc +0.1 v i oh = -40 a 0.75 v cc v cc +0.1 v output level, high (i/ouc) i oh =0 0.9 v dd v dd +0.1 v i oh = -40 a 0.75 v dd v dd +0.1 v v ol output level, low (i/o) 0.15 v cc v output level, low (i/ouc) i ol =1ma 0.3 v v ih input level, high (i/o) 0.6 v cc v cc +0.30 v input level, high (i/ouc) 1.8 v dd + 0.3 v v il input level, low (i/o) -0.15 0.2 v cc v input level, low (i/ouc) -0.3 0.8 v v inact output voltage when outside of session i ol = 0 0.1 v i ol = 1ma 0.3 v i leak input leakage v ih = v cc 10 a i il input current, low v il = 0 0.65 ma i shortl short circuit output current for output low, shorted to v cc through 33 15 ma i shorth short circuit output current for output high, shorted to ground through 33 15 ma t r , t f output rise time, fall times c l = 80pf, 10% to 90%. 100 ns t ir , t if input rise, fall times 1 s r pu internal pull-up resistor output stable for >400ns 8 11 14 k fd max maximum data rate 1 mhz t fdio delay, i/o to i/ouc, i/ouc to i/o, (respectively falling edge to falling edge and rising edge to rising edge) edge from master to slave, measured at 50% 60 100 200 ns t rdio 15 ns c in input capacitance 10 pf downloaded from: http:///
ds_8014r_012 73s8014r data sheet rev. 1.0 11 symbol parameter condition min nom max unit reset and clock for card interface, rst, clk v oh output level, high i oh =-200 a 0.9 v cc v cc v v ol output level, low i ol =200 a 0 0.15 v cc v v inact output voltage when outside of session i ol = 0 0.1 v i ol = 1ma 0.3 v i rst_lim output current limit, rst 30 ma i clk_lim output current limit, clk 70 ma clk sr3v clk slew rate vcc = 3v 0.3 v/ns clk sr5v clk slew rate vcc = 5v 0.5 v/ns t r , t f output rise time, fall time c l = 35pf for clk, 10% to 90% 8 ns c l = 200pf for rst, 10% to 90% 100 ns duty cycle for clk c l =35pf, f clk 20mhz 45 55 % 2.5 characteristics: digital signals table 6 lists the 73s8014r digital signals characteristics. table 6: digital signals characteristics symbol parameter condition min nom max unit digital i/o except for xtalin and xtalout v il input low voltage -0.3 0.8 v v ih input high voltage 1.8 v dd + 0.3 v v ol output low voltage i ol = 2ma 0.45 v v oh output high voltage i oh = -1ma v dd - 0.45 v r out pull-up resistor, off 16 20 24 k |i il1 | input leakage current gnd < v in < v dd -5 5 a downloaded from: http:///
73s8014r data sheet ds_8014r_012 12 rev. 1.0 oscillator (xtalin) i/o parameters v ilxtal input low voltage - xtalin -0.3 0.3 v dd v v ihxtal input high voltage - xtalin 0.7 v dd v dd +0.3 v i ilxtal input current - xtalin gnd < v in < v dd -30 30 a f max max freq. osc or external clock 27 mhz in external input duty cycle limit t r/f < 10% f in , 45% < clk < 55% 48 52 % 2.6 dc characteristics table 7 lists the 73s8014r dc characteristics. table 7: dc characteristics symbol parameter condition min nom max unit i dd 12 mhz xtal 2.7 7.0 ma ext clk, vdd = 2.7 C 3.6v, vcc off 1.7 ma supply current ext clk, vdd = 2.7 C 3.6v, vcc on 2.2 ma ext clk, vdd = 4.5 C 5.5v, vcc off 2.7 ma ext clk, vdd = 4.5 C 5.5v, vcc on 3 ma i pc supply current v cc on, icc=0 i/o, aux1, aux2=high, clock not toggling 450 700 a i pcoff v pc supply current when v cc = 0 cmdvcc high 345 650 a downloaded from: http:///
ds_8014r_012 73s8014r data sheet rev. 1.0 13 2.7 voltage fault detection circuits table 8 lists the 73s8014r voltage fault detection circuits. table 8: voltage fault detection circuits symbol parameter condition min nom max unit v ddf v dd fault (v dd voltage supervisor threshold) no external resistor on vddf_adj pin 2.15 2.4 v v ccf v cc fault (v cc voltage supervisor threshold) v cc = 5v 4.6 v v cc = 3v 2.7 v downloaded from: http:///
73s8014r data sheet ds_8014r_012 14 rev. 1.0 3 applications information this section provides general usage information fo r the design and implementation of the 73s8014r. the documents listed in related documentation provide more detailed information. 3.1 example 73s8014r schematics figure 3 shows a typical application schematic for the implementation of the 73s8014r. note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact teridian for the latest information. downloaded from: http:///
ds_8014r_012 73s8014r data sheet rev. 1.0 15 vdd c1 emv & iso7816=1uf clkdiv2_from_uc clk track should be routed far from rst, i/o, c4 and c8. notes: 1) vdd = 2.7v to 5.5v dc. 2) vpc = 4.75v to 5.5v dc 3) required if external clock from up is used. 4) required if crystal is used. y1, c2 and c3 must be removed if external clock is used. 5) r1 and r3 are external resistors that adjust the vdd fault voltage. can be left open. r1 rext1 see note 1 c6 100nf see note 2 vdd low esr (<100mohms) c1 should be placed near the sc connecter contact clkdiv1_from_uc 73s8014r 12 3 45 6 7 12 8 9 10 11 13 14 15 16 17 18 19 20 clkdiv1 clkdiv2 5v3v gnd vpc pres i/o test clk rst vcc vddf_adj cmdvcc rstin vdd gnd off xtalout xtalin i/ouc 5v/ #v _select_from_uc r3 rext2 see note 5 smart card connector 1 2 3 4 5 6 7 8 9 10 vcc rst clk c4 gnd vpp i/o c8 sw-1 sw-2 c4 100nf c5 10uf vpc off _interrupt_to_uc i/ouc_to/from_uc rstin_from_uc cmdvcc _from_uc see note 4 y1 crystal c2 22pf c3 22pf external_clock_from uc see note 3 - or - vdd r4 10k card detection switch is normally open 47k r2 figure 3: 73s8014r C typical application schematic downloaded from: http:///
73s8014r data sheet ds_8014r_012 16 rev. 1.0 3.2 system controller interface three digital inputs allow direct control of the card inte rface by the host. the 73s8014r is controlled as follows: ? pin cmdvcc : when asserted low, starts an activation sequence ? pin rstin: controls the card rst signal (when enabled by the sequencer) ? pin 5v/ #v : defines the card vcc voltage (5v when high and 3v when low) card clock frequency can be controlled by 2 digital inputs: ? clkdiv1 and clkdiv2 define the division rate for the cl ock frequency, from the input clock frequency (crystal or external clock) note: the maximum clk frequency is 20mhz. therefore, if using an input clock source greater than 20mhz, a divisor rate of 2x or higher must be used. interrupt output to the host: as long as the card is not activated, the off pin informs the host about the card presence only (low = no card in the reader). when cmdvcc is asserted low (card activation sequence requested from the host), low level on off means a fault has been detected (e.g. card removal during card session, voltage fault, or over-current fault) that automatically initiates a deactivation sequence. 3.3 power supply and voltage supervision the 73s8014r smart card interface ic incorporates a ld o voltage regulator. the voltage output is controlled by the digital input 5v/ #v of the 73s8014r. this regulator is able to provide either 3v or 5v card voltage from the power supply applied on the vpc pin. the voltage regulat or can provide a current of at least 65ma on vcc for both 3v and 5v that complies with emv 4.0. digital circuitry is powered by the power supply applied on the vdd pin. vdd also defines the voltage range to interface with the system controller. a card deactivation sequence is forced upon fault of any of this voltage supervisor. one voltage supervisor cons tantly monitors the vdd voltage. it is used to initialize the iso 7816-3 sequencer at power-on, and to deactivate the card at power-off or upon fault. the voltage threshold of the vdd voltage supervisor is internally set by default to 2.33v nominal. however, it may be desirable, in some applications, to modify this threshold value. the pi n vddf_adj is used to connect an external resistor r ext to ground to change the vdd fault voltage to another value, v ddf . the resistor value is defined as follows: r ext = 56k ? /(v ddf - 2.33) an alternative (more accurate) method of adjusting the v dd fault voltage is to use a resistive network of r3 from the pin to supply and r1 from the pin to ground (see figure 3 ). in order to set the new threshold voltage, the equivalent resistance must be determined. this re sistance value will be designated kx. kx is defined as r1/(r1+r3). kx is calculated as: kx = (2.789 / v th ) - 0.6125 where v th is the desired new threshold voltage. to determine the values of r1 and r3, use the following formulas. r3 = 24000 / kx r1 = r3*(kx / (1 C kx)) taking the example above, where a v dd fault threshold voltage of 2.7v is desired, solving for kx gives: ? kx = (2.789 / 2.7) - 0.6125 = 0.42046. solving for r3 gives: ? r3 = 24000 / 0.42046 = 57080. solving for r1 gives: ? r1 = 57080 *(0.42046 / (1 C 0.42046)) = 41412. using standard 1 % resistor values gives r3 = 57.6k and r1 = 42.4k . these values give an equivalent resist ance of kx = 0.4228, a 0.6% error. if the 2.33v default threshold is used, this pin must be left unconnected. downloaded from: http:///
ds_8014r_012 73s8014r data sheet rev. 1.0 17 3.4 card power supply the card power supply is internally provided by t he ldo regulator, and controlle d by the digital iso 7816-3 sequencer. card voltage selection on the 73s80 14r is carried out by the digital input 5v/ #v . choice of the vcc capacitor: depending on the application, the requirements in terms of both vcc minimum voltage and transient currents that the interface must be able to provide to the card are di fferent. an external capacitor must be connected between the vcc pin and to the card ground in order to guaran tee stability of the ldo regulator, and to handle the transient requirements. the type of capacitor should be an x5r/x7r with ers<100 m . 3.5 on-chip oscillator and card clock the 73s8014r device ha s an on-chip oscillator that c an generate the smart card cloc k using an external crystal (connected between the pins xtalin and xtalout) to set the oscillator frequency. when the clock signal is available from another source, it can be connected to the pin xtalin, and the pin xtalout should be left unconnected. the card clock frequency may be chosen between 4 different division rates, defined by digital inputs clkdiv 1 and clkdiv 2, as per the following table: clkdiv1 clkdiv2 clk max xtalin 0 0 1/8 xtalin 27mhz 0 1 ? xtalin 27mhz 1 0 xtalin 20mhz 1 1 ? xtalin 27mhz downloaded from: http:///
73s8014r data sheet ds_8014r_012 18 rev. 1.0 3.6 activation sequence the 73s8014r smart card interface ics have an inter nal 10ms delay on the application of vdd where vdd > v ddf . no activation is allowed during this 10ms period. the cmdvcc (edge triggered) signal must then be set low to activate the card. in order to initiate acti vation, the card must be present; there can be no vdd fault. the following steps show the activation sequence and t he timing of the card control signals when the system controller sets cmdvcc low while the rstin is low: - cmdvcc is set low at t 0 . - vcc will rise to the selected level and then the internal vcc control circuit checks the presence of vcc at the end of t 1 . in normal operation, the voltage vcc to the card becomes valid before t 1 . if vcc is not valid at t 1 , the off goes low to report a fault to the system controller, and vcc to the card is shut off. - turn i/o to reception mode at t 2 . - clk is applied to the card at t 3 . - rst is a copy of rstin after t 3 . cmdvcc vcc i/o clk rstin t 1 t 2 t 3 rst t 0 t 1 = 0.510 ms (timing by 1.5mhz internal oscillator) t 2 = 1.5 s, i/o goes to reception state t 3 = >0.5 s, clk starts, rst to become the copy of rstin figure 4: activation sequence C rstin low when cmdvcc goes low the following steps show the activation sequence and t he timing of the card control signals when the system controller pulls the cmdvcc low while the rstin is high: - cmdvcc is set low at t 0 . - vcc will rise to the selected level and then the internal vcc control circuit checks the presence of vcc at the end of t 1 . in normal operation, the voltage vcc to the card becomes valid before t 1 . if vcc is not valid at t 1 , the off goes low to report a fault to the system controller, and vcc to the card is shut off. - at the fall of rstin at t 2 , clk is applied to the card - rst is a copy of rstin after t 2 . downloaded from: http:///
ds_8014r_012 73s8014r data sheet rev. 1.0 19 cmdvcc vcc i/o clk rstin t 1 t 2 t 0 rst t 1 = 0.510 ms (timing by 1.5mhz internal oscillator, i/o goes to reception state) t 2 = rstin goes low and clk becomes active t 3 = > 0.5 s, clk active, rst to become the copy of rstin figure 5: activation sequence C rstin high when cmdvc c goes low 3.7 deactivation sequence deactivation is initiated either by the system controller by setting the cmdvcc high, or automatically in the event of hardware faults. hardware faults are over-current, v dd fault, vcc fault, and card extraction during the session. the following steps show the deactivation sequence and t he timing of the card control signals when the system controller sets the cmdvcc high or off goes low due to a fault or card removal: - rst goes low at the end of t 1 . - clk is set low at the end of t 2 . - i/o goes low at the end of t 3 . out of reception mode. - vcc is shut down at the end of time t 4 . after a delay t 5 (discharge of the vcc c apacitor), vcc is low. rst clk i/o vcc t 1 t 2 t 3 t 4 t 5 cmdvcc -- or -- off t 1 = > 0.5 s, timing by 1.5mhz internal oscillator t 2 = > 7.5 s t 3 = > 0.5 s t 4 = > 0.5 s t 5 = depends on vcc filter capacitor. figure 6: deactivation sequence downloaded from: http:///
73s8014r data sheet ds_8014r_012 20 rev. 1.0 3.8 fault detection and off there are two different cases that t he system controller can monitor the off signal: to query regarding the card presence outside card sessions, or for fault detection during card sessions. outside a card session: in this condition, cmdvcc is/are always high, off is low if the card is not present, and high if the card is present. because it is outside a card session, any fault detection will not act upon the off signal. no deactivation is required during this time. during a card session: cmdvcc is/are always low, and off falls low if the card is extracted or if any fault detection is detected. at the same time that off is set low, the sequencer st arts the deactivation process. figure 7 shows the timing diagram for the signals cmdvcc , pres, and off during a card session and outside the card session: e the card session: pres off cmdvcc vcc pres off cmdvcc vcc outside card session within card session off is low by card extracted off is low by any fault wi thi n card session figure 7: timing diagram C management of the interrupt line off 3.9 i/o circuitry and timing the state of the i/o pin is low after power on reset and it goes high when the activation sequencer turns on the i/o reception state. see the activation sequence section for details on when the i/o reception is enabled. the state of i/ouc is high after power on reset. within a card session and when the i/o reception state is turned on, the first i/o line on which a falling edge is detected becomes the input i/o line and the other becomes the output i/o line. when the input i/o line rising edge is detected then both i/o lines return to their neutral state. figure 8 shows the state diagram of how the i/o and i/ouc lines are managed to become input or output. the delay between the i/o signals is shown in figure 9 . downloaded from: http:///
ds_8014r_012 73s8014r data sheet rev. 1.0 21 neutral state i/ouc in i/o reception i/oicc in no yes no no no yes no yes i/o & not i/ouc i/ouc & not i/o i/ouc i/o yes yes figure 8: i/o and i/ouc state diagram i/o i/ouc t i/o_hl t i/o_lh t i/ouc_hl t i/ouc_lh delay from i/o to i/ouc: t i/o_hl = 100ns t i/o_lh = 25ns delay from i/ouc to i/o: t i/ouc_hl = 100ns t i/ouc_lh = 25ns figure 9: i/o C i/ouc delays C timing diagram downloaded from: http:///
73s8014r data sheet ds_8014r_012 22 rev. 1.0 4 equivalent circuits this section provides illustrations of circuits equi valent to those described in the pinout section. pin vdd strong nfet data from circuit output disable 20k esd figure 10: open drain type C off pin esd to internal circuits figure 11: power input/output circuit, vdd, vpc, vcc downloaded from: http:///
ds_8014r_012 73s8014r data sheet rev. 1.0 23 clk pin vcc very strong pfet very strong nfet from circuit esd esd figure 12: smart card clk driver circuit rst pin vcc strong pfet strong nfet from circuit esd esd figure 13: smart card rst driver circuit downloaded from: http:///
73s8014r data sheet ds_8014r_012 24 rev. 1.0 400ns delay io pin vcc strong pfet strong nfet rl=11k from circuit cmos to circuit esd esd figure 14: smart card io interface circuit 400ns delay uc pin vdd strong pfet strong nfet rl=11k from circuit cmos to circuit esd esd figure 15: smart card iouc interface circuit downloaded from: http:///
ds_8014r_012 73s8014r data sheet rev. 1.0 25 pin vdd ttl to circuit pull-up disable very weak pfet esd very weak nfet pull-down enable esd note: pins cmdvcc ,5v/ #v , clkdiv1 and clkdiv2 have the pull-up enabled. pins rstin, clkin, pres have the pull-down enabled. figure 16: general input circuit pin pin vdd xtalin xtalout enableb enable esd esd esd esd very weak fets strong nfet strong nfet strong pfet strong pfet figure 17: oscilla tor circuit downloaded from: http:///
73s8014r data sheet ds_8014r_012 26 rev. 1.0 esd pin vdd vdd fault detection vref = 1.400v pin + - r = 60k r = 40k r = 0.4k (approx.) vddf_ adj esd esd figure 18: vddf_adj downloaded from: http:///
ds_8014r_012 73s8014r data sheet rev. 1.0 27 5 mechanical drawing 0.5050(12.82) 0.4065(10.32) 0.2960(7.51) .0125(.318) + .003(.076) - .004(.101) + .005(.127) - .009(.228) base plane seating plane 0.5050(12.82) 0.0082 (.208) 0.1000 (2.54) + .004(.101) - .007(.178) 0.016(.406) 0.050(1.27) typ + .004(.101) - .003(.076) + .005(.127) - .009(.228) 0 . 0 1 ( .2 5 4 ) + . 0 0 2 5 ( . 0 6 3 4 ) - . 0 0 1 0 ( . 0 2 5 4 ) detail a .033 (.838) detail a 0 - 8 .017(.431) figure 19: mechanical drawing 20-pin so package inches (mm) downloaded from: http:///
73s8014r data sheet ds_8014r_012 28 rev. 1.0 6 ordering information table 9 lists the order numbers and packaging marks used to identify 73s8014r products. table 9: order numbers and packaging marks part description order number packaging mark 73s8014r 20-pin lead-free 73s8014r-il/f 73s8014r 73s8014r 20-pin lead-free tape / reel 73s8014r-ilr/f 73s8014r 7 related documentation the following 73s8014r document is available from teridian semiconductor corporation: 73s8014r/rn/rt 20so demo board user manual 8 contact information for more information about teridian semiconductor produc ts or to check the availability of the 73s8014r, contact us at: 6440 oak canyon road irvine, ca 92618-5201 telephone: (714) 508-8800 fax: (714) 508-8878 email: scr.support@teridian.com for a complete list of worldwide sales offices, go to http://www.teridian.com . downloaded from: http:///
ds_8014r_012 73s8014r data sheet rev. 1.0 29 revision history revision date description 1.0 9/3/2008 first publication. ? 2008 teridian semiconductor corporation. all rights reserved. teridian semiconductor corporation is a registered trademark of teridian semiconductor corporation. simplifying system integration is a trademark of teridian semiconductor corporation. all other trademarks are the proper ty of their respective owners. teridian semiconductor corporation makes no warranty for the use of its products, other than expressly contained in the companys warranty detailed in the te ridian semiconductor corporation standard terms and conditions. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed her ein at any time without notice and does not make any commitment to update the information contained herein. accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest ve rsion on http://www.teridian.com or by checking with your sales representative. teridian semiconductor corp., 6440 oak canyon rd., suite 100, irvine, ca 92618 tel (714) 508-8800, fax (714) 508-8877, http://www.teridian.com downloaded from: http:///

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