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features ? low voltage and standard voltage operation: 2.7 (v cc = 2.7v to 5.5v) ? internally organized 128 x 8 ? two-wire serial interface ? bidirectional data transfer protocol ? 1 mhz compatibility ? 4-byte page write mode ? self-timed write cycle (5 ms max) ? high reliability ? endurance: 1 million write cycles ? data retention: 100 years ? automotive grade and lead-free/halogen-free devices available ? 8-lead jedec soic and 8-lead tssop packages description the at24c11 provides 1024 bits of serial electrically erasable and programmable read only memory (eeprom) organized as 128 words of 8 bits each. the device is optimized for use in many automotive applications where low power and low voltage operation are essential. the at24c11 is available in space saving 8-lead jedec soic and 8-lead tssop packages and is ac cessed via a two-wire serial interface. in addition, the entire family is av ailable in 2.7v (2.7v to 5.5v). table 0-1. pin configuration pin name function nc no connect sda serial data scl serial clock input test test input (gnd or vcc) two-wire automotive temperature serial eeprom 1k (128 x 8) at24c11 note: not recommended for new design; please refer to at24c01b automotive datasheet. rev. 5093e?seepr?8/07 8-lead soic 1 2 3 4 8 7 6 5 nc nc nc gnd vcc test scl sda 8-lead tssop 1 2 3 4 8 7 6 5 nc nc nc gnd vcc test scl sda
2 5093e?seepr?8/07 at24c11 figure 0-1. block diagram 1. pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negative edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open-drain driven and may be wire-ored with any number of other open-drain or open collector devices. absolute maximum ratings* operating temperature..................................?55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .....................................?65 c to +150 c voltage on any pin with respect to ground .................................... ?1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma s ta rt s top logic vcc gnd wp s cl s da a 2 a 1 a 0 s erial control logic en h.v. pump/timing eeprom data recovery s erial mux x dec d out /ack logic comp load inc data word addr/counter y dec r/w d out d in load device addre ss comparator
3 5093e?seepr?8/07 at24c11 2. memory organization at24c11, 1k serial eeprom: internally organized with 32 pages of 4 bytes each. the 1k requires a 7-bit data word address for random word addressing. note: 1. v il min and v ih max are reference only and are not tested. table 2-1. pin capacitance applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +2.7v to +5.5v symbol test condition max units condition c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a0, a1, a2, scl) 6 pf v in = 0v table 2-2. dc characteristics applicable over recommended operating range from: t ae = ? 40 c to +125 c, v cc = +2.7v to +5.5v (unless otherwise noted) symbol parameter test co ndition min typ max units v cc1 supply voltage 2.7 5.5 v v cc2 supply voltage 4.5 5.5 v i cc supply current v cc = 5.0v read at 100 khz 0.4 1.0 ma i cc supply current v cc = 5.0v write at 100 khz 2.0 3.0 ma i sb1 standby current v cc = 1.8v v in = v cc or v ss 0.6 3.0 a i sb2 standby current v cc = 2.5v v in = v cc or v ss 1.4 4.0 a i sb3 standby current v cc = 2.7v v in = v cc or v ss 1.6 4.0 a i sb4 standby current v cc = 5.0v v in = v cc or v ss 8.0 18.0 a i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il input low level (1) ?0.6 v cc 0.3 v v ih input high level (1) v cc 0.7 v cc + 0.5 v v ol2 output low level v cc = 3.0v i ol = 2.1 ma 0.4 v v ol1 output low level v cc = 1.8v i ol = 0.15 ma 0.2 v
4 5093e?seepr?8/07 at24c11 note: 1. this parameter is ensured by characterization only. 3. device operation clock and data transitions: the sda pin is normally pul led high with an external device. data on the sda pin may change only during scl low time periods (see figure 3-3 on page 6 ). data changes during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (see figure 3-4 on page 6 ). stop condition: a low-to-high transition of sda with sc l high is a stop condition which ter- minates all communications. after a read se quence, the stop comm and will place the eeprom in a standby power mode (see figure 3-4 on page 6 ). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. any device on the sy stem bus receiving data (when communicating with the eeprom) must pull the sd a bus low to acknowledge that it has successfully received each word. this must happen during the ninth clock cycle after each word received and after all other system devices have freed the sda bu s. the eeprom will likewise acknowledge by pull- ing sda low after receiving each address or data word (see figure 3-5 on page 6 ). table 2-3. ac characteristics applicable over recommended operating range from t a = ? 40 c to +125 c, v cc = +2.7v to +5.5v, cl = 1 ttl gate and 100 pf (unless otherwise noted) symbol parameter 2.7v, 5.0v units min max f scl clock frequency, scl 1000 khz t low clock pulse width low 0.4 s t high clock pulse width high 0.4 s t aa clock low to data out valid 0.05 0.55 s t buf time the bus must be free before a new transmission can start (1) 0.5 s t hd.sta start hold time 0.25 s t su.sta start set-up time 0.6 s t hd.dat data in hold time 0 s t su.dat data in set-up time 100 ns t r inputs rise time (1) 0.3 s t f inputs fall time (1) 100 ns t su.sto stop set-up time 0.25 s t dh data out hold time 50 ns t wr write cycle time 5 ms endurance (1) 5.0v, 25c, page mode 1m write cycles
5 5093e?seepr?8/07 at24c11 standby mode: the at24c11 features a low power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the stop bit and the completion of any internal operations. memory reset: after an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) clock up to 9 cycles, (b) look for sda high in each cycle while scl is high and then (c) create a start condition as sda is high. figure 3-1. bus timing scl: serial clock, sda: serial data i/o figure 3-2. write cycle timing scl: serial clock, sda: serial data i/o note: 1. the write cycle time t wr is the time from a valid stop co ndition of a write sequence to the e nd of the internal clear/write cycle. s cl s da in s da out t f t high t low t low t r t aa t dh t buf t s u. s to t s u.dat t hd.dat t hd. s ta t s u. s ta t wr (1) stop condition start condition wordn ack 8th bit s cl s da
6 5093e?seepr?8/07 at24c11 figure 3-3. data validity figure 3-4. start and stop definition figure 3-5. output acknowledge s da s cl data s table data s table data change s da s cl s ta rt s top s cl data in data out s tart acknowledge 9 8 1
7 5093e?seepr?8/07 at24c11 4. write operations byte write: following a start condition, a write oper ation requires a 7-bit data word address and a low write bit. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8-bit data word. follo wing receipt of the 8-bit data word, the eeprom will output a zero and the addressin g device, such as a microcontroller, must terminate the write sequence with a stop condit ion. at this time the eeprom en ters an internally -timed write cycle to the nonvolatile memory. all inputs are disabled during this write cycle, t wr , and the eeprom will not respond until the write is complete (see refer to figure 5-1 on page 8 ). page write: the at24c11 is capable of a 4-byte page write. a page write is initiated the same as a byte write but the microcontro ller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to three more data words. the eeprom will respond with a zero after each data word received. the microcontroller must ter- minate the page write sequence with a stop condition (see figure 5-2 on page 8 ). the data word address lower 2 bits are interna lly incremented following th e receipt of each data word. the higher five data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the fol- lowing byte is placed at the beginning of the same page. if more than four data words are transmitted to the eeprom, the data word a ddress will ?roll over? and previous data will be overwritten. access to 1 additional page is available upon request. acknowledge polling: once the internally-timed write cycle has started and the eeprom inputs are disabled, ackno wledge polling can be initiate d. this involves sending a start condition followed by the device address wo rd. the read/write bit is representative of the operation desired. only if th e internal write cycle has comp leted will the eeprom respond with a zero allowing the read or write sequence to continue. 5. read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are two read operations: byte read and sequential read. byte read: a byte read is initiated with a start cond ition followed by a 7-bi t data word address and a high read bit. the at24c11 will respond wi th an acknowledge and then serially output 8 data bits. the microcontroller does not respond with a zero but does generate a following stop condition (see figure 5-3 on page 8 ). sequential read: sequential reads are initiated the same as a byte read. after the micro- controller receives an 8-bit data word, it re sponds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will ?ro ll over? and the sequential read will cont inue. the sequential read operation is terminated when the microcontroller does not respond with an input zero but does generate a following stop condition (see figure 5-4 on page 8 ).
8 5093e?seepr?8/07 at24c11 figure 5-1. byte write figure 5-2. page write figure 5-3. byte read figure 5-4. sequential read
9 5093e?seepr?8/07 at24c11 at24c11 ordering information ordering code package operation range at24c11n-10sq-2.7 at24c11-10tq-2.7 8s1 8a2 lead-free/halogen-free/ automotive temperature (?40 c to 85 c) package type 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) options ? 2.7 low-voltage (2.7v to 5.5v)
10 5093e?seepr?8/07 at24c11 packaging information 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
11 5093e?seepr?8/07 at24c11 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
12 5093e?seepr?8/07 at24c11 revision history doc. rev. date comments 5093e 8/2007 updated to new template updated common figures added note to first page 5093d 1/2007 removed pdip package offering removed pb parts 5093c 9/2006 revision history implemented; removed ?preliminary? status from datasheet.
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