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august 2008 rev 4 1/51 1 m41t93 serial spi bus rtc with battery switchover features ultra-low battery supply current of 365 na factory calibrated accuracy 5 ppm guaranteed after 2 reflows (sox18) ? much better accuracies achievable using built-in programmable analog and digital calibration circuits 2.0 v to 5.5 v clock operating voltage counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century automatic switchover and reset output circuitry (fixed reference) ?m41t93s: v cc = 3.0 v to 5.5 v (2.85 v v rst 3.00 v) ?m41t93r: v cc = 2.7 v to 5.5 v (2.55 v v rst 2.70 v) ?m41t93z: v cc = 2.38 v to 5.50 v (2.25 v v rst 2.38 v) compatible with spi bus serial interface (supports spi mode 0 [cpol = 0, cpha = 0]) programmable alarm with interrupt function (valid even during battery back-up mode) optional 2 nd programmable alarm available square wave output (defaults to 32 khz on power-up) reset (rst ) output watchdog timer programmable 8-bit counter/timer 7 bytes of battery-backed user sram battery low flag power-down time stamp (ht bit) low operating current of 80 a oscillator stop detection battery or supercap? backup operating temperature of ?40c to +85c package options include: ? a 16-lead qfn or an 18-lead embedded crystal soic rohs compliance: lead-free components are compliant with the rohs directive sox18 (my, 18-pin, 300 mil soic qfn16, 4 mm x 4 mm (qa) 1 18 with embedded crystal) www.st.com
contents m41t93 2/51 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.1 serial data output (sdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.2 serial data input (sdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.3 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.4 chip enable (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 spi bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 read and write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 data retention and battery switchover (v so = v rst ) . . . . . . . . . . . . . . . . 15 2.4 power-on reset (t rec ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 clock/control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 real-time clock accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.1 digital calibration (periodic counter correction) . . . . . . . . . . . . . . . . . . . 20 3.4.2 analog calibration (programmable load capacitance) . . . . . . . . . . . . . . 22 3.5 setting the alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6 optional second programmable alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.7 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.8 8-bit (countdown) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.8.1 ti /tp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.8.2 tf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.8.3 tie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.8.4 te . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.8.5 td1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.9 square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.10 battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.11 century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
m41t93 contents 3/51 3.12 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.13 oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.14 oscillator fail interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.15 initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.16 otp bit operation (sox18 package only) . . . . . . . . . . . . . . . . . . . . . . . . 35 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
list of tables m41t93 4/51 list of tables table 1. signal name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. digital calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5. analog calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 6. alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 7. timer control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8. interrupt operation (bit ti /tp = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9. timer source clock frequency selection (244.1 s to 4.25 hrs). . . . . . . . . . . . . . . . . . . . . . 31 table 10. timer countdown value register bits (addr 11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 11. square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. initial power-on default values (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 14. initial power-up default values (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 15. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 16. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 17. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 19. crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 20. oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 21. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 22. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 23. qfn16 ? 16-lead, quad, flat package, no lead, 4 x 4 mm body, mech. data . . . . . . . . . . . 45 table 24. sox18 ? 18-lead plastic so, 300 mils, embedded crystal, pkg. mech. data . . . . . . . . . . . 47 table 25. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 26. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
m41t93 list of figures 5/51 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. qfn16 (qa) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. sox18 (my) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. data and clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. internal load capacitance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. clock accuracy vs. on-chip load capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 12. clock divider chain and calibration circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 13. crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 14. alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 15. backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 16. measurement ac i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 17. i cc2 vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 18. power down/up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 19. input timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 20. output timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 21. qfn16 ? 16-lead, quad, flat package, no lead, 4 x 4 mm body size, outline . . . . . . . . . . . 44 figure 22. qfn16 ? 16-lead, quad, flat, no lead, 4 x 4 mm, recommended footprint . . . . . . . . . . . . . 46 figure 23. 32 khz crystal + qfn16 vs. vsoj20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 24. sox18 ? 18-lead plastic small outline, 300 mils, embedded crystal . . . . . . . . . . . . . . . . . 47
description m41t93 6/51 1 description the m41t93 is a low-power serial spi bus real-time clock with a built-in 32.768 khz oscillator (external crystal-controlled for the qfn16 package, and emb edded crystal for the sox18 package). eight bytes of the register map (see table3 on page18 ) are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. an additional 17 bytes of the register map provide status/control of the two alarms, watchdog, 8-bit counter, and square wave functions. an additional seven bytes are made available as user sram. addresses and data are transferred serially via a serial spi bus-compatible interface. the built-in address register is incremented automatically after each write or read data byte. the m41t93 has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. the energy needed to sustain the clock operations can be supplied by a small lithium button battery when a power failure occurs. functions available to the user include a non-volatile, time-of-day clock/calendar, alarm interrupt, watchdog timer, programmable 8-bit counter, and square wave outputs. the eight clock address locations contain the century, year, month, date, day, hour, minute, second, and tenths/hundredths of a second in 24-hour bcd format. corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. the m41t93 is supplied in either a qfn16 or an sox18 (my), 300mil soic which includes an embedded 32 khz crystal. the sox18 package requires only a user-supplied battery to provide non-volatile operation.
m41t93 description 7/51 figure 1. logic diagram 1. for qfn16 package only 2. defaults to 32 khz on power-up 3. open drain table 1. signal name symbol description xi (1) 1. for qfn16 package only 32 khz oscillator input xo (1) 32 khz oscillator output irq /ft/out interrupt /frequency te st/output driver (open drain) sqw (2) 2. defaults to 32 khz on power-up 32 khz programmable square wave output rst power-on reset output (open drain) e chip enable sdi serial data address input sdo serial data address output scl serial clock input v bat battery supply voltage (tie v bat to v ss if no battery is connected.) du (3) 3. do not use (must be tied to v cc ) do not use v cc supply voltage v ss ground sdi v cc v ss v bat scl rst (3) e irq/out/ft (3) sqw (2) sdo xi (1) xo (1) ai11818
description m41t93 8/51 figure 2. qfn16 (qa) connections 1. open drain output 2. defaults to 32 khz on power-up figure 3. sox18 (my) connections 1. nf pins must be tied to v ss . pins 2 and 3, and 16 and 17 are internally shorted together. 2. open drain output 3. do not use (must be tied to v cc ) 4. defaults to 32khz on power-up 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 xo xi e v ss nc nc rst (1) nc sqw (2) nc v bat v cc sdo scl sdi irq/ft/out (1) ai11819 m41t93 8 2 3 4 5 6 7 9 12 11 10 18 17 16 15 14 13 1 nf (1) du (3) sqw (4) nc rst (2) e scl sdi v ss v bat nf (1) nc v cc m41t93 irq/ft/out (2) nf (1) nf (1) nc sdo ai11820
m41t93 description 9/51 figure 4. block diagram 1. open drain output 2. v rst = v so = 2.93 v (s), 2.63 v (r), and 2.32 v (z) real time clock calendar alarm1 alarm2 watchdog oscillator fail circuit square wave output driver 8 bits of otp 8-bit counter frequency test user sram (7 bytes) irq/ft/out (1) sqw rst (1) internal power sqwe a1ie e scl v cc ofie compare t rec timer sdo sdi spi interface 32khz oscillator v bat crystal xi xo v rst /v so (2) ai11821 write protect v cc < v rst ft out tie
description m41t93 10/51 figure 5. hardware hookup 1. open drain output 2. cpol (clock polarity) and cpha (clock phase) are bits that may be set in the spi control register of the mcu. figure 6. data and clock timing note: supports spi mode 0 (cpol = 0, cpha = 0) only. ai11822 v cc reset input (st6, st7, st9, st10, others) scl (2) spi interface with (cpol = 0, cpha = 0) sdi sdo cs 32khz clkin xo xi m41t93 mcu v ss v bat irq/ft/out (1) rst (1) sdi sqw sdo scl v cc int e v cc table 2. function table mode e scl sdi sdo disable reset h input disabled input disabled high z write l data bit latch high z read l x next data bit shift (1) 1. sdo remains at high z until eight bits of data are ready to be shifted out during a read. ai04630 ai04631 ai04632 c msb lsb cpha sdi 0 cpol 0 msb lsb sdo
m41t93 description 11/51 1.1 spi signal description 1.1.1 serial data output (sdo) the output pin is used to transfer data serially out of the memory. data is shifted out on the falling edge of the serial clock. 1.1.2 serial data input (sdi) the input pin is used to transfer data serially into the device. instructions, addresses, and the data to be written, are each received this way. input is latched on the rising edge of the serial clock. 1.1.3 serial clock (scl) the serial clock provides the timing for the serial interface (as shown in figure 19 on page 41 and figure 20 on page 41 ). the w/r bit, addresses, or data are latched, from the input pin, on the rising edge of the clock input. the output data on the sdo pin changes state after the falling ed ge of the clock input. the m41t93 can be driven by a microcontroller with its spi peripheral running in only mode 0: (cpol, cpha) = (0,0). for this mode, input data (sdi) is latched in by the low-to-high transition of clock scl, and output data (sdo) is shifted out on the high-to-low transition of scl (see ta b l e 2 o n page 10 and figure 6 on page 10 ). 1.1.4 chip enable (e ) when e is high, the memory device is deselected, and the sdo output pin is held in its high impedance state. after power-on, a high-to-low transition on e is required prior to the start of any operation.
operation m41t93 12/51 2 operation the m41t93 clock operates as a slave device on the spi serial bus. each memory device is accessed by a simple serial interface that is spi bus-compatible. the bus signals are scl, sdi, and sdo (see table 1 on page 7 and figure 5 on page 10 ). the device is selected when the chip enable input (e ) is held low. all instructions, addresses and data are shifted serially in and out of the chip. the most significant bit is presented first, with the data input (sdi) sampled on the first rising edge of the clock (scl) after the chip enable (e ) goes low. the 32 bytes contained in the device can then be accessed sequentially in the following order: the m41t93 clock continually monitors v cc for an out-of tolerance condition. should v cc fall below v rst , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at th is time to prevent erroneous data from being written to the device from a an out-of-tolerance system. the power input will also be switched from the v cc pin to the external battery when v cc falls below the battery back-up switchover voltage (v so = v rst ). at this time the clock registers will be maintained by th e battery supply. as sys tem power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protection continues until v cc reaches v pfd (min) plus t rec (min). for more information on battery storage life refer to application note an1012. 1 tenths/hundredths of a second register 2 seconds register 3 minutes register 4 century/hours register 5 day register 6 date register 7 month register 8 year register 9 digital calibration register 10 watchdog register 11-15 alarm1 registers 16 flags register 17 timer value register 18 timer control register 19 analog calibration register 20 square wave register 21-25 alarm2 registers 26-32 user ram
m41t93 operation 13/51 2.1 spi bus characteristics the serial peripheral interface (spi) bus is intended for synchronous communication between different ics. it consists of four signal lines: serial data input (sdi), serial data output (sdo), serial clock (scl) and a chip enable (e ). by definition a device that gives out a message is called ?transmitter,? the receiving device that gets the message is called ?receiver.? th e device that controls the message is called ?master.? the devices that are controlled by the master are called ?slaves.? the e input is used to initiate and terminate a data transfer. the scl input is used to synchronize data transfer between the master (micro) and the slave (m41t93) device. the scl input, which is generated by the microcontroller, is active only during address and data transfer to any device on the spi bus (see figure 5 on page 10 ). the m41t93 can be driven by a microcontroller with its spi peripheral running in only mode 0: (cpol, cpha) = (0,0). for this mode, input data (sdi) is latched in by the low-to-high transition of clock scl, and output data (sdo) is shifted out on the high-to-low transition of scl (see ta b l e 2 and figure 6 on page 10 ). there is one clock for each bit transferred. address and data bits are transferred in groups of eight bits. due to memory size the second mo st significant address bit is a ?don?t care? (address bit 6). 2.2 read and write cycles address and data are shifted msb first into the serial data input (sdi) and out of the serial data output (sdo). any data transfer considers the first bit to define whether a read or write will occur. this is followed by seven bits defining the address to be read or written. data is transferred out of the sdo for a read operation and into the sdi for a write operation. the address is always the second through the eighth bit written after the enable (e ) pin goes low. if the first bit is a '1,' one or more write cycles will occur. if the first bit is a '0,' one or more read cycles will occur (see figure 7 and figure 8 on page 14 ). data transfers can occur one byte at a time or in multiple byte burst mode, during which the address pointer will be automatica lly incremented. for a single byte transfer, one byte is read or written and then e is driven high. for a multiple byte transfer all that is required is that e continue to remain low. under this condit ion, the address pointer will continue to increment as stated previously . incrementing will continue until the device is deselected by taking e high. the address will wrap to 00h after incrementing to 3fh. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). although the clock continues to maintain the correct time, this will prevent updates of time and date during either a r ead or write of these address locations by the user. the update will resume eith er due to a deselect co ndition or when the pointer increments to an non-clock or ram address (08h to 1fh). note: this is true both in read and write mode.
operation m41t93 14/51 figure 7. read mode sequence figure 8. write mode sequence scl sdi e sdo 2 high impedance w/r bit 7 bit address 0 msb data out msb msb (byte 1) data out (byte 2) 1 12 13 14 15 16 17 22 3 4 5 6 7 8 9 2 0 1 3 4 5 6 7 2 0 1 3 4 5 6 7 2 0 1 3 4 5 6 7 ai04635 scl sdi e sdo 7 2 high impedance 0 data byte 7 bit addr w/r bit 10 15 msb msb 6 6 5 5 4 4 3 3 21 1 0 65 4321 0 7 7 7 8 9 ai04636
m41t93 operation 15/51 2.3 data retention and battery switchover (v so = v rst ) once v cc falls below the switchover voltage (v so = v rst ), the device automatically switches over to the battery and powers down into an ultra low current mode of operation to preserve battery life. if v bat is less than, or greater than v rst , the device power is switched from v cc to v bat when v cc drops below v rst (see figure 18 on page 40 ). at this time the clock registers and user ram will be mainta ined by the attach ed battery supply. when it is powered back up, the device switches back from battery to v cc at v so + hysteresis. when v cc rises above v rst , it will recognize the inpu ts. for more information on battery storage life refer to application note an1012. 2.4 power-on reset (t rec ) the m41t93 continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst output pulls low (open drain) and remains low after power-up for t rec (210ms typical) after v cc rises above v rst (max). note: the t rec period does not affect the rtc operation. write protect only occurs when v cc is below v rst . when v cc rises above v rst , the rtc will be selectable immediately. only the rst output is affected by the t rec period. the rst pin is an open drain output and an appropriate pull-up resistor to v cc should be chosen to control the rise time.
clock operation m41t93 16/51 3 clock operation the m41t93 is driven by a quartz-contro lled oscillator with a nominal frequency of 32.768 khz. the accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the rtc. the 8-byte clock register (see table 3 on page 18 ) is used to both set the clock and to read the date and time from the clock, in binary coded decimal format. tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. bit d7 of register 01h contains the stop bi t (st). setting this bit to a '1' will cause the oscillator to stop. when reset to a '0' the os cillator restarts within one second (typical). note: upon initial power-up, the user should set the st bit to a '1,' then immediately reset the st bit to '0.' this provides an additional ?kick-start? to the oscillator circuit. bits d6 and d7 of clock register 03h (century/ hours register) contain the century bit 0 (cb0) and century bit 1 (cb1). bits d0 through d2 of register 04h contain the day (day of week). registers 05h, 06h, and 07h contain the date (day of month), month, and years. the ninth clock register is the digital calibration register, while the analog calibration register is found at address 12h (these are both described in the clock calibration section). bit d7 of register 09h (watchdog register) contains the o scillator fail interrupt en able bit (ofie). when the user sets this bit to '1 ,' any condition which sets t he oscillator fail bit (of) (see oscillator fail detection on page 34 ) will also generate an interrupt output. note: a write to any location within the first eight bytes of the clock register (00h-07h), including the st bit and cb0-cb1 bits will resu lt in an update of the system clock and a reset of the divider chain. this could result in an inadvertent change of the current time. these non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. the eight clock registers may be read one byte at a time, or in a sequential block. provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. if a clock address is being read, an update of the clock registers will be halted. this will prevent a trans ition of data during the read. 3.1 power-down time-stamp when a power failure occurs, the halt update bit (ht) will automatically be set to a ?1?. this will prevent the clock from updating the clock/control regi sters, and will allow the user to read the exact time of the powe r-down event. resetting the ht bit to a ?0? will allow the clock to update the clock/registers with the current time. for more information, see application note an1572. 3.2 clock/control register map the m41t93 offers 32 internal registers which contain clock, calibration (digital and analog), alarm 1 and 2, watchdog, flags, timer, and square wave. the clock registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as biport? timekeeper ? cells). the external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. the internal di vider (or clock) chain will be reset upon the
m41t93 clock operation 17/51 completion of a write to any clock address (0 0h to 07h). the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (0 0h to 07h). the update will resume either due to a stop condition or when the pointer increments to a non-clock address. clock and alarm registers store data in bcd format. calibration, timer, watchdog, and square wave bits are written in a binary format.
clock operation m41t93 18/51 table 3. clock/control register map (32 bytes) addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h cb1 cb0 10 hours hours (24-hour format) century/hours 0-3/00-23 04h 0 0 0 0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h 0 0 0 10m month month 01-12 07h 10 years year year 00-99 08h out ft dcs dc4 dc3 dc2 dc1 dc0 digital calibration 09h ofie bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah a1ie sqwe abe al1 10m alarm1month al1 month 01-12 0bh rpt14 rpt15 ai1 10 date alarm1 date al1 date 01-31 0ch rpt13 ht ai1 10 hour alarm1 hour al1 hour 00-23 0dh rpt12 alarm1 10 minutes alarm1 minutes al1 min 00-59 0eh rpt11 alarm1 10 seconds alarm1 seconds al1 sec 00-59 0fh wdf af1 af2 (1) 1. af2 will always read ?0? if the al2e bit is set to ?0?. bl tf of 0 0 flags 10h timer countdown value timer value 11h te ti /tp tie 0 0 0 td1 td0 timer control 12h acs ac6 ac5 ac4 ac3 ac2 ac1 ac0 analog calibration 13h rs3 rs2 rs1 rs0 0 0 al2e otp sqw 14h 0 0 0 al2 10m alarm2 month sram/al2 month 01-12 15h rpt24 rpt25 ai2 10 date ala rm2 month sram/al2 date 01-31 16h rpt23 0 ai2 10 hour alarm2 date sram/al2 hour 00-23 17h rpt22 alarm2 10 minutes alarm2 minutes sram/al2 min 00-59 18h rpt21 alarm2 10 seconds alarm2 seconds sram/al2 sec 00-59 19h- 1fh user sram (7 bytes) sram 0 = must be set to zero ofie = oscillator fail interrupt enable abe = alarm in battery backup enable bit otp = otp control bit a1ie = alarm1 interrupt enable bit rb0-rb2 = watchdog resolution bits ac0-ac6 = analog calibration bits rpt11-rpt15 = alarm 1 repeat mode bits acs = analog calibration sign bit rpt21-rpt25 = alarm 2 repeat mode bits af1, af2 = alarm flag rs0-rs3 = sqw frequency al2e = alarm 2 enable bit sqwe = square wave enable bl = battery low bit sram/alm2 = sram/alarm 2 bit bmb0-bmb4 = watchdog multiplier bits st = stop bit cb0, cb1 = century bits td0, td1 = timer frequency bits dc0-dc4 = digital calibration bits te = timer enable bit dcs = digital calibration sign bit tf = timer flag ft = frequency test bit ti /tp = timer interrupt or pulse ht = halt update bit tie = timer interrupt enable of = oscillator fail bit wdf = watchdog flag out= output level
m41t93 clock operation 19/51 3.3 real-time clock accuracy the m41t93 is driven by a quartz contro lled oscillator with a nom inal frequency of 32,768 hz. the accuracy of the real-time clock is dependent upon the accuracy of the crystal, and the match between the capacitive load of the oscilla tor circuit and the capacitive load for which the crystal was trimmed. temperature also affects the crystal frequency, causing additional error (see figure 10 on page 23 ). the m41t93 provides the option of clock correction through either manufacturing calibration or in-application calibration. the total possible compensation is typically ?93 ppm to +156 ppm. the two compensation circuits that are available are: 1. an analog calibration register (12h) can be used to adjust internal (on-chip) load capacitors for oscillator capacitance tri mming. the individual load capacitors c xi and c xo (see figure 9 ), are selectable from a range of ?18 pf to +9.75 pf in steps of 0.25pf. this translates to a calculated co mpensation of approximately 30 ppm (see analog calibration (programmable load capacitance) on page 22 ). 2. a digital calibration register (08h) can also be used to adjust the clock counter by adding or subtracting a pulse at the 512 hz divider stage. this approach provides periodic compensation of approximately ?63 ppm to +126 ppm (see digital calibration (periodic counter correction) on page 20 ). figure 9. internal load capacitance adjustment ai11804 xo xi crystal oscillator c xi c xo
clock operation m41t93 20/51 3.4 clock calibration the m41t93 oscillator is designed for use with a 12.5 pf crystal load capacitance. when the calibration circuit is properly employed, accuracy improves to better than 1 ppm at 25c. the m41t93 design provides the following two methods for clock error correction. 3.4.1 digital calibration (p eriodic counter correction) this method employs the use of periodic counter correction by adjusting the ratio of the 100 hz divider stage to the 512 hz divider st age. under normal operation, the 100hz divider stage outputs precisely 100 pulses for every 512 pulses of the 512 hz input stage to provide the input frequency to the fraction of seconds clock register. by adjusting the number of 512 hz input pulses used to generate 100 ou tput pulses, the clock can be sped up or slowed down, as shown in figure 12 on page 26 . when a non-zero value is loaded into the fi ve calibration bits (dc4 ? dc0) found in the digital calibration register (08h) and the sign bit is ?1,? (indicating positive calibration), the 100 hz stage outputs 100 pulses for every 511 input pulses instead of the normal 512. since the 100 pulses are now being output in a shorter window, this has the effect of speeding up the clock by 1/512 seconds for each second the circuit is active. similarly, when the sign bit is ?0,? indicating negative calibration, the block outputs 100 pulses for every 513 input pulses. since the 100 pulses are then being output in a longer window, this has the effect of slowing down the clock by 1/512 seconds for each second the circuit is active. the amount of calibration is controlled by using the value in the calibration register (n) to generate the adjustment in one second increments. this is done for the first n seconds once every eight minutes for positive calibration, and for n seconds once every sixteen minutes for negative calibration (see table 4 on page 21 ). for example, if the calibration register is se t to '100010,' then the adjustment will occur for two seconds in every minute. similarly, if the calibration register is set to '000011,' then the adjustment will occur for 3 seconds in every alternating minute. the digital calibration bits (dc4 ? dc0) occupy the five lower order bits in the digital calibration register (08h). these bits can be set to represent any value between 0 and 31 in binary form. the sixth bit (dcs) is a sign bit; '1 ' indicates positive calibration, '0' indicates negative calibration. calibration occurs within an 8-minute (positive) or 16-minute (negative) cycle. therefore, each calibration step has an effect on clock accuracy of +4.068 or ?2.034 ppm. assuming that the oscillator is running at exactly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month, which corresponds to a total range of +5.5 or ?2.75 minutes per month. note: 1 the modified pulses are not observable on the frequency test (ft) output, nor will the effect of the calibration be measurable real-time, due to the periodic nature of the error compensation. 2 positive digital calibration is performed on an eight minute cycle, therefore the value in the calibration register should not be modified more frequently than once every eight minutes for positive values of calibration. negative digita l calibration is performed on a sixteen minute cycle, therefore negative values in the calibration register should not be modified more frequently than once every sixteen minutes.
m41t93 clock operation 21/51 table 4. digital calibration values calibration value (binary) calibratio n value rounded to the nearest ppm dc4 ? dc0 negative calibration (dcs = 0) positive calibration (dcs = 1) 0 (00000) 0 0 1 (00001) ?2 4 2 (00010) ?4 8 3 (00011) ?6 12 4 (00100) ?8 16 5 (00101) ?10 20 6 (00110) ?12 24 7 (00111) ?14 28 8 (01000) ?16 33 9 (01001) ?18 37 10 (01010) ?20 41 11 (01011) ?22 45 12 (01100) ?24 49 13 (01101) ?26 53 14 (01110) ?28 57 15 (01111) ?31 61 16 (10000) ?33 65 17 (10001) ?35 69 18 (10010) ?37 73 19 (10011) ?39 77 20 (10100) ?41 81 21 (10101) ?43 85 22 (10110) ?45 90 23 (10111) ?47 94 24 (11000) ?49 98 25 (11001) ?51 102 26 (11010) ?53 106 27 (11011) ?55 110 28 (11100) ?57 114 29 (11101) ?59 118 30 (11110) ?61 122 31 (11111) ?63 126 n n/491520 (per minute) n/245760 (per minute)
clock operation m41t93 22/51 3.4.2 analog calibration (p rogrammable lo ad capacitance) a second method of calibration employs the use of programmable internal load capacitors to adjust (or trim) the oscillator frequency. by design, the oscillator is intended to be 0 ppm crystal accuracy at room temperature (25c, see figure 10 on page 23 ). for a 12.5 pf crystal, the default loading on each side of the crystal will be 25 pf. for in crementing or decrementing the calibration value, capacitance will be added or removed in increments of 0.25 pf to each side of the crystal. internally, c load of the oscillator is changed via tw o digitally controlled capacitors, c xi and c xo , connected from the xi and xo pins to ground (see figure 9 on page 19 ). the effective on-chip series load capacitance, c load , ranges from 3.5 pf to 17.4 pf, with a nominal value of 12.5 pf (ac0-ac6 = ?0?). the effective series load capacitance (c load ) is the combination of c xi and c xo : seven analog calibration bits, ac0 to ac6, are provided in order to adjust the on-chip load capacitance value for frequency compensation of the rtc. each bit has a different weight for capacitance adjustment. an analog calibrati on sign (acs) bit determines if capacitance is added (acs bit = ?0,? negative calibration) or removed (acs bit = ?1,? positive calibration). the majority of the calibration adjustment is positive (i.e. to increase the oscillator frequency by removing capacitance) due to the typical characteristic of quartz crystals to slow down due to changes in temperature, but negative calibration is also available. since the analog calibration regi ster adjustment is essentially ?pulling? the fr equency of the oscillator, the resulting fre quency changes will not be linear with incremental capacitance changes. the equations which govern this mechanism indicate that smaller capacitor values of analog calibration adjustm ent will provide larger increments . thus, the larger values of analog calibration adjustment will produce smaller incremental frequency changes. these values typically vary from 6-10 ppm/bit at the low end to <1 ppm/bit at the highest capacitance settings. the range provided by the analog calibration register adjustment with a typical surface mount crystal is approximately 30 ppm around the ac6-ac0 = 0 default setting because of this property (see table 5 on page 23 ). c load 11c xi ? 1c xo ? + () ? =
m41t93 clock operation 23/51 figure 10. crystal accuracy across temperature table 5. analog calibration values addr analog calibration value d7 d6 d5 d4 d3 d2 d1 d0 c xi , c xo c load (1) 1. c load = 1/(1/c xi + 1/c xo ) acs () ac6 (16 pf) ac5 (8 pf) ac4 (4 pf) ac3 (2 pf) ac2 ( 1pf) ac1 (0.5 pf) ac0 (0.25 pf) 12h 0 pfx0 0000 0 0 25 pf12.5 pf 3 pf00 0011 0 0 28 pf14 pf 5 pf00 0101 0 0 30 pf15 pf ?7 pf10 0111 0 0 18 pf9 pf 9.75 pf (2) 2. maximum negative calibration value 00 1001 1 134.75 pf17.4 pf ?18 pf (3) 3. maximum positive calibration value 11 0010 0 0 7 pf3.5 pf ai07888 ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 = ?0.036 ppm/ c 2 0.006 ppm/ c 2 k f = k x (t ? t o ) 2 f t o = 25 c 5 c
clock operation m41t93 24/51 the on-chip capacitance can be calculated as follows: for example: c load (12h = x0000000) = 12.5 pf c load (12h =11001000) = 3.5 pf and c load (12h = 00100111) = 17.4 pf the oscillator sees a minimum of 3.5 pf with no programmable load capacitance selected. note: these are typical values, and the total lo ad capacitance seen by the crystal will include approximately 1-2 pf of package and board capacitance in addition to the analog calibration register value. any invalid value of analog calibration will re sult in the default ca pacitance of 25 pf. the combination of analog and digital trimming can give up to ?93 to +156 ppm of the total adjustment. figure 11 on page 25 represents a typical curve of clock ppm adjustment versus the analog calibration value. this curve may vary with diff erent crystals, so it is good practice to evaluate the crystal to be used with an m4 1t93 device before establishing the adjustment values for the application in question. c load ac6 ac0 value ? decimal , () 0.25pf [] 7pf + =
m41t93 clock operation 25/51 figure 11. clock accuracy vs. on-chip load capacitors ai13906 decreasing load cap. -20.0 0.0 20.0 40.0 60.0 80.0 100.0 -5.0 -18.0 -15.0 -10.0 0.0 5.0 9.75 analog calibration value, ac, register 0x12 ppm adjustment offset to c xi , c xo (pf) net equiv. load cap., c load , (pf) 10 3.5 5.0 7.5 12.5 15 17.4 0xc8 0xbc 0xa8 0x94 0x00 0x14 0x27 increasing load cap. slower faster xo xi crystal oscillator c xo c xi c load = c xi + c xo c xi * c xo on-chip
clock operation m41t93 26/51 two methods are available for ascertaining how much calibration a given m41t93 may require: the first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. this allows the designer to give the end us er the ability to calibrate th e clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that a ccesses either or both of the calibration bytes. the second approach is better suited to a manufacturing environment, and involves the use of the irq /ft/out pin. the irq /ft/ out pin will toggle at 512 hz when ft and out bits = '1' and st = '0.' any deviation from 512 hz indicates the degree and direction of oscillator frequen cy shift at the test temperatur e. for example, a reading of 512.010124 hz would indicate a +20 ppm oscillator frequency error, requiring either a ?10 (xx001010) to be loaded into the digital calibration byte, or +6 pf (00011000) into the analog calibration byte for correction. note: setting or changing the digital calibration byte does not affect the frequency test, square wave, or watchdog timer frequency, but changing the analog calibration byte does affect all functions derived from the low current oscillator (see figure 12 ). figure 12. clock divider ch ain and calibration circuits ai11806a analog calibration circuitry remainder of divider circuit 1hz signal 512hz output frequency test 32khz low current oscillator c xi c xo 2 8 2 2 2 2 digital calibration circuitry (divide by 511/512/513) clock registers square wave watchdog timer 8-bit timer
m41t93 clock operation 27/51 figure 13. crystal isolation example note: the substrate pad should be tied to v ss . 3.5 setting the alarm clock registers address locations 0ah-0eh (alarm 1) and 14h-18h (alarm 2) contain the alarm settings. either alarm can be configured independently to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. bits rpt15?rpt11 and rpt25-rpt21 put the alarms in the repeat mode of operation. table6 on page28 shows the possible bit configurations. codes not listed in the table default to the once-per-second mode to quickly alert the user of an incorrect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt15?rpt11 and/or rpt25-rpt21, af1 (alarm 1 flag) or af2 (alarm 2 flag) is set. if a1ie (alarm 1 interrupt enable) is set, the alarm condition activates the irq /ft/out output pin. to disable either of the alarms, write a '0' to the alarm date registers and to the rptx5?rptx1 bits. note: if the address pointer is allowed to increment to the flag register address, or the last address written is ?alarm seconds,? the address pointer will increment to the fl ag address, and an alarm condition will not cause the interrupt/flag to occur until the addre ss pointer is moved to a different address. the irq output is cleared by a read to the flags register (0fh) as shown in figure 14 . a subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.'. the irq /ft/out pin can also be activated in the battery backup mode (see figure 15 on page 28 ). ai11814 crystal xi xo v ss local grounding plane (layer 2)
clock operation m41t93 28/51 3.6 optional second programmable alarm when the alarm 2 enable (al2e) bit (d1 of address 13h) is set to a logic ?1,? registers 14h through 18h provide control for a second programmable alarm which operates in the same manner as the alarm function described above. the al2e bit defaults on initial power-up to a logic ?0? (alarm 2 disabled). in this mode, the five address bytes (14h-18h) function as additional user sram, for a total of 12 bytes of user sram. figure 14. alarm interrupt reset waveform figure 15. backup mode alarm waveform note: abe and a1ie bits = 1. alarm flag bits (af x ) 0fh 0eh 00h high-z ai11823 irq/ft/out v cc irq/ft/out af x bits in flags register high-z v so v pfd trec ai11824 table 6. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 11111 once per second 11110 once per minute 11100 once per hour 11000 once per day 10000 once per month 00000 once per year
m41t93 clock operation 29/51 3.7 watchdog timer the watchdog timer can be used to detect an out-of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. bits bmb4-bmb0 store a binary multiplier and the two lower order bits rb1-rb0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. the amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (for example: writing 00001110 in the watchdog register = 3*1, or 3 seconds). if the processor does not reset the timer within the specified period, the m41t93 sets the wdf (watchdog flag) and generates a watchdog interrupt. the watchdog timer can be reset by having the microprocessor perform a write of the watchdog register. the time-out period then starts over. should the watchdog timer time-out, a value of 00h needs to be written to the watchdog register in order to clear the irq /ft/out pin. this will also di sable the watchdog function until it is again programmed correctly. a read of the flags register will reset the watchdog flag (bit d7; register 0fh). the watchdog function is automatically disabled upon power-up and the watchdog register is cleared. if the watchdog function is set, the frequency test function is activated, and the sqwe bit is '0,' the watchdog function preva ils and the frequency test function is denied. 3.8 8-bit (countdown) timer the timer value register is an 8-bit binary countdown timer. it is enabled and disabled via the timer control register (11h) te bit. other timer properties such as the source clock, or interrupt generation are also selected in the timer control register (see ta bl e 7 ). for accurate read back of the countdown value, the serial clock (scl) must be operating at a frequency of at least twice the selected timer clock. the timer control register selects one of four source clock frequencies for the timer (4096, 64, 1, or 1/60 hz), and enables/disables the timer. the timer counts down from a software- loaded 8-bit binary value. at the end of every countdown, the timer sets the timer flag (tf) bit. the tf bit can only be cleared by software. when asserted, the timer flag (tf) can also be used to generate an interrupt (irq /ft/out) on the m41t93. the interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of tf. the timer interrupt/timer pulse (ti /tp) bit is used to control this mode selection. when reading the timer, the current countdown value is returned. note: bit positions labeled with ?0? should always be written with logic '0.' table 7. timer control register map addr d7 d6 d5 d4 d3 d2 d1 d0 function 0fh wdf af1 af2 bl tf of 0 0 flags 10h timer countdown value timer value 11h te ti /tp tie 0 0 0 td1 td0 timer control
clock operation m41t93 30/51 3.8.1 ti /tp ti /tp = 0 irq /ft/out is active when tf is logic '1' (subject to the status of the timer interrupt enable bit (tie). ti /tp = 1 irq /ft/out pulses active according to ta bl e 8 (subject to the status of the tie bit). note: if an alarm condition, watchdog time-ou t, oscillator failure, or out = 0 cause irq /ft/out to be asserted low, then irq /ft/out will remain asserted even if ti /tp is set to '1.' when in pulse mode (ti /tp = 1), clearing the tf bit w ill not stop the pulses on irq /ft/out. the output pulses will only stop if te, tie, or ti /tp are reset to '0.' 3.8.2 tf at the end of a timer countdown, tf is set to logic '1.' if both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading the flag bits. the timer will auto-reload and continue to count down rega rdless of the state of tf bit (or ti /tp bit). the tf bit is cleared by reading the flags register. 3.8.3 tie in level mode (ti /tp = 0), when tf is asserted, the interrupt is asserted (if tie = 1). to clear the interrupt, the tf bit or the tie bit must be reset. 3.8.4 te te = 0 when the timer register (10h) is set to ?0,? the timer is disabled. te = 1 the timer is enabled. te is reset (disabled) on power-down. when re-enabled, the counter will begin from the same va lue as when it was disabled. table 8. interrupt operation (bit ti /tp = 1) source clock (hz) irq (1) period(s) 1. tf and irq /ft/out become active simultaneously. n (2) = 1 2. n = loaded countdown timer value. the timer is stopped when n = 0. n > 1 4096 1/8192 1/4096 64 1/128 1/64 1 1/64 1/64 1/60 1/64 1/64
m41t93 clock operation 31/51 3.8.5 td1/0 these are the timer source clock frequency selection bits (see ta bl e 9 ). these bits determine the source clock fo r the countdown timer (see ta bl e 1 0 ). when not in use, the td1 and td0 bits should be set to ?11? (1/60 hz) for power saving. note: writing to the timer re gister will not reset the tf bit or clear the interrupt. table 9. timer source clock frequency selection (244.1 s to 4.25 hrs) td1 td0 timer source clock frequency (hz) 0 0 4096 (244.1 s) 0 1 64 (15.6 ms) 10 1 (1 s) 1 1 1/60 (60 s) table 10. timer countdown value register bits (addr 11h) bit symbol description 7 - 0 this register holds the loaded countdown value ?n.? countdown period = n / source clock frequency
clock operation m41t93 32/51 3.9 square wave output the m41t93 offers the user a programmable square wave function which is output on the sqw pin. rs3-rs0 bits located in 13h establish the square wave output frequency. these frequencies are listed in ta bl e 1 1 . once the selection of the sqw frequency has been completed, the sqw pin can be turned on and off under software control with the square wave enable bit (sqwe) located in register 0ah. note: if the sqwe bit is set to '1', and v cc falls below the switchover (v so ) voltage, the squarewave output will be disabled. table 11. square wave output frequency square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000none? 000132.768khz 00108.192khz 00114.096khz 01002.048khz 01011.024khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
m41t93 clock operation 33/51 3.10 battery low warning the m41t93 automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. the battery low (bl) bit, bit d4 of flags register 0fh, will be asserted if the battery volt age is found to be less than approximately 2.5 v. the bl bit will remain asse rted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. if a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity. clock data should be considered suspect and verified as correct. a fresh battery should be installed. if a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. however, data is not compromised due to the fact that a nominal v cc is supplied. in order to insure data integrity during subsequent periods of battery backup mode, the battery should be replaced. the m41t93 only monitors the battery when a nominal v cc is applied to the device. thus applications which require extensive durations in the battery backup mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. 3.11 century bits these two bits will increment in a binary fashio n at the turn of the century, and handle all leap years correctly. see ta bl e 1 2 for additional explanation. 3.12 output driver pin when the ofie bit, a1ie bit, and watchdog register are not set to generate an interrupt, the irq /ft/out pin becomes an output driver that reflects the contents of d7 of register 08h. in other words, when d7 (out bit) is a '0,' then the irq /ft/out pin will be driven low. note: the irq /ft/out pin is an open drain which requires an external pull-up resistor. table 12. century bits examples cb0 cb1 leap year? example (1) 1. leap year occurs every four years (f or years evenly divisible by four), except for y ears evenly divisible by 100. the only exceptions are those years evenly divisible by 400 (the y ear 2000 was a leap year, year 2100 is not). 00yes2000 0 1 no 2100 1 0 no 2200 1 1 no 2300
clock operation m41t93 34/51 3.13 oscillator fail detection if the oscillator fail (of) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data. this bit will be set to '1' any time the oscillator stops. in the event the of bit is found to be set to '1' at any time other than the initial power-up, the stop bit (st) should be written to a '1,' then im mediately reset to '0.' this will restart the oscillator. the following conditions can cause the of bit to be set: the first time power is applied (defaults to a '1' on power-up). note: if the of bit cannot be written to '1' four seconds after the initial power-up, the stop bit (st) should be written to a '1,' then immediately reset to '0.' the voltage present on v cc or battery is insufficien t to support oscillation the st bit is set to '1.' external interference of the crystal for the m41t93, if the oscilla tor fail interrupt enable bit (o fie) is set to a '1,' the irq /ft/out pin will also be activated. the irq /ft/out output is cleared by resetting the ofie or of bit to '0' (not by reading the flag register). the of bit will remain set to '1' until written to logic '0.' the oscillator must start and have run for at least 4 seconds before attempting to reset the of bit to '0.' if the trigger event occurs during a power down condit ion, this bit will be set correctly. 3.14 oscillator fail interrupt enable if the oscillator fail interrupt bit (ofie) is set to a '1,' the irq /ft/out pin will also be activated. the irq /ft/out output is cleared by resetting the ofie or of bit to '0' (not be reading the flags register).
m41t93 clock operation 35/51 3.15 initial power-on defaults upon initial application of power to the device, the register bits will initially power-on in the state indicated in ta bl e 1 3 and ta bl e 1 4 . table 13. initial power-on default values (part 1) table 14. initial power-up default values (part 2) 3.16 otp bit operation (sox18 package only) when the otp (one time programmable) bit is set to a '1,' the value in the internal otp registers will be transferred to the analog calibra tion register (12h) an d are ?read only.? the otp value is programmed by the manufactur er, and will contain the calibration value necessary to achieve 5 ppm at room temperature after two smt reflows. this clock accuracy can be guaranteed to drift no more than 3 ppm the first year, and 1 ppm for each following year due to crystal aging. if the otp bit is set to '0,' the analog calibration register will become a write/read register and function like standard sram memory cells, allowing the user to implement any desired value of analog calibration. when the user sets the otp bit, they need to wait for approximately 8 ms before the analog registers transfer the value from the otp to the analog registers due to the otp read operation. condition (1) 1. all other control bits po wer-up in an undetermined state st cb1 cb0 out ft dcs acs digital calib. analog calib. ofie watchdog (2) 2. bmb0-bmb4, rb0, rb1 a1ie sqwe abe initial power-up 000 100 0 0 0 0 0 1 0 subsequent power-up (3)(4) 3. with battery backup 4. uc = unchanged uc uc uc uc 0 uc uc uc uc 0 uc uc uc condition (1) 1. all other control bits po wer-up in an undetermined state rpt11-15 ht of te ti /tp tie td1 td0 rs0 rs1-3 otp rpt21-25 al2e initial power-up 011000111000 0 subsequent power-up (2)(3) 2. with battery backup 3. uc = unchanged uc 1 uc 0 uc uc uc uc uc uc uc uc uc
maximum ratings m41t93 36/51 4 maximum ratings stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 15. absolute maximum ratings symbol parameter value (1) 1. data based on characterization results, not tested in production. unit t stg storage temperature (v cc off, oscillator off) ?55 to 125 c v cc supply voltage ?0.3 to 7.0 v t sld (2) 2. reflow at peak temperature of 260c (total th ermal budget not to exceed 245c for greater than 30 seconds). lead solder temperature for 10 seconds qfn16 260 c sox18 245 c v io input or output voltages ?0.2 to vcc+0.3 v i o output current 20 ma p d power dissipation 1 w
m41t93 dc and ac parameters 37/51 5 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. note: output hi-z is defined as the point where data is no longer driven. figure 16. measurement ac i/o waveform table 16. operating and ac measurement conditions parameter m41t93 supply voltage (v cc ) 2.38 v to 5.5 v ambient operating temperature (t a ) ?40 to +85c load capacitance (c l , typical) 30 pf input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc input and output timing ref. voltages 0.3v cc to 0.7v cc table 17. capacitance symbol parameter (1)(2) 1. effective capacitance m easured with power supply at 3.6 v; sampled only, not 100% tested 2. at 25c, f = 1 mhz min max unit c in input capacitance 7 pf c out (3) 3. outputs deselected output capacitance 10 pf ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc
dc and ac parameters m41t93 38/51 table 18. dc characteristics sym parameter test condition (1) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.38 v to 5.5 v (except where noted) min typ max unit v cc operating voltage (s) ?40 to 85c 3.00 5.50 v operating voltage (r) ?40 to 85c 2.70 5.50 v operating voltage (z) ?40 to 85c 2.38 5.50 v i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current scl = 0.1v cc /0.9v cc sdo = open f scl = 2 mhz 0.5 ma f scl = 5 mhz 1.0 ma f scl = 10 mhz 2.0 ma i cc2 supply current (standby) e = v cc ; all inputs v cc ? 0.2 v; v ss + 0.2 v 5.5 v 8 10 a 3.0 v 6.5 a v il input low voltage ?0.3 0.3v cc v v ih input high voltage 0.7v cc v cc +0.3 v v ol output low voltage rst , ft/rst v cc /v bat = 3.0 v, i ol = 1.0 ma 0.4 v sqw, irq /ft/out v cc = 3.0 v, i ol = 1.0 ma 0.4 v sdo v cc = 3.0 v, i ol = 3.0 ma 0.4 v v oh output high voltage v cc = 3.0 v, i oh = ?1.0 ma (push-pull) 2.4 v pull-up supply voltage (open drain) irq /ft/out 5.5 v v bat backup supply voltage 1.8 5.5 v i bat battery supply current 25c; v cc = 0 v; osc on; v bat = 3 v; 32 khz off 365 450 na
m41t93 dc and ac parameters 39/51 figure 17. i cc2 vs. temperature table 19. crystal electrical characteristics symbol parameter (1)(2) 1. externally supplied if using the qfn16 package. stmicroelectroni cs recommends the citizen cfs-145 (1.5 x 5 mm) and the kds dt-38 (3 x 8 mm) for thru- hole, or the kds dmx-26s (3.2 x 8 mm) or micro crystal ms3v-t1r (1.5 x 5 mm) for surface-mount, tuning fork-ty pe quartz crystals. for contact information, see section 8: references on page 49 . 2. load capacitors are integrated within the m41t93. circ uit board layout considerat ions for the 32.768 khz crystal of minimum trace lengths and isolation from rf generating signal s should be taken into account. min typ max units f o resonant frequency 32.768 khz r s series resistance 65 (3) 3. guaranteed by design. k c l load capacitance 12.5 pf table 20. oscillator characteristics symbol parameter (1)(2) 1. with default analog calibration value ( = 0) 2. reference value conditions min typ max units v sta oscillator start voltage 4 s 2.0 v t sta oscillator start time v cc = v so 1s c xi, c xo (1) capacitor input, capacitor output 25 pf ic-to-ic frequency variation (2)(3) 3. t a = 25c, v cc = 5.0 v ?10 +10 ppm ai 13909 2.000 3.000 4.000 5.000 6.000 7.000 8.000 9.000 10.000 -40 -20 0 20 40 60 80 temperature (?c) icc2 ( a) (3.0v) (5.0v)
dc and ac parameters m41t93 40/51 figure 18. power down/up mode ac waveforms table 21. power down/up trip points dc characteristics sym parameter (1)(2) 1. all voltages referenced to v ss 2. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.38 to 5.5 v (except where noted) min typ max unit v rst reset threshold voltage s 2.85 2.93 3.0 v r 2.55 2.63 2.7 v z 2.25 2.32 2.38 v v so battery backup switchover v rst v hysteresis 25 mv t rec reset pulse width (v cc rising) 140 280 ms v cc to reset delay, v cc = (v rst + 100 mv), falling to (v rst ? 100 mv; for v cc slew rate of 10 mv/s 2.5 s ai11839 v cc trec tpd v so scl sdi don't care
m41t93 dc and ac parameters 41/51 figure 19. input timing requirements figure 20. output timing requirements ai12295 scl sdi e msb in sdo tdvch high impedance lsb in telch tchel tchdx tdldh tdhdl tchcl tclch tehch tehel tcheh ai04634 scl sdo e lsb out sdi addr. lsb in tehqz tch tcl tqlqh tqhql tclqx tclqv msb out
dc and ac parameters m41t93 42/51 table 22. ac characteristics sym parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.38 to 5.5 v (except where noted) v cc < 2.7 v v cc 2.7 v units min max min max f scl scl clock frequency d.c. 5 d.c. 10 mhz t elch e active setup time 90 30 ns t ehch e not active setup time 90 30 ns t ehel e deselect time 100 40 ns t cheh e active hold time 90 30 ns t chel e not active hold time 90 30 ns t ch (2) 2. t ch and t cl must never be lower than the shortest possible clock period, 1/f c(max) clock high time 90 40 ns t cl (2) clock low time 90 40 ns t clch (3) 3. value guaranteed by characterizati on, not 100% tested in production clock rise time 1 2 s t chcl (3) clock fall time 1 2 s t dvch data in setup time 20 10 ns t chdx data in hold time 30 10 ns t ehqz (3) output disable time 100 40 ns t clqv clock low to output valid 60 40 ns t clqx output hold time 0 0 ns t qlqh (3) output rise time 50 40 ns t qhql (3) output fall time 50 40 ns
m41t93 package mechanical data 43/51 6 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at www.st.com .
package mechanical data m41t93 44/51 figure 21. qfn16 ? 16-lead, quad, flat package, no lead, 4 x 4 mm body size, outline 1. drawing is not to scale 2. substrate pad should be tied to v ss a3 a a1 e k k b ch (2) d2 e2 l e d 1 2 ddd 3 qfn16-a2 c
m41t93 package mechanical data 45/51 table 23. qfn16 ? 16-lead, quad, flat package, no lead, 4 x 4 mm body, mech. data sym mm inches typ min max typ min max a 0.90 0.80 1.00 0.035 0.032 0.039 a1 0.02 0.00 0.05 0.001 0.000 0.002 a3 0.20 ? ? 0.008 ? ? b 0.30 0.25 0.35 0.010 0.007 0.012 d 4.00 3.90 4.10 0.118 0.114 0.122 d2 ? 2.50 2.80 0.067 0.061 0.071 e 4.00 3.90 4.10 0.118 0.114 0.122 e2 ? 2.50 2.80 0.067 0.061 0.071 e0.65? ?0.020? ? k0.20? ?0.008? ? l 0.40 0.30 0.50 0.016 0.012 0.020 ddd ? 0.08 ? ? 0.003 ? ch ? 0.33 ? ? 0.013 ? n16 16
package mechanical data m41t93 46/51 figure 22. qfn16 ? 16-lead, quad, flat, no lead, 4 x 4 mm, recommended footprint 1. dimensions shown ar e in millimeters (mm) 2. substrate pad should be tied to v ss figure 23. 32 khz crystal + qfn16 vs. vsoj20 mechanical data note: dimensions shown are in millimeters (mm). 0.35 2.70 4.50 2.70 ai11815 0.65 0.70 0.325 0.20 (2) 1 16 15 14 13 xi 2 xo 3 4 ai11816 st qfn16 smt crystal vsoj2 0 3.9 3.9 1.5 3.2 6.0 0.2 7.0 0.3
m41t93 package mechanical data 47/51 figure 24. sox18 ? 18-lead plastic small outline, 300 mils, embedded crystal note: drawing is not to scale. e 9 e d c h 10 18 1 b so-j a1 l a1 h x 45 a a2 ddd table 24. sox18 ? 18-lead plastic so, 300 mils, embedded crystal, pkg. mech. data sym mm inches typ min max typ min max a ? 2.44 2.69 ? 0.096 0.106 a1 ? 0.15 0.31 ? 0.006 0.012 a2 ? 2.29 2.39 ? 0.090 0.094 b ? 0.41 0.51 ? 0.016 0.020 c ? 0.20 0.31 ? 0.008 0.012 d 11.61 11.56 11.66 0.457 0.455 0.459 ddd ? ? 0.10 ? ? 0.004 e ? 7.57 7.67 ? 0.298 0.302 e1.27? ?0.050? ? h ? 10.16 10.52 ? 0.400 0.414 l ? 0.51 0.81 ? 0.020 0.032 ? 0 8 ? 0 8 n18 18
part numbering m41t93 48/51 7 part numbering table 25. ordering information 1. the sox18 package includes an embedded 32,768 hz crystal. contact local st sales office for availability. for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: m41t 93 s qa 6 e device family m41t device type 93 operating voltage s = v cc = 3.00 to 5.5 v r = v cc = 2.70 to 5.5 v z = v cc = 2.38 to 5.5 v package qa = qfn16 (4 mm x 4 mm) my (1) = sox18 temperature range 6 = ?40c to +85c shipping method e = ecopack ? package, tubes f = ecopack ? package, tape & reel
m41t93 references 49/51 8 references below is a listing of the crystal componen t suppliers mentioned in this document. kds can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp . citizen can be contacted at csd@citizen-america.com or http://www.citizencrystal.com . micro crystal can be contacted at sales@microcrystal.ch or http://www.microcrystal.com .
revision history m41t93 50/51 9 revision history table 26. document revision history date revision changes 07-aug-2006 1 initial release. 08-may-2007 2 document status upgraded to full datasheet; updated figure 11: clock accuracy vs. on-chip load capacitors ; section 3.16 ; section 3.4.1 ; ta b l e 1 , 15 , and 18 , figure 3 and 23 ; added figure 17: i cc2 vs. temperature . micro crystal information added ( ta b l e 1 9 ). 22-oct-2007 3 updated features on cover page; minor formatting changes; modified footnote 1 in ta b l e 1 9 ; added section 8: references . 15-aug-2008 4 removed references to spi bus mode 3 operation (updated cover page, figure 5 , 6 , section 1.1.3 , section 2.1 ); minor formatting changes.
m41t93 51/51 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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