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this is information on a product in full production. january 2013 doc id 024147 rev 1 1/33 33 PM8903A 3 a step-down monolithic switching regulator datasheet ? production data features integrated 35 m mosfets for high efficiency 3 a continuous output current 2.8 v to 6 v input voltage (v in ) 2.9 v to 5.5 v supply voltage (v cc ) adjustable output voltage down to 0.6 v 1% output voltage accuracy 1.1 mhz switching frequency operation pskip mode to optimize light load efficiency embedded bootstrap diode thermally compensated loss-less current sense across hs and ls mosfets ov/uv/oc and overtemperature protection internal soft-start and soft-stop interleaving synchronization (up to 2 ics) power good output shutdown function (< 15 a quiescent current) vfqfpn16 3 x 3 mm compact package applications subsystem power supply cpu, dsp and fpga power supplies distributed power supply general dc-dc converters description the PM8903A is a high efficiency monolithic step- down switching regulator designed to deliver up to 3 a continuous current. the ic operates from 2.8 v to 6 v input voltage (v in ). the PM8903A features low-resistance integrated nmos and proprietary pulse-skipping mode for optimum efficiency over all the loading range. the voltage mode control loop allows the widest range of output filters. current sense is internally thermally compensated for optimum precision. the integrated 0.6 v reference allows the regulation of output voltages with 1% accuracy over temperature variations. switching frequency is typically set to 1.1 mhz and can be programmed to 0.8 mhz or 1.0 mhz. out of phase synchronization allows the reduction of input rms current. the PM8903A provides precise dual-threshold overcurrent protection as well as over/undervoltage and overtemperature protection. pgood output easily provides real- time information on the output voltage. the PM8903A is available in vfqfpn16 3 x 3 mm. vfqfpn16 (3 x 3 mm) table 1. device summary order codes package packaging PM8903A vfqfpn16 (3 x 3 mm) tube PM8903Atr vfqfpn16 (3 x 3 mm) tape and reel www.st.com
contents PM8903A 2/33 doc id 024147 rev 1 contents 1 typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 3 1.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.4 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 startup and shutdown management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2.1 low-side-less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2.2 soft-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 output voltage monitoring and protection . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3.1 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3.2 undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.3 feedback disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.4 power good (pgood) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5 overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.7 pulse-skipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.8 multifunction pin pskip/ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PM8903A contents doc id 024147 rev 1 3/33 6.2 output voltage setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3 inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 PM8903A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 detailed demonstration board description . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1.1 power input (v in ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.2 signal input (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.3 output (v out ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.4 test points and jumper connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
typical application circuit and block diagram PM8903A 4/33 doc id 024147 rev 1 1 typical application circuit and block diagram 1.1 application circuit figure 1. typical application circuit 1.2 block diagram figure 2. block diagram
PM8903A pin description and connection diagrams doc id 024147 rev 1 5/33 2 pin description and connection diagrams figure 3. pin connection (top view) 2.1 pin description 1 2 3 4 567 8 16 15 14 1 3 12 11 10 9 en s ynch pgood boot pha s e pha s e pha s e p s kip / m s pgnd pgnd vin vin vcc gnd fb comp table 2. pin description pin # name function 1en enable. internally pulled up by 5 a to v cc . force low to disable the device, set free or pull up above turn-on threshold to enable the converter operations. 2 synch synchronization pin. according to pskip status, the ic sends the synchronization signal out of this pin when master, while accepting a synchronization signal when slave. connect to the same synch pin of a similar part when synchronizing ics. in case of single ic operation, leave floating. 3 pgood open drain output set free after ss has finished and pulled low when v out is out of the pgood window or any protection is triggered. pull up to a voltage lower than v cc , if not used it can be left floating. 4boot bootstrap pin. it provides power supply for the floating high-side driver. connect with 0.1 f to phase. see figure 1 . 5 to 7 phase output inductor connection. the pins are connected to the embedded mosfets (high-side source and low-side drain). connect directly to output inductor. see figure 1 . 8 pskip / ms pulse-skip and master/slave definition. connect with a resistor to gnd or leave it floating to define: pulse-skip feature status; master/slave for synchronization; switching frequency. see section 5.8 on page 17 .
pin description and connection diagrams PM8903A 6/33 doc id 024147 rev 1 9comp error amplifier output. connect with an (r f - c f ) // c p to fb. see figure 1 the device cannot be disabled by pulling low this pin. 10 fb error amplifier inverting input. connect with r fb or r fb // (r s - c s ) to vsen and with an (r f - c f ) // c p to comp. a resistor r os to gnd sets the output voltage ratio. see figure 1 11 gnd all the internal references are referred to this pin. connect to the pcb signal ground. 12 vcc device power supply. operative voltage is 2.9 v - 5.5 v. filter with at least 1 f mlcc vs. gnd. 13, 14 vin power input voltage, connected to embedded high-side drain. supply range is from 2.8 v to 6 v. bypass vin pins to pgnd pins close to the ic package with high quality mlcc capacitors (at least 10 f). see figure 1 . 15, 16 pgnd power ground connection, connected to embedded low-side mosfet source. connect to pgnd pcb plane. see figure 1 . thermal pad thermal pad connects the silicon substrate and makes good thermal contact with the pcb. connect to the pcb pgnd plane. table 2. pin description (continued) pin # name function
PM8903A thermal data doc id 024147 rev 1 7/33 3 thermal data table 3. thermal data symbol parameter value unit r thja thermal resistance junction-to-ambient (device soldered on standard demonstration board, see section 7 for details) 30 c/w r thjc thermal resistance junction-to-case 12 c/w t max maximum junction temperature 150 c t stg storage temperature range -40 to 150 c t j junction temperature range -25 to 125 c
electrical specifications PM8903A 8/33 doc id 024147 rev 1 4 electrical specifications 4.1 absolute maximum ratings table 4. absolute maximum ratings 4.2 recommended operating conditions symbol parameter value unit v cc to pgnd, gnd -0.3 to 6 v v in to pgnd, gnd -0.3 to 7 v v boot to pgnd, gnd to phase -0.3 to 13 -0.3 to 6 v v phase to pgnd, gnd to pgnd, gnd, vin=6 v, t<100 nsec. -0.3 to 7 -1.7 to 7.5 v v pgood to pgnd, gnd -0.3 to 7 v v synch , v en to pgnd, gnd -0.3 to 6 v all other pins to gnd -0.3 to 3.6 v table 5. recommended operating conditions symbol parameter min. typ. max. unit v in power supply voltage 2.8 - 6 v v cc signal supply voltage 2.9 - 5.5 v
PM8903A electrical specifications doc id 024147 rev 1 9/33 4.3 electrical characteristics v in = v cc = 3.3 v 5%, t j = 0 c to 125 c, typical values at t j = 25 c, unless otherwise specified. table 6. electrical characteristics symbol parameter test conditions min. typ. max. unit supply current and undervoltage lockout i in vin supply current switching, no inductor connected 5 ma i cc vcc supply current switching, no inductor connected 1 ma i shutdown vcc + vin supply current shutdown, en = 0 v 13 a vin uvlo vin turn-on vin rising 2.8 v hysteresis 100 mv deglitching (1) rising and falling edge 1 s vcc uvlo vcc turn-on vcc rising 2.9 v hysteresis 100 mv deglitching (1) rising and falling edge 1 s oscillator f sw main oscillator accuracy r pm =0 / 24 k / 180 k / 240 k or pskip/ms pin floating 0.99 1.1 1.21 mhz v osc pwm ramp amplitude (1) 1v d duty cycle (1) 0100% t on-min minimum on-time (1) 80 ns t off-min minimum off-time (1) 80 ns reference and error amplifier output voltage accuracy vout = 0.6 v -1 - 1 % a 0 dc gain (1) 120 db gbwp gain-bandwidth product (1) 14 mhz sr slew-rate (1) c comp = 20 pf 5 v/ s output power mosfets hs r ds-on hs drain-source on- resistance 35 m ls r ds-on ls drain-source on- resistance 35 m overcurrent protection i oc1 1st level overcurrent threshold hs sourcing 4.0 4.6 5.2 a i oc2 2nd level overcurrent threshold (1) hs sourcing 4.5 5.2 5.9 a
electrical specifications PM8903A 10/33 doc id 024147 rev 1 over and undervoltage protection ovp ovp threshold fb rising 0.69 0.72 0.75 v ls turns off, fb falling 0.30 v uvp uvp threshold fb falling 0.45 0.48 0.51 v i fb fb disconnection bias current sourced from fb 100 na overtemperature protection otp thermal shutdown threshold (1) 140 c thermal shutdown hysteresis (1) 40 c pgood pgood upper threshold fb rising 0.69 0.72 0.75 v lower threshold fb falling 0.45 0.48 0.51 v v pgoodl pgood voltage low i pgood = -4 ma 0.4 v enable en input logic high en rising 1.5 v input logic low en falling 0.65 v hysteresis 150 mv deglitching (1) rising and falling edge 3 s ss t ss soft-start time r pm = 0 / 24 k / 180 k / 240 k or pskip/ms pin floating 0.79 ms 1. guaranteed by design, not subject to test. table 6. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
PM8903A electrical specifications doc id 024147 rev 1 11/33 4.4 typical operating characteristics in the demonstration board, as described in section 7.1 , r pm = 0 , v in = v cc = 3.3 v, vout=1v5, t j = 25 c, unless otherwise specified. figure 4. efficiency vs. output current - v in = 3.3 v, r pm = 240 k figure 5. efficiency vs. output current - v in = 5 v, r pm = 240 k figure 6. load regulation - v in = 3.3 v figure 7. load regulation - v in = 5 v figure 8. line regulation - i out = 3 a
device description PM8903A 12/33 doc id 024147 rev 1 5 device description the PM8903A is a high efficiency synchronous step-down monolithic switching regulator capable of delivering up to 3 a continuous output current. the power input voltage (v in ) can range from 2.8 v to 6 v, the signal input voltage (v cc ) can range from 2.9 v to 5.5 v. thanks to the 0.6 v internal reference and 0-100% duty cycle capability, the PM8903A can precisely regulate output voltages ranging from 0.6 v to almost v in (limited only by minimum t off time). the output voltage accuracy is better than 1% over line, load and temperature. the PM8903A embeds low r ds(on) (35 m ) n-channel mosfets for both hs (high-side) and ls (low-side) and implements the proprietary pulse-skipping technology, therefore, the PM8903A guarantees high efficiency over all the load range. the voltage mode control loop with high bandwidth error amplifier and external compensation enables a wide range of output filter configurations (including all mlcc solutions) and fast response to load transient. the high-switching frequency (typically 1.1 mhz) and the small vfqfpn16 3x3 mm package allow very compact vr solutions. the PM8903A features a full set of protections and output voltage monitoring: precise and accurate dual level overcurrent protection (internally compensated against temperature variations) over and undervoltage protection overtemperature protection undervoltage lockout on both signal and power supply power good open drain output easily provides real-time information about the output voltage. by simply connecting two PM8903As through the synch pin, they can synchronize each other with 180 phase shift switching interleaving, reducing rms current absorption from the input filter and preventing ?beating frequency? noise, therefore allowing the size and cost of the input filter to be reduced. a simple resistor connected from the pskip/ms pin to ground enables/disables pulse- skipping technology and assigns master or slave status to the ic. the dedicated enable pin (en) offers easy control on the power sequencing or to reset the latched protection. forcing the en low, the device enters shutdown state and absorbs a total quiescent current from v cc and v in less than 15 a. 5.1 power section the PM8903A integrates two low r ds(on) (35 m ) n-channel mosfets as low-side and high-side switches, optimized for fast switching transition and high efficiency over all the load range. the power stage is designed to deliver a continuous output current up to 3 a. the hs mosfet drain is connected to the vin pins (power input), the ls mosfet source is connected to the pgnd pins (power ground), and hs mosfet source and ls mosfet drain are connected together and to the phase pins (see figure 2 ). the driving section is supplied from the v in pins through an internal voltage regulator (v drive ) that assures the proper driving voltage over all the vin range.
PM8903A device description doc id 024147 rev 1 13/33 to properly supply the power section the following is advised: bypass v in pins to pgnd pins as close as possible to the ic package with high quality mlcc capacitors (at least 10 f). connect the bootstrap capacitor (typically a 100 nf ceramic capacitor rated to stand v in voltage) from the boot pin to the phase pin to supply the hs driver. caution: do not connect an external bootstrap diode. the ic already integrates an active bootstrap diode to charge the bootstrap capacitor, saving the cost of this external component. the PM8903A embodies an anti-shoot-through and adaptive deadtime control to minimize low-side body diode conduction time and consequently reduce power losses: when the voltage at the phase pin drops (to check high-side mosfet turn-off), the ls mosfet is suddenly switched on when the gate driving voltage of ls drops (to check low-side mosfet turn-off), the hs mosfet is suddenly switched on. if the current flowing in the inductor is negative, voltage on the phase pin never drops. a watchdog controller is implemented to allow the ls mosfet to turn on even in this case, allowing the negative current of the inductor to recirculate. this mechanism allows the system to regulate even if the current is negative (if pulse-skipping is disabled). 5.2 startup and shutdown management the PM8903A monitors the supply voltage on both vcc and vin pins. once both vcc and vin voltages are above the respective uvlo (undervoltage lockout) thresholds and the en pin is high, the device waits for 0.5 ms (typ.) and then begins the soft-start. figure 9. PM8903A soft-start sequence t ss =0.9 m s 2. 8 v vin uvlo vin t 2.7v vcc t vcc uvlo 0.6v en t en thre s hold 1.5v vref t 0.5 m s
device description PM8903A 14/33 doc id 024147 rev 1 the PM8903A implements the soft-start by gradually increasing the internal reference from 0 v to 0.6 v in a 1024 switching clock (0.79 ms typ.), linearly charging the output capacitors to the final regulation voltage in closed loop regulation. the soft-start prevents high inrush current from power supply rail. 5.2.1 low-side-less startup in order to avoid any kind of negative undershoot and dangerous return from the load during startup, the PM8903A performs a special sequence in enabling the ls driver to switch: during the soft-start phase, the ls driver results disabled (ls = off) until the first pwm pulse occurs. this avoids the dangerous negative spike on the output voltage that may happen if starting over a pre-biased output. as long as the output voltage is biased to a voltage higher than the programmed one, the control loop does not provide the hs pulse that enables ls. in this case ls is enabled at the end of the soft-start time and, if the device is allowed to sink (pskip disabled), it discharges the output to the final regulation value. this particular feature of the device masks the ls turn-on only from the control loop point of view: protection has higher priority and can turn on the ls mosfet if an overvoltage event is detected. 5.2.2 soft-off the PM8903A implements the soft-off sequence turning off both hs and ls mosfets and connecting the integrated bleeding resistor (100 ) between the phase and pgnd pin. when small load currents are applied to the converter, the soft-off sequence allows the discharging of the output voltage within a maximum time (t so ) that depends only on the output capacitance value. the PM8903A begins the soft-off sequence, and remains in a latched state, if one of the following conditions occurs: vcc voltage falls below uvlo threshold ovp (overvoltage protection) uvp (undervoltage protection) ocp (overcurrent protection) en pin is pulled low. cycle en or vcc to recover from latched state with a new soft-start sequence. 5.3 output voltage monitoring and protection the PM8903A monitors the output voltage status through the fb pin and compares the voltage on this pin with the internal reference in order to provide over and undervoltage protection as well as pgood signal. 5.3.1 overvoltage protection overvoltage protection is active as soon as the device is enabled and both v cc and v in voltages are above the respective undervoltage lockout levels. t so 5 100 c out ?? =
PM8903A device description doc id 024147 rev 1 15/33 the protection is triggered when the voltage sensed on the fb pin rises over the ovp threshold (0.72 v typ.) and the device acts as follows: hs mosfet is suddenly forced off ls mosfet is turned on (to discharge the output and protect the load) until v fb drops to 0.3 v, it is then turned off (to avoid negative spikes on the output voltage). if v fb recrosses ovp rising threshold, ls is turned on again. this protection state is latched, cycle en or vcc to recover. 5.3.2 undervoltage protection undervoltage protection is active from the end of soft-start. if v fb falls below the uvp threshold (0.48 v typ.), undervoltage protection is triggered and the device starts a soft-off sequence (see section 5.2.2 ). this protection state is latched, cycle en, vcc or vin to recover. 5.3.3 feedback disc onnection protection in order to protect the load even if the fb pin is not connected to the pcb, a 100 na current is constantly sourced from the fb pin: if the fb pin is left floating, it is internally pulled high triggering ovp protection and preventing v out from rising out of control. figure 10. fb disconnection 5.3.4 power good (pgood) pgood is an open drain output, left floating when v out is in regulation at the programmed voltage, at the end of soft-start. pgood is forced low, to communicate that the output voltage is no longer in regulation, if one of the following conditions is verified: the voltage of the fb pin exits from the pgood window ( 20% of v ref ) the device is disabled, en is forced low vcc voltage is below the uvlo threshold any protection is triggered (ovp, uvp, ocp, otp). 100na fb r o s r fb v out 720mv ovp comparator
device description PM8903A 16/33 doc id 024147 rev 1 5.4 overcurrent protection overcurrent protection is active as soon as the device is enabled and both vcc and vin voltages are above the respective uvlo levels. the overcurrent function protects the converter from a shorted output or overload by sensing the output current information across the integrated mosfets as follows: during normal operation the output current information is monitored reading the current flowing in the hs mosfet when the converter is working with an on-time lower than 130 ns (typ.) the current is monitored reading the current flowing in the ls mosfet. if the monitored current information is bigger than the overcurrent thresholds, an overcurrent event is detected. for maximum safety and load protection, the PM8903A implements a dual level overcurrent protection system. first level threshold during a switching cycle, if the monitored current information exceeds a 4.6 a (typ.) threshold, first level overcurrent is detected: the hs mosfet is turned off and the ls mosfet is turned on until the next cycle. if four first level oc events are detected in four consecutive switching cycles, overcurrent protection is triggered. second level threshold if the monitored current information exceeds the 5.2 a (typ.) threshold, overcurrent protection is triggered immediately. when overcurrent protection is triggered, the device suddenly turns off the hs and keeps the ls turned on until the output current drops to 600 ma, then the device turns off both ls and hs mosfets in a latched condition; cycle en or vcc to recover. 5.5 overtemperature protection it is recommended that the device never exceeds the maximum allowable junction temperature. this temperature increase is mainly caused by the total power dissipated from the integrated power mosfets. to avoid any damage to the device when reaching high temperature, the PM8903A implements a thermal shutdown feature: when the junction temperature reaches 140 c the device turns off both mosfets. when the junction temperature drops to 100 c, the device restarts with a new soft-start sequence. 5.6 synchronization synchronization of two PM8903As is enabled simply connecting the synch pins of the two devices together. no synchronization is implemented if the synch pin is left floating. when synchronization is enabled, the first device must be configured as a master and the second device must be configured as a slave. connect a resistor between the pskip/ms pin and ground, and select the resistor value according to ta b l e 7 , to program the ic to be master or slave.
PM8903A device description doc id 024147 rev 1 17/33 caution: do not connect together the synchronization pin of two master devices in order to avoid any damage to the ics. when two PM8903As are synchronized together they act as follows: master mode the synch pin is configured as clock output. the device provides, on the synch pin, its internal switching clock information with a 180 time shifting. slave mode the synch pin is configured as clock input. the device uses the clock information received on the synch pin to synchronize its internal switching clock. 5.7 pulse-skipping the PM8903A implements an st proprietary adaptive pulse-skipping algorithm which requires no configuration by the user and is independent from application setup and parasites. the algorithm allows to strongly increase the overall system efficiency skipping some switching cycles (so reducing the equivalent switching frequency of the converter) when the load current is low. in many applications, mlccs (multi layer ceramic capacitors) are used as the input or output filter, or both. mlccs can produce audible noise if the switching frequency is in the human hearing range. to avoid audible noise, the PM8903A pulse-skipping algorithm limits the minimum equivalent switching frequency above the audio band. pulse-skipping mode is enabled connecting a resistor between the pskip/ms pin and ground, and selects the resistor value according to ta b l e 7 . 5.8 multifunction pin pskip/ms with this pin it is possible to: enable/disable the pulse-skipping management assign to the ic master or slave status select the switching frequency. connect a resistor (r pm ) between the pskip/ms pin and gnd in order to set the ic functionality according to ta b l e 7 . table 7. pskip/ms pin configuration r pm pulse-skipping synch mode switching frequency 0 disabled slave 1.1 mhz 24 k enabled slave 1.1 mhz 56 k disabled slave 0.8 mhz 110 k disabled master 1.0 mhz 180 k enabled master 1.1 mhz 240 k (or pin floating) disabled master 1.1 mhz
application information PM8903A 18/33 doc id 024147 rev 1 6 application information 6.1 compensation network the PM8903A implements a voltage mode control loop (see figure 11 ). the output voltage is regulated to the internal reference (offset resistor between fb node and gnd can be neglected in control loop calculation). error amplifier output is compared with the oscillator sawtooth waveform to provide the pwm signal to the driver section. the pwm signal is then transferred to the switching node with v in amplitude. this waveform is filtered by the output filter. the converter transfer function is the small signal transfer function between the output of the ea and v out . this function has a double pole at frequency f lc depending on the l-c output filter and a zero at f esr depending on the output capacitor esr. the dc gain of the modulator is simply the input voltage v in divided by the peak-to-peak oscillator voltage v osc . figure 11. PM8903A control loop the compensation network closes the loop joining v out and ea output with a transfer function ideally equal to -z f /z fb . the compensation goal is to close the control loop assuring high dc regulation accuracy, good dynamic performance, and stability. to achieve this, the overall loop needs high dc gain, high bandwidth and good phase margin. high dc gain is achieved giving an integrator shape to the compensation network transfer function. loop bandwidth (f 0db ) can be fixed choosing the right r f /r fb ratio, however, for fb r f c f r fb l esr c out v out comp c p r os r s c s dcr osc hs ls driver driver v osc error amplifier modulator output filter z fb z f v ref v in phase
PM8903A application information doc id 024147 rev 1 19/33 stability, it should not exceed f sw /2 . to achieve a good phase margin, the control loop gain must cross the 0 db axis with -20 db/decade slope. for example, figure 12 shows an asymptotic bode plot of a type iii compensation. figure 12. example of type iii compensation the open loop converter singularities are: the compensation network singularity frequencies are: f lc 1 2 lc out ? --------------------------------- - = f esr 1 2 c out esr ?? ------------------------------------------- - = f z1 1 2 r f c f ?? ------------------------------ = f z2 1 2 r fb r s + () c s ?? ---------------------------------------------------- - = f p1 1 2 r f c f c p ? c f c p + --------------------- ?? ?? ?? -------------------------------------------------- = f p2 1 2 r s c s ?? ------------------------------ - =
application information PM8903A 20/33 doc id 024147 rev 1 the following suggestions may be followed in order to place the poles and zeroes of the compensation network. select a value for r fb in the range of some k select r f in order to obtain the desired closed loop regulator bandwidth according to the approximate formula: select c f in order to place f z1 below f lc (typically 0.1*f lc ): select c p in order to place f p1 at 0.5*f sw : select c s and r s in order to place f z2 at f lc and f p2 at half of the switching frequency: check that compensation network gain is lower than open loop ea gain before f 0db check phase margin obtained (it should be greater than 45 ) repeat the whole procedure if necessary. 6.2 output voltage setting the PM8903A integrates a 0.6 v internal reference (v ref ), with a total accuracy of 1% over line, load, and temperature variations (excluding external resistor divider tolerance, when present). the output voltage can be easily programmed connecting ros and rfb resistors as follows (see also figure 1 on page 4 ). connect pin fb to v out through r fb resistor connect pin fb to gnd through r os resistor. usually, the r fb resistor is selected in order to obtain the desired closed loop regulator bandwidth (see section 6.1 for details) and it is not changed when setting the output voltage. therefore, the output voltage setting is easily achieved using the following formula to select the value of the r os resistor: r f f 0db f lc ------------ v osc v in_max --------------------- - r fb ?? = c f 1 2 r f 0.1 f lc ?? ? ---------------------------------------------- = c p 1 r f f sw ?? ------------------------------ - = r s 1 c s f sw ?? ------------------------------- = c s 1 2 r fb f lc ?? ------------------------------------ - = r os r fb v ref v out v ref ? ---------------------------------- - ? =
PM8903A application information doc id 024147 rev 1 21/33 6.3 inductor design the inductance value is defined by a compromise between the dynamic response time, the efficiency, the cost, and the size. the inductor must be calculated to maintain the ripple current ( i l ) between 20% and 30% of the maximum output current (typ.). the inductance value can be calculated with the following relationship: where f sw is the switching frequency, v in is the input voltage, and v out is the output voltage. increasing the value of the inductance reduces the current ripple but, at the same time, increases the converter response time to a dynamic load change. the response time is the time required by the inductor to change its current from the initial to the final value. until the inductor finishes its charging time, the output current is supplied by the output capacitors. minimizing the response time can minimize the output capacitance required. if the compensation network is well designed, during a load variation the device is able to set a duty cycle value very different (0% or 100%) from the steady-state one. when this condition is reached, the response time is limited by the time required to change the inductor current. 6.4 output capacitors the output capacitors are basic components to define the ripple voltage across the output and for the fast transient response of the power supply. they depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. during steady-state conditions, the output voltage ripple is influenced by both the esr and the capacitive value of the output capacitors as follows: where i l is the inductor current ripple. in particular, the expression that defines v out_c takes into consideration the output capacitor charge and discharge as a consequence of the inductor current ripple. during a load variation, the output capacitor supplies the current to the load or absorbs the current stored in the inductor until the converter reacts. in fact, even if the controller immediately recognizes the load transient and sets the duty cycle at 100% or 0%, the current slope is limited by the inductor value. the output voltage has a drop that, also in this case, depends on the esr and capacitive charge/discharge as follows: where v l is the voltage applied to the inductor during the transient response ( for the load appliance or v out for the load removal). mlcc capacitors have typically low esr to minimize the ripple but also have low capacitance that does not minimize the voltage deviation during dynamic load variations. l v in v out ? f sw i l ? ----------------------------- - v out v in -------------- ? = v out_esr i l esr ? = v out_c i l 1 8c out f sw ?? -------------------------------------- - ? = v out_esr i out esr ? = v out_c i out l i out ? 2c out v l ?? ------------------------------------- - ? = d max v in v out ? ?
application information PM8903A 22/33 doc id 024147 rev 1 electrolytic capacitors have a large capacitance to minimize voltage deviation during load transients while they do not show the same esr values as the mlcc, resulting then in higher ripple voltages. a mix between an electrolytic and mlcc capacitor can be used to minimize ripple as well as reducing voltage deviation in dynamic mode. the high bandwidth error amplifier of the PM8903A and external compensation enables a wide range of output filter configurations (including all mlcc solutions) and fast transient response. 6.5 input capacitors the input capacitor bank is designed considering, mainly, the input rms current that depends on the output deliverable current (i out ) and the duty-cycle (d) for the regulation as follows: the equation reaches its maximum value, i out /2, with d = 0.5. the losses depend on the input capacitor esr and, in the worst case, are: i rms i out d1d ? () ? ? = pesri out 2 ? () 2 ? =
PM8903A PM8903A demonstration board doc id 024147 rev 1 23/33 7 PM8903A demonstration board the PM8903A demonstration board realizes, in a four-layer pcb, a high efficiency synchronous step-down monolithic switching converter capable of delivering up to 3 a continuous output current. the demonstration board shows the operation of the device in a general purpose application. two devices are present on the demonstration board and connected through the synch pin, also allowing the testing of the synchronization capability of the PM8903A. the two devices are synchronized to each other with 180 phase shift switching interleaving, reducing rms current absorption from the input filter and preventing beating frequency noise, therefore allowing a reduction in the size and cost of the input filter. figure 13. PM8903A demonstration board the input voltage (vin) can range from 2.8 v to 6 v and the supply voltage (vcc) can range from 2.9 v to 5.5 v. the output voltage is programmed to be 1.5 v but can be easily programmed, changing a single resistor, from 0.6 v to almost v in with a total accuracy better than 1% over line, load and temperature. a simple resistor connected from the pskip / ms pin to ground enables / disables pulse- skipping technology and assigns, to the ic, master or slave status. the dedicated dip switch sw1 allows the enabling / disabling of each device and offers easy control on the power sequencing or to reset latched protection. forcing en low, the device enters a shutdown state and absorbs a total quiescent current from vcc and vin less than 15 a.
PM8903A demonstration board PM8903A 24/33 doc id 024147 rev 1 7.1 detailed demonstration board description this section describes: demonstration board schematics, see figure 14 demonstration board layout, see figure 15 demonstration board bom (bill of materials), see ta b l e 8 . furthermore, the following sub-sections detail how to configure and use the standard demonstration board.
PM8903A PM8903A demonstration board doc id 024147 rev 1 25/33 figure 14. PM8903A demonstration board schematic boot pm 8 90 3 a r 12 c 1 3 c 14 comp r 11 c 12 en vin vcc gnd r 1 c 6 , c 8 , c 9 c 4 c 2 , c 3 pgnd r 2 v cc1 c 1 12 11 q 1 c 5 r 6 pha s e c 10 r 8 l 1 s ynch pgood p s kip/m s fb 9 10 r 14 r 15 r 16 r 17 r 1 3 r 10 r 7 r 3 r 4 d 1 r 5 v in1 v cc r 9 c 7 1 2 3 8 1 3 , 14 15, 16, ep 5, 6, 7 4 boot pm 8 90 3 a r 3 0 c 2 8 c 29 comp r 29 c 27 en vin vcc gnd c 22 , c 2 3 , c 24 c 20 c 1 8 , c 19 pgnd r 20 v cc2 c 17 12 11 q 2 c 5 r 6 pha s e c 26 r 26 l 2 s ynch pgood p s kip/m s fb 9 10 r 3 2 r 33 r 3 4 r 3 5 r 3 1 r 2 8 r 25 r 21 r 22 d 2 r 2 3 v in2 r 27 c 25 1 2 3 8 1 3 , 14 15, 16, ep 5, 6, 7 4 r 1 8 on on 1 2 s w 1 en1 en2 margin1 margin2 vout2 vout1 c 11 r 19 vin c 15 c 16 jp 1 jp 2 vin1 vin2 en1 en2
PM8903A demonstration board PM8903A 26/33 doc id 024147 rev 1 figure 15. PM8903A demonstration board layout top layer inner-1 layer inner-2 layer bottom layer table 8. PM8903A demonstration board - bill of material reference alias value manufacturer p.n. package supplier resistors r1, r7, r9, r19, r25, r27 nm 0603 r2, r20 10 0603 r3, r21 r pgood(1,2) 10 k 0603 r4, r22 1 k 0603 r5, r23 560 k 0603 r6, r24 r boot(1,2) 0 0603 r8, r26 r snubber(1,2) nm 0603 r10 r pm(1) 270 k 0603 r11, r29 r s(1,2) 100 0603 r12, r30 r f(1,2) 680 0603 r13, r17, r18, r31, r35 0 0603 r14, r32 r fb1(1,2) 0 0603
PM8903A PM8903A demonstration board doc id 024147 rev 1 27/33 r15, r33 r fb2(1,2) 3.3 k 0603 r16, r34 r os(1,2) 2.2 k 0603 r28 r pm(2) 0 0603 capacitors c1, c17 c vcc(1,2) 1 f, x7r 0603 c2, c3, c18, c19 c vin(1,2) 22 f, x5r, 6.3 v, 10% - mlcc grm21br60j226me 0805 murata c4, c20 c vin(1,2) 100 nf, x7r 0603 c5, c21 c boot(1,2) 100 nf, x7r 0603 c6, c8, c9, c22, c23, c24 c out(1,2) 10 f x7r 6.3 v 10% - mlcc grm21br70j106ke 0805 murata c7, c25 nm 0603 c10, c26 c snubber(1,2) nm 0603 c11 c vcc 10 f x7r 6.3 v 10% - mlcc grm21br70j106ke 0805 murata c12, c27 c s(1,2) 4.7 nf, x7r 0603 c13, c28 c f(1,2) 22 nf, x7r 0603 c14, c29 c p(1,2) 220 pf, x7r 0603 c15a, c16 c in nm case d c15 c in) nm t.h.m inductors l1, l2 1.0 h, 10.4 m spm5030t-1r0m tdk alternative inductors l1, l2 1.2 h, 35 m h.di0520-1r2 nec 1.2 h, 25 m ltf5022t-1r2n4r2-lc tdk active components d1, d2 led q1, q2 2n7002 stm u1, u2 PM8903A stm table 8. PM8903A demonstration board - bill of material (continued) reference alias value manufacturer p.n. package supplier
PM8903A demonstration board PM8903A 28/33 doc id 024147 rev 1 7.1.1 power input (v in ) connect a power supply to connectors j4(vin) and j5(gnd) on the demonstration board to provide voltage on the power input pins of both devices. input voltage can range from 2.8 v to 6 v bus. if the voltage is between 2.9 v and 5.5 v, it can also supply the signal input pins of both devices (through the v cc pin). in this case, make sure that resistors r2/r20 are nm (not mounted) and mount 0 resistors on r1/r19 locations. 7.1.2 signal input (v cc ) the controller is usually supplied separately from the power stage through the v cc input pins. connect a power supply to connector j2 (pin one is vc and pin two is gnd) on the demonstration board to provide voltage on the signal input pins of both devices. supply voltage can range from 2.9 v to 5.5 v. 7.1.3 output (v out ) on the standard demonstration board, the output voltage is programmed to be 1.5 v, but it can be easily changed mounting one of the values suggested in ta b l e 9 . select the r os (r16/r34) resistor value with the following formula in order to program a custom value for the output voltage of each device. where: v out is the desiderated output voltage v ref is the internal voltage reference (0.6 v) r fb resistor, on the demonstration board, is the sum of two resistors (r14/r15 for device u1 and r32/r33 for device u2) and has a total value of 3.3 k . table 9. typical r os resistors (r16/r34) programmed output voltage resistor value 0.6 v nm 0.8 v 10 k 1.0 v 4.9 k 1.2 v 3.3 k 1.5 v 2.2 k 1.8 v 1.65 k 2.5 v 1 k r os r fb v ref v out v ref ? ---------------------------------- - ? =
PM8903A PM8903A demonstration board doc id 024147 rev 1 29/33 7.1.4 test points and jumper connection use the following test points in order to measure the most important signals of the PM8903A. vcc1 / vcc2: monitor the supply voltages vin1 / vin2: monitor the input voltages v_out_s1 / v_out_s2: monitor the output voltages (use these test points to perform efficiency load-line regulation measurements) pgood1 / pgood2: (active high) monitor the regular functioning of the controllers synch1 / synch2: these are usually shorted when two devices are synchronized together. unplug jumpers jp1 /jp2 in order to remove the power input voltage from device u1, device u2, or both. provide power supply voltage to one device at a time when performing efficiency tests. turn on dip-switch sw1 in order to disable device u1, device u2, or both.
package mechanical data PM8903A 30/33 doc id 024147 rev 1 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. table 10. vfqfpn16 3 x 3 x 1.0 mm mechanical data dim. mm min. typ. max. a 0.80 0.90 1.00 a1 0.02 0.05 a2 0.65 1.00 a3 0.20 b 0.18 0.25 0.30 d 2.85 3.00 3.15 d1 1.50 d2 1.60 e 2.85 3.00 3.15 e1 1.50 e2 1.60 e 0.45 0.50 0.55 l 0.30 0.40 0.50 ddd 0.08
PM8903A package mechanical data doc id 024147 rev 1 31/33 figure 16. package dimensions
revision history PM8903A 32/33 doc id 024147 rev 1 9 revision history table 11. document revision history date revision changes 11-jan-2013 1 first release
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