extra low capacitance for integrated esd mechanical data e}? ? dice size a x :600um,b x :420um/p1,3,4,6 - 85*95um/pin 5 - 270*105um wafer size 4 (gross die:27,500pcs/good die>25,575pcs) chip thickness (a)138um12um (b)470um20um scribe line width 60um top metal al/au/ag back side metal al/au/ag/sn parameter ^?u}o }v]?}v? so hv]? reverse stand - of voltage v rwm 5.0 v peak pulse power p pp tp=8/20us 150** w peak pulse current i pp tp=8/20us 5.0** a electrostatc discharge v esd iec61000 - 4 - 2 level 4 15(air) kv max.juncton temp. t j + 150 parameter ^?u}o }v]?}v d]vx d??x d?x hv]? breakdown voltage v br i t =1ma pin 5 to 2 6.1 8.0 8.5 v reverse leakage current i r v r =5v pin 1,3,4,5,6 to 2 0.9 ua forward voltage v f 1 f =15ma pin2 to pin1,3,4,5,6 0.95 v clamping voltage v c i pp =1a i pp =5a 15.0 28.0 v diode capacitance i/o - gnd c i/o - gnd v r =0v f=1mh z 0.8 pf diode capacitance i/o - i/o c i/o - i/o v r =0v f=1mh z 0.4 pf characteristics ta=25 notes: ( 1)sampling testng:no bad dice inking/guaranteed good die >93% (2)testng follow customer (3)tj=ta+rth(j - a)*(pf+pr),where rth(j - a) - thermal resistance,pf - forward power dissipaton, pr - revers power dissipaton (4)**for device testng futurewafer technology co.,ltd www.futurewafer.com.tw+886 - 3 - 3573583 FER5VC4S1 ew1608a5 - fw - a
|
