View DS742_8897120.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DS742 january 18, 2012 www.xilinx.com 1 product specification ? copyright 2010?2012 xilinx, inc. xilinx, the xilinx logo, artix, ise, kintex, spartan, virtex, and other designated brands in cluded herein are trademarks of xilinx in the united states and other countries. arm is a registered trademark of arm in the eu and other countries. the amba trademar k is a registered trademark of arm limited. all other trademarks are the property of their respective owners. introduction the axi serial peripheral in terface (spi) connects to the advanced extensible interface (axi4). this core provides a serial interface to spi devices such as spi electrically erasable programmable read-only memories (eeproms) and spi serial flash devices. the spi protocol, as described in the motorola m68hc11 data sheet, provides a simple method for a master and a selected slave to exchange data. this 32-bit soft intellectual property (ip) co re is designed to interface with the axi4-lite interface. features ? axi4-lite interface is based on the axi4 specification ? connects as a 32-bit axi4-lite slave ? supports four signal interfaces: ? master out slave in (mosi) ? master in slave out (miso) ? serial clock (sc) ?ss ?slave select (ss ) bit for each slave on the spi bus ? full-duplex operation ? master and slave spi modes ? programable clock phase and polarity ? continuous transfer mode for automatic scanning of a peripheral ? back-to-back transactions ? automatic or manual slave select modes ? msb/lsb first transactions ? transfer length of 8-bits, 16-bits or 32-bits ? local loopback capa bility for testing ? multiple master and multiple slave environment ? optional 16 element deep (an element is a byte, a half-word or a word) transmit and receive first in first out (fifo) logicore ip axi serial peripheral interface (axi spi) (v1.02.a) DS742 january 18, 2012 product specification logicore ip facts core specifics supported device family (1) artix-7 (2) , virtex-7 (2) , zynq?-7000, kintex-7 (2) , virtex-6 (3) , spartan-6 (4) supported user interfaces axi4-lite configuration resources and frequency configuration 1 luts ffs freq. block rams see ta b l e 2 0 , ta b l e 1 9 , ta bl e 1 8 , ta bl e 1 6 and ta bl e 1 7 . 0 provided with core documentation product specification design files vhsic hardware description language (vhdl) example design n/a test bench n/a constraints file n/a supported s/w driver (5) standalone and linux tested design tools (6) design entry tools xilinx platform studio (xps) simulation mentor graphics modelsim synthesis tools xilinx sy nthesis technology (xst) support provided by xilinx @ www.xilinx.com/support notes: 1. for a complete listing of supported derivative devices, see the ids embedded edition derivative device support . 2. for more information, see 7 series fpgas overview ds180. 3. for more information, see the virtex-6 family overview product specification (ds150). 4. for more information, see spartan-6 family overview product specification (ds160). 5. standalone driver details can be found in the edk or sdk directory (< install_directory >/doc/usenglish/xilinx_drivers.htm). linux os and driver support information is available from http://wiki.xilinx.com. 6. for a listing of the supported tool versions, see the ise design suite 13: release note guide .
DS742 january 18, 2012 www.xilinx.com 2 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) functional description the top level block diagram for the xilinx ? axi spi ip core is shown in figure 1 . the axi spi ip core is a full-duplex synchronous channel that supports a four-wire interface (receive, transmit, clock and slave-select) between a master and a selected sl ave. the core supports manual slave select mode as the default mode of operation. this mode allows the user to ma nually control the slave select line using the data written to the slave select register. this allows transfers of an arbitrary number of el ements without toggling the slave select line between elements. however, the user must toggle the slave select line before starting a new transfer. the other mode of operation is automatic slave select mode. in this mode the slave select line is toggled automatically after each element transfer. th is mode is described in more detail in spi protocol with automatic slave select assertion . the axi spi ip core supports continuous transfer mode; when configured as a master the transfer continues until the data is available in transmit register/fifo. this ca pability is provided in both manual and automatic slave select modes. when the core is configured as a slave and if inadvertently its slave select line (spisel) goes high (inactive state) in between the data element transfer, then the current transfer is aborted. again if the slave select line goes low then the aborted data element is transmitted again. the core allows additional slaves to be added with automatic generation of the required decoding logic for individual slave select outputs by the ma ster. additional masters can also be added. however, the means to detect all possible conflicts are not im plemented with this interface standard. to eliminate conflicts, software is required to arbitrate bus control. x-ref target - figure 1 figure 1: axi spi ip core top-level block diagram axi4-lite interf ace module register module status register (spisr) control register (spicr) receive regi ster (spidrr) tr ansmit register (spidtr) interrr upt controller register set sla ve select register (spissr) tx fifo rx fifo control unit shift register brg (3) pins interf ace spi module axi spi interr upt notes: 1. the width of tx fifo, rx fifo, and shift register depends on the v alu e of the generic, c_num_transer_bits . 2. the width of ss depends on the v alu e of the generic c_num_ss_bits . 3 . brg (buad rate gener ator) spi port s sck miso mosi ss(n) spisel axi4-lite DS742_01 (1) (2) (1)
DS742 january 18, 2012 www.xilinx.com 3 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) the core can communicate with both off-chip and on-chip ma sters and slaves. the number of slaves is limited to 32 by the size of the slave select register. however, the number of slaves and masters does impact the achievable performance in terms of frequency and resource utilizatio n. all of the spi and intr registers are 32-bit wide. the core supports only 32-bit word access to all spi and intr register modules. axi4-lite ip ipif interface (ipif): the axi4-lite ip interface (ipif) provides the interface to the axi4-lite to ip interconnect (ipic). the read and writ e transactions at the axi4-lite interf ace are translated into equivalent ip interconnect (ipic) transactions. see [ref 4] for more information about the ipic. spi register module : the spi register module includes all memory mapped registers (as shown in figure 1 ). it interfaces to the axi. it consists of status register, cont rol register, n-bit slave select register (n 32) and a pair of transmit/receive registers. interrupt controller register set module : the interrupt controller register set module consists of interrupt related registers, namely: device global interrupt enable register (dgier), ip interrupt enable register (ipier), and ip interrupt status register (ipisr). spi module : the spi module consists of a shift register, a para meterized baud rate generator (brg) and a control unit. it provides the spi interface, including the control logic and initialization logic. it is the heart of core. optional fifos : the tx fifo and rx fifo are implemented on both transmit and receive paths when enabled by the parameter c_fifo_exist. the width of tx fifo and rx fifo are the same and depend on the generic c_num_transfer_bits. when the fifos are enabled, their depth is fixed at 16. design parameters to allow the user to obtain an axi spi ip core that is uniquely tailored for the system, certain features can be parameterized. parameterization affords a measure of cont rol over the function, resource usage, and performance of the implemented axi spi ip core. the features that can be parameterized are as shown in table 1 . in addition to the parameters listed in this table, there are also para meters that are inferred for each axi interface in the embedded development kit (edk) tools. through the desi gn, these edk-inferred parameters control the behavior of the axi interconnect. for a complete list of the in terconnect settings related to the axi interface, see [ref 6] . ta bl e 1 : design parameters generic feature/description para meter name allowable values default value vhdl type system parameters g1 target fpga family c_family virtex6 , spartan6, 7series, zynq virtex6 string axi parameters g2 axi base address c_b aseaddr valid address (1) none (2) std_logic_ vector g3 axi high address c_highaddr valid address (1) none (2) std_logic_ vector g4 axi address bus width c_s_axi_addr_width 32 32 integer g5 axi data bus width c_s_axi _data_width 32, 64 32 integer axi spi ip core parameters g6 include receive and transmit fifos c_fifo_exist 0 = fifos not included 1 = fifos included 1 integer
DS742 january 18, 2012 www.xilinx.com 4 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) input/output (i/o) signals the i/o signals are listed and described in table 2 . g7 spi clock frequency ratio c_sck_ratio 2 (3) , 4, 8, nx16 for n = 1, 2, 3, ... 32 integer g8 total number of slave select bits c_num_ss_bits 1 - 32 1 integer g9 select number of transfer bits as 8 c_num_transfer_bits 8, 16, 32 8 integer notes: notes: 1. the range c_baseaddr to c_highaddr is the address range for th e axi spi ip. this range is subject to restrictions to accommodate the simple address decoding scheme that is employed. the size, c_highaddr - c_baseaddr + 1, must be a power of two and must be at least 0x80 to accommodate all axi spi ip core registers. however, a larger power of two can be chosen to reduce decoding logic. c_baseaddr must be aligned to a multiple of the range size. 2. no default value is specified to ensure that an actual value appropriate to the system is set. the values must be set by the user. 3. c_sck_ratio = 2 is not supported when the axi spi ip core is configured as slave. read the precautions to be taken while assigning the c_sck_ratio parameter section carefully when using this parameter. ta bl e 2 : i/o signal descriptions port signal name interface i/o initial state description axi global system signals p1 s_axi_aclk axi i - axi clock p2 s_axi_aresetn axi i - axi reset, active low axi write address channel signals p3 s_axi_awaddr[(c_s_axi_ addr_width - 1) : 0] axi i - axi write address. the write address bus gives the address of the write transaction. p4 s_axi_awvalid axi i - write address valid. this signal indicates that a valid write address and control information are available. p5 s_axi_awready axi o 0 write address ready. this signal indicates that the slave is ready to accept an address and associated control signals. axi write channel signals p6 s_axi_wdata[(c_s_axi_ data_width - 1) : 0] axi i - write data p7 s_axi_wstb[((c_s_axi_ data_width/8) - 1) : 0] axi i - write strobes. this signal indicates which byte lanes to update in memory. p8 s_axi_wvalid axi i - write valid. this signal indicates that valid write data and strobes are available. p9 s_axi_wready axi o 0 write ready. this signal indicates that the slave can accept the write data. axi write response channel signals p10 s_axi_bresp[1 : 0] axi o 0 write response. this signal indicates the status of the write transaction 00 - okay (normal response) 10 - slverr (error response) 11 - decerr (not issued by core) ta bl e 1 : design parameters (cont?d) generic feature/description para meter name allowable values default value vhdl type
DS742 january 18, 2012 www.xilinx.com 5 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) p11 s_axi_bvalid axi o 0 write response valid. this signal indicates that a valid write response is available. p12 s_axi_bready axi i - response ready. this signal indicates that the master can accept the response information. axi read address channel signals p13 s_axi_araddr[(c_s_axi_ addr_width - 1) : 0 ] axi i - read address. the read address bus gives the address of a read transaction. p14 s_axi_arvalid axi i - read address valid. when high, this signal indicates that the read address and control information is valid and remains stable until the address acknowledgement signal, s_axi_arready, is high. p15 s_axi_arready axi o 1 read address ready. this signal indicates that the slave is ready to accept an address and associated control signals. axi read data channel signals p16 s_axi_rdata[(c_s_axi_ data_width - 1) : 0] axi o 0 read data p17 s_axi_rresp[1 : 0] axi o 0 read response. this signal indi cates the status of the read transfer. 00 - okay (normal response) 10 - slverr (error condition) 11 - decerr (not issued by core) p18 s_axi_rvalid axi o 0 read valid. this signal indicates that the required read data is available and the read transfer can complete. p19 s_axi_rready axi i - read ready. this signal indicates that the master can accept the read data and response information. spi interface signals p20 ip2intc_irpt spi o 0 interrupt control signal from spi p21 sck_i spi i - spi bus clock input p22 sck_o spi o 0 spi bus clock output p23 sck_t spi o 1 3-state enable for spi bus clock.active low p24 mosi_i spi i - master output slave input p25 mosi_o spi o 1 master output slave input p26 mosi_t spi o 1 3-state enable master output slave input. active low. p27 miso_i spi i - master input slave output p28 miso_o spi o 1 master input slave output p29 miso_t spi o 1 3-state enable master input slave output. active low. p30 spisel (1) spi i 1 local spi slave select active low input must be set to 1 in idle state p31 ss_i[(c_num_ss_bits - 1):0] spi i - input one-hot encoded. this signal is a dummy signal and is used in the design as chip-select input. p32 ss_o[(c_num_ss_bits - 1):0] spi o 1 output one-hot encoded, active low slave select vector of length n. p33 ss_t spi o 1 3-state enable for slave select. active low. 1. spisel signal is used as a slave select line when axi spi is configured as a slave. ta bl e 2 : i/o signal descriptions (cont?d) port signal name interface i/o initial state description
DS742 january 18, 2012 www.xilinx.com 6 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) parameters - i/o signal dependencies the dependencies between the axi spi ip core design parameters and i/o signals are described in ta ble 3 . register overview table table 4 gives a summary of the axi spi ip core registers. the transmit fifo occupancy register and the receive fifo occupancy register exist only when c_fifo_exist = 1. ta bl e 3 : parameters - signal dependencies generic or port name affects depends relationship description design parameters g4 c_s_axi_addr_width p3, p13 - affects the number of bits in address bus g5 c_s_axi_data_width p6, p7, p16 affects the number of bits in data bus g8 c_num_ss_bits p31, p32 - defines the total number of slave select bits i/o signals p3 s_axi_awaddr[(c_s_axi_addr_ width - 1) : 0] -g4 width of the axi bus address varies with c_s_axi_addr_width. p6 s_axi_wdata[(c_s_axi_ data_width - 1) : 0] -g5 width of the s_axi_wdata varies according to c_s_axi_data_width. p7 s_axi_wstb[((c_s_axi_ data_width/8) - 1): 0] -g5 width of the s_axi_wstb varies according to c_s_axi_data_width. p16 s_axi_rdata[(c_s_axi_data_ width - 1):0] -g5 width of the s_axi_rdata varies according to c_s_axi_data_width. p31 ss_i[(c_num_ss_bits - 1):0] - g8 the number of ss_i pins are generated based on c_num_ss_bits. p32 ss_o[(c_num_ss_bits - 1):0] - g8 the number of ss_o pins are generated based on c_num_ss_bits. ta bl e 4 : core registers base address + offset (hex) register name access type default value (hex) description core grouping c_baseaddr + 40 srr write n/a software reset register c_baseaddr + 60 spicr r/w 0x180 spi control register c_baseaddr + 64 spisr read 0x25 spi status register c_baseaddr + 68 spidtr write 0x0 spi data transmit register a single register or a fifo c_baseaddr + 6c spidrr read na spi data receive register a single register or a fifo c_baseaddr + 70 spissr r/w no slave is selected spi slave select register c_baseaddr + 74 spi transmit fifo occupancy register (1) read 0x0 transmit fifo occupancy register c_baseaddr + 78 spi receive fifo occupancy register (1) read 0x0 receive fifo occupancy register interrupt controller grouping c_baseaddr + 1c dgier r/w 0x0 device gl obal interrupt enable register
DS742 january 18, 2012 www.xilinx.com 7 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) register details software reset register (srr) the software reset register allows the programmer to reset the core independent of other cores in the systems. to activate software generated reset, the value of 0x0000_000a must be written to this register. any other write access generates an error condition with undefined results and results in error generation. the bit assignment in the software reset register is shown in figure 2 and described in table 5 . an attempt to read this register returns undefined data. spi control register (spicr) the spi control register (spicr) gives the programmer contro l over various aspects of the axi spi ip core. the bit assignment in the spicr is shown in figure 3 and described in table 6 . c_baseaddr + 20 ipisr r/tow (2) 0x0 ip interrupt status register c_baseaddr + 28 ipier r/w 0x0 ip interrupt enable register note: 1. exists only when c_fifo_exist = 1. 2. tow = toggle on write. writing a 1 to a bit position within the register causes the corresponding bit position in the registe r to toggle. x-ref target - figure 2 figure 2: software reset register (c_baseaddr + 0x40) ta bl e 5 : software reset register (srr) description (c_baseaddr + 0x40) bit(s) name core access reset value description 31 - 0 reset write only n/a the only allowed operation on this register is a write of 0x0000000a, which resets the axi spi ip core. x-ref target - figure 3 figure 3: spi control register (c_baseaddr + 0x60) ta bl e 4 : core registers (cont?d) base address + offset (hex) register name access type default value (hex) description res et 3 1 0 DS742_02 0 1 2 3 456 7 8 910 31 s pe loop cpol m aster tx fifo res et cpha m a n ual s l a ve s elect ass ertion enab le rx fifo res et m aster tr a n saction inhib it res erved l s b firs t DS742_03
DS742 january 18, 2012 www.xilinx.com 8 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) ta bl e 6 : spi control register (spicr) description (c_baseaddr + 0x60) bit(s) name core access reset value description 31 - 10 reserved n/a n/a reserved 9 lsb first r/w 0 lsb first this bit selects lsb first data transfer format. the default transfer format is msb first. 0 = msb first transfer format 1 = lsb first transfer format 8 master transaction inhibit r/w 1 master transaction inhibit this bit inhibits master transactions. this bit has no effect on slave operation. 0 = master transactions enabled 1 = master transactions disabled 7 manual slave select assertion enable r/w 1 manual slave select assertion enable this bit forces the data in the slave select register to be asserted on the slave select output anytime the device is conf igured as a master and the device is enabled (spe asserted). this bit has no effect on slave operation. 0 = slave select output asserted by master core logic 1 = slave select output follows data in slave select register 6 rx fifo reset r/w 0 receive fifo reset when written to 1, this bit forces a reset of the receive fifo to the empty condition. one axi clock cycle after reset, this bit is again set to 0. this bit is unassigned when the axi spi ip core is not configured with fifos. 0 = receive fifo normal operation 1 = reset receive fifo pointer 5 tx fifo reset r/w 0? transmit fifo reset when written to 1, this bit forces a reset of the transmit fifo to the empty condition. one axi clock cycle after reset, this bit is again set to 0. this bit is unassigned when the axi spi ip core is not configured with fifos. 0 = transmit fifo normal operation 1 = reset transmit fifo pointer 4cphar/w0 clock phase (cpha) setting this bit selects one of two fu ndamentally different transfer formats. see spi clock phase and polarity control . 3cpolr/w0 clock polarity (cpol) setting this bit defines clock polarity. 0 = active high clock; sck idles low 1 = active low clock; sck idles high 2 master r/w 0 master (spi master mode) setting this bit configures the spi device as a master or a slave. 0 = slave configuration 1 = master configuration 1 spe r/w 0 spi system enable setting this bit to 1 enables the spi devices: 0 = spi system disabled. both master an d slave outputs are in "3-state" and slave inputs ignored. 1 = spi system enabled. mast er outputs active (for ex ample, mosi and sck in idle state) and slave outputs become active if ss becomes asserted. master starts a transfer when transmit data is available. 0 loop r/w 0 local loopback mode enables local loopback operation and is functional only in master mode. 0 = normal operation 1 = loopback mode. the transmitter output is internally connected to the receiver input. the receiver and transmitter operate normally, except that received data (from remo te slave) is ignored.
DS742 january 18, 2012 www.xilinx.com 9 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) spi status register (spisr) the spi status register (spisr) is a read-only register that gives the programmer visibi lity of the status of some aspects of the axi spi ip core. the bit assignment in the spisr is shown in figure 4 and described in table 7 . writing to the spisr does not modify the register contents. x-ref target - figure 4 figure 4: spi status register (c_baseaddr + 0x64) ta bl e 7 : spi status register (spisr) description (c_baseaddr + 0x64) bit(s) name core access reset value description 31 - 6 reserved n/a n/a reserved 5 slave_ mode_ select read 1 slave_mode_select flag this flag is asserted when the core is co nfigured in slave mode. slave_mode_select is activated as soon as the master spi core asserts the chip select pin for the core. 1 = default 0 = asserted when core configured in slave mode and selected by external spi master 4 modf read 0 mode-fault error flag (mode-fault error) this flag is set if the ss signal goes active while the spi device is configured as a master. modf is automatically cleared by reading the spisr. a low-to-high modf transition generates a sing le-cycle strobe interrupt. 0 = no error 1 = error condition detected 3 tx_full read 0 transmit full when a transmit fifo exists, this bit is set high when the transmit fifo is full. note: when fifos do not exist, this bit is set high when an axi write to the transmit register has been made. this bit is cleared when the spi transfer is completed. 2 tx_empty read 1 transmit empty when a transmit fifo exists, this bit is set high when the transmit fifo is empty. the occupancy of the fifo is decremented with the completion of each spi transfer. note: when fifos do not exist, this bit is set with the completion of an spi transfer. either with or without fifos, this bit is clea red upon a axi write to the fifo or transmit register. 1 rx_full read 0 receive full when a receive fifo exists, this bit is set high when the receive fifo is full. the occupancy of the fifo is incremented with the completion of each spi transaction. note: when fifos do not exist, this bit is set high when an spi transfer has completed. rx_empty and rx_full are complements in this case. 0 rx_empty read 1 receive empty when a receive fifo exists, this bit is set high when the receive fifo is empty. the occupancy of the fifo is decremen ted with each fifo read operation. note: when fifos do not exist, this bit is set high when the receive register has been read. this bit is cleared at t he end of a successful spi transfer. 5 31 rx_fu ll rx_empty tx_fu ll tx_empty res erved modf 0 123 4 6 s l a ve_mode _ s elect DS742_04
DS742 january 18, 2012 www.xilinx.com 10 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) spi data transmit register (spidtr) this register is written to with the data to be transmitted on the spi bus. after the spe bit is set to 1 in master mode or spisel is active in the slave mode, th e data is transferred from the spidtr to the shift register. if a transfer is in progress, the data in the spidtr is loaded in the shift regist er as soon as the data in the shift register is transferred to the spidrr and a new transfer starts. the data is held in the spidtr until a subsequent write overwrites the data. the spidtr is shown in figure 5 , while table 8 shows specifics of the data format. when a transmit fifo exists, data is written directly in the fifo and the first location in the fifo is treated as the spidtr. the pointer is decremented after completion of each spi transfer. this register cannot be read and can only be written when it is known that space for the data is available. if an attempt to write is made on a full register or fifo, then the axi write transaction completes with an error condition. reading to the spidtr is not allowed and the read transaction results in undefined data. spi data receive register (spidrr) this register is used to read data that is received from the spi bus. this is a double-buffered register. the received data is placed in this register after each complete tran sfer. the spi architecture does not provide any means for a slave to throttle traffic on the bus; consequently, the sp idrr is updated following each completed transaction only if the spidrr was read prior to the last spi transfer. if the spidrr was not read, and therefore is full, the most recently transferred data is lost and a receive overrun in terrupt occurs. the same condition can occur with a master spi device as well. for both master and slave spi devices with a receive fifo, the data is buffered in the fifo. the receive fifo is a read-only buffer. if an attempt to read an empty receive register or fifo is made, then the axi read transaction completes successfully with undefined da ta. writes to the spidrr do not modi fy the register contents and return with a successful ok response. the spidrr is shown in figure 6 , while the specifics of the data format is described table 9 . x-ref target - figure 5 figure 5: spi data transmit regist er (c_baseaddr + 0x68) ta bl e 8 : spi data transmit register (spi dtr) description (c_baseaddr + 0x68) bit(s) name core access reset value description [n-1] - 0 tx data (1) (d n-1 - d 0 ) write only 0 n-bit spi transmit data. n can be 8, 16 or 32. n = 8 when c_num_transfer_bits = 8 n = 16 when c_num_transfer_bits = 16 n = 32 when c_num_transfer_bits = 32 1. the d n-1 bit always represents the msb bit irrespective of "l sb first" or "msb first" transfer selection. when c_num_transfer_bits = 8 or 16, the unused upper bits ((c_axi_data_width-1) to n) are reserved. x-ref target - figure 6 figure 6: spi data receive register (c_baseaddr + 0x6c) 0 tx da t a ((d(n-1) - d0)) n-1 0 n-1 rx da t a (d( n-1) - d 0 )
DS742 january 18, 2012 www.xilinx.com 11 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) spi slave select register (spissr) this register contains an active low, one-hot encoded slave select vector ss of length n, where n is the number of slaves set by parameter c_num_ss_bits. the ss occupies the right-most bits of the register. at most, one bit can be asserted low. this bit denotes the slave with whom the local master communicates. the bit assignment in the spissr is shown in figure 7 and described in ta ble 10 . spi transmit fifo occupancy register (tx_fifo_ocy) the spi transmit fifo occupancy register is present only if the axi spi ip core is configured with fifos (c_fifo_exist = 1). if it is present and if the transmit fifo is not empty, the register contains a four-bit, right-justified value that is one less th an the number of elements in the fifo (occupancy minus one). this register is read-only. a write to it (or a read when the fifo is em pty) does not affect the register contents. the only reliable way to determine that the tx fifo is empty is by reading the tx_empty status bit in the spi status register or the data transmit register (dtr) empty bit in the interrupt status register. the transmit fifo occupancy register is shown in figure 8 , while the specifics of the data format are described in table 11 . ta bl e 9 : spi data receive register (spi drr) description (c_baseaddr + 0x6c) bit(s) name core access reset value description [n-1] - 0 rx data (1) (d n-1 - d 0 ) read only 0 n-bit spi receive data. n can be 8, 16 or 32. n = 8 when c_num_transfer_bits = 8 n = 16 when c_num_transfer_bits = 16 n = 32 when c_num_transfer_bits = 32 1. the d n-1 bit always represents the msb bit irrespective of "l sb first" or "msb first" transfer selection. when c_num_transfer_bits = 8 or 16, the unused upper bits ((c_axi_data_width-1) to n) are reserved. x-ref target - figure 7 figure 7: spi slave select register (c_baseaddr + 0x70) ta bl e 1 0 : spi slave select register (spiss r) description (c_baseaddr + 0x70) bit(s) name core access reset value description 31 - n reserved n/a n/a reserved [n-1] - 0 selected slave r/w 1 active low, one-hot encoded slave select vector of length n-bits. n must be less than or equal to the data bus width (32-bit). the slaves are numbered right to left starting at ze ro with the lsb. the slave numbers correspond to the indexes of signal ss . x-ref target - figure 8 figure 8: spi transmit fifo occupancy register (c_baseaddr + 0x74) ta bl e 1 1 : spi transmit fifo occupancy register description (c_baseaddr + 0x74) bit(s) name core access reset value (hex) description 31 - 4 reserved n/a n/a reserved 3 - 0 occupancy value read 0 bit 3 is the msb. the binary value plus 1 yields the occupancy. 0 n-1n 31 s elected s l a ve res erved DS742_07 0 31 occu p a ncy v a l u e res erved 3 4
DS742 january 18, 2012 www.xilinx.com 12 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) spi receive fifo occupancy register (rx_fifo_ocy) the spi receive fifo occupancy register is present if and only if the axi spi ip core is configured with fifos (c_fifo_exist = 1). if it is present and if the receive fifo is not empty, the register contains a four-bit, right-justified value that is one less th an the number of elements in the fifo (occupancy minus one). this register is read-only. a write to it (or of a read when the fifo is empty) does not affect the register contents. the only reliable way to determine that the rx fifo is empty is by reading the rx_empty status bit in the spi status register. the receive fifo occupancy register is shown in figure 9 , while the specifics of the data format are described in table 12 . interrupt register set description the axi spi ip core has a number of dist inct interrupts that are sent to the interrupt controller submodule. the axi spi ip interrupt controller allows each interrupt to be enabled independently (via the ip interrupt enable register (ipier)). the interrupt registers are in the interrupt contro ller. an interrupt strobe can be generated under multiple conditions or only after a transfer completion. setting the parameter c_fifo_exist = 1 makes available almost all of the interrupts shown in table 14 when the core is configured in the master mode. setting the parameter c_fifo_exist = 0 makes available all of the interrupts exce pt bit(6), tx fifo half empty and bit(8) data receive register (drr) not empty, which is not present in this case. device global interrupt enable register (dgier) the device global interrupt enable register is used to gl obally enable the final interrupt output from the interrupt controller as shown in figure 10 and described in table 13 . this bit is a read/write bi t and is cleared upon reset. x-ref target - figure 9 figure 9: spi receive fifo occupancy register (c_baseaddr + 0x78) ta bl e 1 2 : spi receive fifo occupancy regist er description (c_baseaddr + 0x78) bit(s) name core access reset value (hex) description 31- 4 reserved n/a n/a reserved 3 - 0 occupancy value read 0 bit 3 is the msb. the binary value plus 1 yields the occupancy. x-ref target - figure 10 figure 10: device global interrupt enable register (dgier) (c_baseaddr + 0x1c) ta bl e 1 3 : device global interrupt enable regist er(dgier) description (c_baseaddr + 0x1c) bit(s) name access reset value description 31 gie r/w 0 global interrupt enable enables all individually enabled interrupts to be passed to the interrupt controller. 0 = disabled 1 = enabled 30 - 0 reserved n/a n/a reserved 0 4 3 31 occu p a ncy v a l u e res erved DS742_09 0 30 31 res erved DS742_10
DS742 january 18, 2012 www.xilinx.com 13 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) ip interrupt status register (ipisr) up to nine unique interrupt conditions are possible depe nding upon whether the system is configured with fifos or not as well as if it is configured in master mode or slave mode. a system without fifos has seven interrupts. the interrupt controller has the 32-bit interrupt status regis ter that can enable each interrupt independently. this register collects all of the interrupt events. bit assignments are shown in figure 11 and described in table 14 . the interrupt register is a read/toggle on write register. writ ing a 1 to a bit position within the register causes the corresponding bit to toggle . all register bits are cleared upon reset. x-ref target - figure 11 figure 11: ip interrupt status register (ipisr) (c_baseaddr + 0x20) ta bl e 1 4 : ip interrupt status register (ipi sr) description (c_baseaddr + 0x20) bit(s) name access reset value description 31 - 9 reserved n/a n/a reserved 8 drr_not_ empty r/tow (1) 0 drr not empty ipisr bit(8) is the drr not empty bit. the assertion of this bit is applicable only in the case where c_fifo_exist = 1 and the core is configured in slave mode. this bit is set when the drr fifo receives the first data value during the spi transaction. this bit is set by one-clock period strobe to the interrupt register when the core receives first data beat. note: the assertion of this bit is applicable only when the c_fifo_exist = 1 and the core is configured in slave mode. in c_fifo_exist = 0, this bit always return 0. it is recommended to use this bit only when c_fifo_exist = 1 and the core is configured in slave mode. 7 slave_ select_ mode r/tow (1) 0 slave select mode ipisr bit(7) is the slave select mode bit. the assertion of this bit is applicable only when the core is configured in slave mode. this bit is set when the other spi master co re selects the core by asserting the slave select line. this bit is set by one-clock period strobe to the interrupt register. note: this bit is applicable only when the core is configured in the slave mode. 6 tx fifo half empty r/tow (1) 0 transmit fifo half empty ipisr bit(6) is the transmit fifo half-empty interrupt. this bit is set by a one-clock period strobe to the interrupt register when the occupancy value is decremented from " 1000 " to " 0111 ". the value "0111" means ther e are 8 elements in the fifo to be transmitted. note: this interrupt exists only if the axi spi ip core is configured with fifos. 5 drr overrun r/tow (1) 0 data receive regi ster/fifo overrun ipisr bit(5) is the data receiv e fifo overrun interrupt. this bit is set by a one-clock period strobe to the interrupt register when an attempt to write data to a full receive register or fifo is made by the spi co re logic to complete an spi transfer. this can occur when the spi device is in either master or slave mode. 0 54 3 76 2 31 1 s l a ve modf modf dtr under-r u n dtr empty res erved drr over-r u n drr f u ll tx fifo h a lf empty s l a ve mode_s elect 8 drr_not_empty 9 DS742_11
DS742 january 18, 2012 www.xilinx.com 14 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) 4 drr full r/tow (1) 0 data receive register/fifo full ipisr bit(4) is the data receive register full interrupt. without fifos, this bit is set at the end of an spi element (an element can be a byte, half-word or word depending on the value of c_num_transfer_bits gene ric) transfer by a one-clock period strobe to the interrupt register. with fifos, this bit is set at the end of the spi element transfer when the receive fifo has been filled by a one-clock period strobe to the interrupt register. 3 dtr under run r/tow (1) 0 data transmit register/fifo underrun ipisr bit(3) is the data transmit register/fif o underrun interrupt. this bit is set at the end of an spi element transfer by a one-clock period strobe to the interrupt register when data is requested from an "empty" tr ansmit register/fifo by the spi core logic to perform an spi transfer. this can occur only when the spi device is configured as a slave and is enabled by the spe bit as set. all zeros are loaded in the shift register and transmitted by the slave in an underrun condition. 2 dtr empty r/tow (1) 0 data transmit register/fifo empty ipisr bit(2) is the data transmit register/f ifo empty interrupt. without fifos, this bit is set at the end of an spi element trans fer by a one-clock period strobe to the interrupt register. with fifos, this bit is set at the end of the spi element transfer when the transmit fifo is emptied by a one-clock period strobe to the interrupt register. see section transfer ending period . in the context of the m68hc11 reference manual, when configured without fifos, this interrupt is equivalent in information content to the complement of the spi transfer complete flag spif interrupt bit. in master mode if this bit is set to 1, no more spi transfers are permitted. 1 slave modf r/tow (1) 0 slave mode-fault error ipisr bit(1) is the slave mode-fault error flag. this interrupt is generated if the ss signal goes active while the spi device is configured as a slave but is not enabled. this bit is set immediately upon ss going active and continually set if ss is active and the device is not enabled. 0modfr/tow (1) 0 mode-fault error ipisr bit(0) is the mode-fault error flag. th is interrupt is generated if the ss signal goes active while the spi device is configur ed as a master. this bit is set immediately upon ss going active. notes: 1. tow = toggle on write. writing a 1 to a bit position within the register causes the corresponding bit position in the registe r to toggle. ta bl e 1 4 : ip interrupt status register (ipi sr) description (c_baseaddr + 0x20) (cont?d) bit(s) name access reset value description
DS742 january 18, 2012 www.xilinx.com 15 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) ip interrupt enable register (ipier) the interrupt controller ipier register allows the system in terrupt output to be active. this interrupt is generated if the enabled bit in ipier detects any activity on the corr esponding ipisr bit. the ipie r has an enable bit for each defined bit of the ipisr as shown in figure 12 and described in table 15 . all bits are cleared upon reset. x-ref target - figure 12 figure 12: ip interrupt enable register (ipier) (c_baseaddr + 0x28) ta bl e 1 5 : ip interrupt enable register (i pier) description (c_baseaddr + 0x28) bit(s) name access reset value description 31 - 9 reserved n/a n/a reserved 8 drr_not_empty r/w 0 drr_not_empty 0 = disabled 1 = enabled note: the setting of this bit is applicable only when c_fifo_exist = 1 and the core is configured in slave mode. if c_fifo_exist = 0, setting of this bit has no effect, which means that this bit is not set in ipier. therefore, it is recommended to use this bit only in c_fifo_exist = 1 condition when the core is configured in slave mode. 7 slave_select_mode r/w 0 slave_select_mode 0 = disabled 1 = enabled this bit is applicable only when the core is configured in slave mode. in master mode, setting this bit has no effect. 6 tx fifo half empty r/w 0 transmit fifo half empty 0 = disabled 1 = enabled note: this bit is meaningful only if the axi spi ip core is configured with fifos. 5 drr overrun r/w 0 receive fifo overrun 0 = disabled 1 = enabled 4 drr full r/w 0 data receive register/fifo full 0 = disabled 1 = enabled 3 dtr underrun r/w 0 data transmit fifo underrun 0 = disabled 1 = enabled 2 dtr empty r/w 0 data transmit register/fifo empty 0 = disabled 1 = enabled 0 54 3 62 31 1 s l a ve modf modf dtr under-r u n dtr empty res erved drr over-r u n drr f u ll tx fifo h a lf empty 7 s l a ve mode_s elect 8 drr_not_empty 9 DS742_12
DS742 january 18, 2012 www.xilinx.com 16 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) design description spi device features in addition to the features listed in the features section, the spi device also includes the following standard features: ? supports multi-master configuration within the field programmable gate array (fpga) with separated _i, _o, _t representation of 3-state ports. ? works with n times 8-bit data char acters in default configuration. the default mode implements manual control of the ss output via data written to the spis sr. this appears directly on the ss output when the master is enabled. this mode can be used only with external slave devices. an optional operation where the ss output is toggled automatically with each 8-bi t character transfer by the master devi ce can be selected via a bit in the spicr for spi master devices. ? multi-master environment supported (i mplemented with 3-state drivers and requires software arbitration for possible conflict). see the spi in multi-master configuration section. ? multi-slave environment supported (automatic generation of additional slave select output signals for the master). ? supports maximum spi clock rates up to one-half of the axi clock rate in master mode and one-fourth of the axi clock rate in slave modes. c_sck_ratio = 2 is not supported in slave mode (due to the synchronization method used between the axi and spi clocks). it is requir ed to take care of the axi and external clock signals alignment when configured in slave mode. ? parameterizable baud rate generator. ? the write collision error (wcol) flag is not supported as a write collision error as described in the m68hc11 reference manual. the user must not write to the transmit register when an spi data transfer is in progress. ? back-to-back transactions are supported, which means there can be multiple byte /half-word/word transfers taking place without interruption, pr ovided that the transmit fifo neve r gets empty and the receive fifo never gets full. ? all spi transfers are full-duplex where an 8-bit data char acter is transferred from the master to the slave and an independent 8-bit data character is tr ansferred from the slave to the master. this can be viewed as a circular 16-bit shift register; an 8-bit shift regi ster in the spi master device and anot her 8-bit shift register in a spi slave device that are connected. ? this ip cannot be used for fpga bitstream programm ing through the spi interface during power-on reset state. ? the data transfer and registering mechanism of this core is synchronized with the axi clock. user should take care while configuring the ip. see the timing parameters for the targeted device while configuring the core and the c_sck_ratio parameter. 1 slave modf r/w 0 slave mode-fault error flag 0 = disabled 1 = enabled 0modfr/w0 mode-fault error flag 0 = disabled 1 = enabled ta bl e 1 5 : ip interrupt enable register (i pier) description (c_baseaddr + 0x28) (cont?d) bit(s) name access reset value description
DS742 january 18, 2012 www.xilinx.com 17 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) spi in multi-mast er configuration the spi bus to a given slave device (n-th device) consists of four wires, serial clock (sck), master out slave in (mosi), master in slave out (miso) and slave select (ss (n)). the signals sck, mosi and miso are shared for all slaves and masters. see figure 13 . each master spi device has the functionality to generate an active low, one-hot encoded ss (n) vector where each bit is assigned an ss signal for each slave spi device. it is possible for spi master/slave devices to be both internal to the fpga and spi slave devices to be external to the fpga. spi pins ar e automatically generated through xilinx platform generator when interfacing to an external spi slave device. multiple spi master/slave devices are shown in figure 13 . optional fifos the user has the option to include fifos in the axi spi ip core as shown in figure 1 . because spi is full-duplex, both transmit and receive fifo s are instantiated as a pair. when fifos are implemented, the slave select address is requ ired to be the same for all data buffered in the fifos. this is required because a fifo for the slave select address is not implemented. because burst mode is not supported, both transmit and receive fifos are 16 elements deep and are accessed vi a single axi transactions. x-ref target - figure 13 figure 13: multi-master configuration block diagram ss(3) ss(2) ss(1) ss(0) mosi miso sck spisel ss(1) ss(2) ss(3) s pi de vic e 0 mosi miso sck spisel ss(1) ss(2) ss(3) s pi de vic e 1 mosi miso sck spisel ss(1) ss(2) ss(3) s pi de vic e 2 mosi miso sck spisel ss(1) ss(2) ss(3) s pi de vic e 3 sla ve-only device s (not s hown) ha ve only spisel local sla ve s elect ports and do not ha ve ss(n) remote sla ve s elect ports DS742_13
DS742 january 18, 2012 www.xilinx.com 18 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) the transmit fifo is write-only. when data is written in the fifo, the occupancy number is incremented and when an spi transfer is completed, the number is decremented. as a consequence of this operation, aborted spi transfers still have the data available for the transmission retry. the transfers can only be aborted in the master mode by setting master transaction inhibit bit, bi t(23) of spicr to 1 during a transfer. setting this bit in the slave mode has no effect on the operation of the slave. these aborted tran sfers are on the spi interface. the occupancy number is a read-only register. if a write is attempted when the fifo is full, then an acknowledgement is given along with an error signal generation. interrupts associated with the transmit fifo include data transmit fifo empty, transmit fifo half empty and transmit fifo underrun. see the section on interrupt register set description for details. the receive fifo is read-only. when data is read from the fifo, the occupancy number is decremented and when an spi transfer is completed, the number is incremented. if a read is attempted when the fifo is empty, then acknowledgement is given along with an error signal generation. when the receive fifo becomes full, the receive fifo full interrupt is generated. data is automatically written to the fifo fr om the spi module shift register after the completion of an spi transfer. if the receive fifo is fu ll and more data is received, then a receive fifo overflow interrupt is issued. when this happens, all data attempted to be written to the full receive fifo by the spi module is lost. spi transfers, when the axi spi ip core is configured with fifos, can be started in two different ways depending on when the enable bit in the spicr is set. if the enable bit is set prior to the first data being loaded in the fifo, then the spi transfer begins immediately af ter the write to the master transmit fifo. if the fifo is emptied via spi transfers before additional elements ar e written to the transmit fifo, an inte rrupt is asserted. when the axi to spi sck frequency ratio is sufficiently small, this scenario is highly probable. alternatively, the fifo can be loaded up to 16 elements and then the enable bit can be set which starts the spi transfer. in this case , an interrupt is issued after all elements are transferred. in all cases, more data can be written to the transmit fifos to increase the number of elements transferred before emptying the fifos. local master loopback operation local master loopback operation, although not included in the m68hc11 reference manual, has been implemented to expedite testing. this operation is selected via setting the loopback bit in the spicr; the transmitter output is internally connected to the receiver in put. the receiver and transmitter operat e normally, except that received data (from a remote slave) is ignored. this operation is relevant only when the spi device is configured as a master. hardware error detection the spi architecture relies on software controlled bus arbi tration for multi-master configurations to avoid conflicts and errors. however, limited error detection is implem ented in the spi hardware. the first error detection mechanism to be discussed is contention error detection. this detects when an spi device configured as a master is selected (that is, its ss bit is asserted) by another spi device simultaneously configured as master. in this scenario, the master being selected as a slave immediately drives its outputs as necessary to avoid hardware damage due to simultaneous drive contention. the master also sets the mode-fault error (modf) bit in the spisr. this bit is automatically cleared by reading the spisr. following a modf error, the master must be disabled and re-enabled with correct data. when configured with fifos, this might require clearing the fifos. a similar error detection mechanism has been implemented for spi slave devices. the error detected is when a spi device configured as a slave but is not enabled and is selected (that is, its ss bit is asserted) by another spi device. when this condition is detected, ipisr bit(1) is set by a strobe to the ipisr register.
DS742 january 18, 2012 www.xilinx.com 19 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) underrun and overrun conditions error detection is also provided. underrun conditions can happen only in slave mode operation. this happens when a master commands a transfer but the slave does not have data in the transmit register or fifo for transfer. in this case, the slave underrun interrupt is asserted and the slave shift register is loaded with all zeros for transmission. overrun can ha ppen to both master and slave devices where a transfer occurs when the receive register or fifo is full. during an overrun condition, the data received in that transfer is not registered (it is lost) and the ipisr overrun interrupt bit(5) is asserted. precautions to be taken while a ssigning the c_sck_ratio parameter the axi spi ip core is tested in hardware with the spi slave devices like serial eeproms, atmel, stmicro-electronics and intel flash memories. read the data sheet of the targeted spi slave flash memory or eeproms for maximum speed of operation. it is the responsi bility of the user to mention the correct values while deciding the axi clock and select ing the c_sck_ratio parameter of the core. the axi clock and the c_sck_ratio decide the clock at sck pin of axi spi ip co re. while using different external spi slave devices, the c_sck_ratio should be set carefully and the maximum cloc k frequencies supported by all the external spi slave devices should be taken into account. spi slave mode the axi spi core can be configured in the slave mode by co nnecting the external master?s slave select line to spisel and by setting bit 2 of spi control register (spicr) to '0'. all the incoming signals are synchronized to the axi when c_sck_ratio > 4. due to the tight timing requirements when c_sck_ratio = 4 the incoming sck clock signal and its synchronized signals are used directly in the internal logic. therefore it is required that the external clock be synchronized with the axi clock when c_sck_ratio = 4. for other c_sck_ratio values, it is preferred, but might not be necessary, to have such synchronization. during the slave mode operation it is strongly recommended to use the fifo by setting c_fifo_exist = 1. in the slave mode, two new interrupts are available in ipisr d rr_not_empty - bit 8 and slave_mode_select - bit 7 along with the available interrupts. before other spi master star ts communication, it is mandatory to fill the slave core transmit fifo with the required data beats. after the master starts communication, with the core configured in slave mode, the core will transfer data until the data ex ists in its transmit fifo. at the end of last data beat transmitted from slave fifo, the core (in slave mode) generates the dtr empty signal to notify that new data beats needed to be filled in its transmit fifo before further communication is started. spi transfer formats spi clock phase and polarity control software can select any of four combinations of serial clock (sck) phase and polarity with programmable bits in the spicr. the clock polarity (cpol) bit selects an active high (the clock?s idle state = low) or active low clock (the clock?s idle state = high). determination of whether the edge of interest is the rising or falling edge depends on the idle state of the clock (that is, cpol setting). the clock phase (cpha) bit can be set to select one of two different transfer formats. if cpha = 0, data is valid on the first sck edge (rising or falling) after ss (n) has been asserted. if cpha = 1, data is valid on the second sck edge (rising or falling) after ss (n) has asserted. for successful transfers the clock phase and polarity must be identical for the master spi device and the selected slave device. the first sck cycle begins with a transi tion of sck signal from its idle state and this denotes the start of the data transfer. because the clock transition from idle denotes th e start of a transfer, the m68hc11 specification notes that
DS742 january 18, 2012 www.xilinx.com 20 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) the ss (n) line can remain active low between successive transfer s. the specification states that this format is useful in systems with a single master and single slave. in th e context of the m68hc11 specification, transmit data is placed directly in the shift register upon a write to the transmit register. consequently, it is the user?s responsibility to ensure that the data is properly loaded in the spissr register prior to the first sck edge. the ss signal is toggled for all cpha configurations and there is no support for spisel being held low. it is required that all ss signals be routed betwee n spi devices internally to the fpga. toggling the ss signal reduces fpga resources. the different transfer formats are described in the following sections. cpha equals zero transfer format figure 14 shows the timing diagram for an spi data write-read cycle when cpha = 0. the waveforms are shown for cpol = 0, lsb first = 0, and the value of generic c_sck_ ratio = 4. all axi and spi signals have the same relation with respect to s_axi_aclk and sck, respectively. signal sck remains in the idle state un til one-half period following the assertion of the slave select line which denotes the start of a transaction. because assertion of the ss (n) line denotes the start of a transfer, it must be deasserted and re-asserted for sequential el ement transfers to the same slave device. one bit of data is transferred per sc k clock period. data is shifted on one edge of sck and is sampled on the opposite edge when the data is stable. consistent with the m68hc11 spi specification, selection of clock polarity and a choice of two different clocking pr otocols on an 8-bit/16-bit/32-bit orient ed data transfer is possible via bits in the spicr. the mosi and miso ports behave differ ently depending on whether the spi device is configured as a master or a slave. when configured as a master, the mosi port is a serial data output port and the miso is a serial data input port. the opposite is true when the devi ce is configured as a slave; the miso port is a slave serial data output port and the mosi is a serial data input port. there can be only one master and one slave transmitting data at any given time. the bus architecture provides limited contention er ror detection (that is, multiple devices driving the shared miso and mosi signals) and requires the software to pr ovide arbitration to prevent possible contention errors. all sck, mosi, and miso pins of all devices are respectively hardwired together. for all transactions, a single spi device is configured as a master and all other spi devices on the spi bus are configured as slaves. the single master drives the sck and mosi pins to the sck and mosi pins of the slaves. the uniquely selected slave device drives data out from its miso pin to the miso master pin, thus realizing full-duplex communication. the nth bit of the ss (n) signal selects the nth spi slave with an active low signal. all other slave devices ignore both sck and mosi signals. in addition, the non-selected slaves (that is, ss pin high) drive their miso pin to 3-state so as not to interfere with spi bus activities. x-ref target - figure 14 figure 14: data write-read cycle on spi bus with cpha = 0 and spicr(24) = 0 for 8-bit data 3#+ -/3) -)3/ 33 30)3%, $t $t $t $t $t $t $t $r $r $r $r $r $r $r

!!ddressof4ransmit?$ata2egister $r2eceived$ata

.otdefinedbutnormally-3"ofcharacterjustreceived 3#+isshownfor#0/, $t4ransmitted$ata ,egend $t $r $3?
DS742 january 18, 2012 www.xilinx.com 21 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) when external slave spi devices are implemented, sck, mosi and miso, as well as the needed ss (n) signals, are brought out to pins. all signals are true 3-state bus signal s and erroneous external bus activity can corrupt internal transfers when both internal and external devices are present. the user must ensure that the external pull-up or pull-dow n of external spi 3-state sign als are consistent with the sink/source capability of the fpga i/o drivers. recall that the i/o drivers can be configured for different drive strengths as well as internal pull-ups . the 3-state signals for multiple extern al slaves can be implemented as per system design requirements, but the external bu s must follow the spi m68hc11 specifications. cpha equals one transfer format with cpha = 1, the first sck cycle begins with an edge on the sck line from its inactive level to active level (rising or falling depending on cpol) as shown in figure 15 . the waveforms are shown for cpol = 0, lsb first = 0, and the value of generic c_sck_ratio = 4. all axi and spi si gnals have the same relation with respect to saxi_clk and sck, respectively. spi protocol slave select assertion modes the spi protocol is designed to have automatic slaves select assertion and ma nual slave select assertion which are described in the following sections. all the spi transfer formats described in spi clock phase and polarity control section are valid for both automatic an d manual slave select assertion mode. spi protocol with automatic slave select assertion this section describes the spi protocol where slave select (ss (n)) is asserted automatically by the spi master device (spicr bit(7) = 0). this is the configuration mode provided to allow transfer of data with automatic toggling of the slave select (ss ) signal until all the elements are transferred. in this mode the data in the spissr register appears on the ss (n) output when the new transfer starts. after every byte (or element) transfer, the ss (n) output goes to 1. the data in spissr register again appears on the ss (n) output at the beginning of a new transfer. the user does not need to manually control the slave select signal. spi protocol with manual slave select assertion this section briefly describes the spi protocol where the slave select (ss (n)) is manually asserted by the user (that is, spicr bit(7) = 1). this is the configuration mode provid ed to allow transfers of an arbitrary number of elements without toggling the slave select until al l the elements are transferred. in this mode, the data in the spissr register appears directly on the ss (n) output. sck must be stable before the assertion of slave select. therefore, when manual slave select mode is used, the spi master must be enabled first (spicr bit(7) = 1) to assert sck to the idle state prior to asserting slave select. x-ref target - figure 15 figure 15: data write-read cycle on spi bus with cpha = 1 and spicr(24) = 0 for 8-bit data $t $t $t $t $t $t $t $r $r $r $r $r $r $r

!!ddressof4ransmit?$ata2egister $r2eceived$ata

.otdefinedbutnormally-3"ofpreviouslytransmitted characterforthesameslave 3#+isshownfor#0/, $t4ransmitted$ata ,egend $t $r 3#+ -/3) -)3/ 33 30)3%, $ 3
DS742 january 18, 2012 www.xilinx.com 22 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) the master transfer inhibit (spicr bit(8) ) can be used to inhibit master transactions until the slave select is asserted manually and all data registers of fifos are initialized as required. this can be used before the first transaction and after any transaction that is allowed to complete. when the preceding rules are followed, the timing is the same as presented for the automatic slave select assertion mode with the exception that assertion of the slave select signal and the number of elements transf erred is controlled by the user. beginning and ending spi transfers the details of the beginning and ending periods depend on the cpha format selected and whether the spi is configured as a master or a slave. th e following sections describe the beginni ng and ending period for spi transfers. transfer beginning period the definition of the transfer beginning period for the axi spi ip core is consistent with the m68hc11 reference manual. this manual can be referenced for more details. al l spi transfers are started and controlled by a master spi device. as a slave, the processor consid ers a transfer to begin with the first sck edge or the falling edge of ss , depending on the cpha format selected. when cpha equals zero, the falling edge of ss indicates the beginning of a transfer. when cpha equals one, the first edge on the sck indicates the start of the transfer. in either cpha format, a transfer can be aborted by deasserting the ss (n) signal. this causes the spi slave logic and bit counters to be reset. in this implementation, the software driver can deselect all slaves (that is, ss (n) is driven high) to abort a transaction. although the hardware is capable of changing slaves during the middle of a single or burst transfer, it is recommended that the software be designed to prevent this. in slave configuration, the data is tran smitted from the spidtr register on th e first axi rising clock edge following ss signal being asserted. the data should be available in the register or fifo. if data is not available, then the underrun interrupt is asserted. transfer ending period the definition of the transfer ending period for the ax i spi ip core is consistent with the m68hc11 reference manual. the spi transfer is signaled complete when the sp if flag is set. however, depending on the configuration of the spi system, there might be additional tasks to be performed before the system can consider the transfer complete. when configured without fifos, the rx_ful l bit, bit(1) in the spisr is set to denote the end of a transfer. when data is available in the spidrr register, bit(4) of the ipisr is asserted as well. the data in the spidrr is sampled on the same clock edge as the assertion of the spidrr register full interrupt. when the spi device is configured as a ma ster without fifos, the following occurs: ? rx_empty bit, bit(0) and tx_full bi t, bit(3) in the spisr are cleared. ? tx_empty bit, bit(2) and rx_ful l bit, bit(1) in spisr are set. ? drr full bit, bit(4) and slave modf bi t, bit(1) in the ipisr are set on the first rising axi clock edge after the end of the last sck cycle. the end of the last sck cycle is a transition on sck for cpha = 0, but is not denoted by a transition on sck for cpha = 1. see figure 14 and figure 15 . however, the internal master clock provides this sck edge which prompts the setting/clearing of the bits noted. in this design, a counter was implemented which allows th e simultaneous setting of spisr and ipisr bits for both master and slave spi devices. external spi slave devices can use an internal clock that is asynchronous to the sck clock. this can cause status bi ts in the spisr and ipisr to be inconsistent with each other. therefore, the axi spi ip core cannot be used with external slav e devices that do not use the axi clock.
DS742 january 18, 2012 www.xilinx.com 23 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) when the axi spi ip core is configured with fifos and a series of consecutive spi 8-bit/16-bit/32-bit element transfers are performed, spisr bits and ipisr do indicate completion of the first and the last spi transfers with no indication of intermediate transfers. the only way to monitor when in termediate transfers are completed is to monitor the receive fifo occupancy number . there is also an interrupt when the transmit fifo is half empty, bit(6) of ipisr. when the spi device is configured as a slave, the setting/clearing of the bits discussed previously for a master coincides with the setting/cleari ng of the master bits for both cases of cpha = 0 and cpha = 1. recall that for cpha = 1 (that is, no sck edge denoting the end of th e last clock period) the slave has no way of knowing when the end of the last sck period occurs unless an axi cl ock period counter was includ ed in the spi slave device. spi registers flow description this section provides information on setting the spi registers to initiate and complete bus transactions. spi master device with or without fifos where the slave select vector is asserted manually via spicr bit(24) assertion. this flow allows the transfer of n number of byte/half-wo rd/word by toggling of the sl ave select vector just once. this is the default mode of operation. the user can fo llow the subsequent steps to successfully complete an spi transaction: 1. start from proper state in cluding spi bus arbitration. 2. configure device global interrupt enable re gister (dgier) and ipier registers as desired. 3. configure target slave spi device as required. this in cludes configuration of the dtr and control register of slave spi core and enabling it. 4. write initial data to master spidtr register/fif o. this assumes that the spi master is disabled. 5. ensure the spissr register has all ones. 6. write configuration data to master spi device spicr as desired including setting bit(7) for manual asserting of ss vector and setting both enable bit an d master transfer inhibit bit. this initializes sck and mosi but inhibits transfer. 7. write to spissr to manually assert ss vector. 8. write the preceding configuration data to master spi de vice spicr, but clear inhibit bit which starts transfer. 9. wait for interrupt (typically ipisr bit(4)) or poll status for completion. wait time depends on spi clock ratio. 10. set master transaction inhibit bit to service interrupt request. write new data to master register/fifos and slave device and then clear master tran saction inhibit bit to continue n 8-bit element transfer. an overrun of the spidrr register/fifo can occur if the spidrr register/fifos are not read properly. in addition, sck will have stretched idle levels between element transfers (or groups of element transfers if utilizing fifos) and mosi can transition at the end of a element transfer (or group of tr ansfers), but will be stable at least one-half sck period prior to sampling edge of sck. 11. repeat previous two steps until all data is transferred. 12. write all ones to spissr or exit manual slave select assert mode to deassert ss vector while sck and mosi are in the idle state. 13. disable devices as desired. spi master and slave devices without fifos performi ng one 8-bit/16-bit/32-bit transfer (optional mode) follow these steps to complete an spi transaction: 1. start from proper state in cluding spi bus arbitration. 2. configure master dgier and ipier. also config ure slave dgier and ipier registers as desired.
DS742 january 18, 2012 www.xilinx.com 24 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) 3. write configuration data to mast er spi device spicr as required. 4. write configuration data to slave spi device spicr as required. 5. write the active low, one-hot encoded slave select address to the master spissr. 6. write data to slave spid tr register as required. 7. write data to master spidtr register to start transfer. 8. wait for interrupt (typically ipisr bi t(4)) or poll status for completion. 9. read ipisr of both master and slave spi devices as required. 10. perform interrupt requests as required. 11. read spisr of both master and slave spi devices as required. 12. perform actions as required or dictated by spisr data. spi master and slave devices where registers/fifos are filled before spi transfer is started and multiple discrete 8-bit transfers are performed (optional mode) user can follow the subsequent steps to successfully complete an spi transaction: 1. start from proper state in cluding spi bus arbitration. 2. configure master dgier and ipier. also config ure slave dgier and ipier registers as desired. 3. write configuration data to mast er spi device spicr as required. 4. write configuration data to slave spi device spicr as required. 5. write the active low, one-hot encoded slave select address to the master spissr. 6. write all data to slave spidtr register/fifo as required. 7. write all data to master spidtr register/fifo. 8. write enable bit to master spicr which starts transfer. 9. wait for interrupt (typically ipisr bi t(4)) or poll status for completion. 10. read ipisr of both master and slave spi devices as required. 11. perform interrupt requests as required. 12. read spisr of both master and slave spi devices as required. 13. perform actions as required or dictated by spisr data. spi master and slave devices with fifos where some initial data is written to fifos, the spi transfer is started, data is written to the fifos as fast or faster than the spi transfer and multiple discrete 8-bit transfers are performed (optional mode). the user can follow the subsequent steps to successfully complete an spi transaction: 1. start from proper state in cluding spi bus arbitration. 2. configure master dgier and ipier. also config ure slave dgier and ipier registers as desired. 3. write configuration data to mast er spi device spicr as required. 4. write configuration data to slave spi device spicr as required. 5. write the active low, one-hot encoded slave select address to the master spissr. 6. write initial data to slave transmit fifo as required. 7. write initial data to master transmit fifo. 8. write enable bit to master spicr which starts transfer. 9. continue writing data to both master and slave fifos. 10. wait for interrupt (typically ipisr bi t(4)) or poll status for completion.
DS742 january 18, 2012 www.xilinx.com 25 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) 11. read ipisr of both master and slave spi devices as required. 12. perform interrupt requests as required. 13. read spisr of both master and slave spi devices as required. 14. perform actions as required or dictated by spisr data. steps to be followed when the core is configured in slave mode 1. set the desired clock ratio using c_sck_ratio = up to 4 is allowed. 2. fill the spidtr with the data; enable the interrupts as required for slave mode. 3. enable the slave mode through spic r and enable the core through spe. 4. connect the spisel input of the core to the ch ip select signal of ex ternal master spi core. 5. select the core using the active low spisel bit . 6. after the core is selected by asserting the spisel, the core waits for the master?s clock on sck line and inputs on the mosi line. 7. when the master starts the clock, data is exchanged between the master and slave on miso and mosi line respectively. 8. after each exchange of 8 bit of data, the core perf orms local housekeeping work. this includes storing the received data in the spidrr, loading the new data from spidtr into the local shift register for a new transfer and resetting the internal counter for the next transfer. 9. all the internal processes in step 8 take approximately 4 axi clock cycles. it is preferable to allow an idle time of 6 clocks in between 2 consecutive transactions. 10. the core transfers the data until its drr fifo is empty. when the complete transfer is finished from the core the interrupt sets to indicate that the drr is empty and the dtr is full. at this point, unless the dtr is re-filled, the core cannot communicate with master. 11. read the drr and re-fill the dtr and repeat the steps above. design constraints timing constraints when the core is added in the mhs of xps build, the timi ng constraints for the core are taken care at the system level by the xps tool. design implementation target technology the target fpga technologies for the core are the supported device families listed in the logicore ip facts . device utilization and performance benchmarks core performance because the axi spi ip core is used with other design modules in the fpga, the utilization and timing numbers reported in this section are estimates only. when the core is combined with other designs in the system, the utilization of fpga resources and ti ming of the core design can vary from the results reported here. the core resource utilization for various parameter comb inations measured with a artix?-7 fpga as the target device are detailed in table 16 .
DS742 january 18, 2012 www.xilinx.com 26 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) the core resource utilization for various parameter comb inations measured with a virtex?-7 fpga as the target device are detailed in table 17 . the core resource utilization for various parameter comb inations measured with a kintex?-7 fpga as the target device are detailed in table 18 . ta bl e 1 6 : performance and resource utilization benchmarks on a artix-7 fpga (xc7a175tdie-3) parameter values (other parameters at default values) device resources performance c_fifo_exist c_sck_ratio c_num_ss_bits c_num_transfer_bits slices slice flip- flops luts fmax (mhz) 0 2 2 8 101 157 200 150 1 2 2 8 124 156 256 150 0 4 2 8 106 167 233 150 1 4 2 8 110 167 273 150 0 32 2 8 101 171 235 150 1 32 2 8 150 171 276 150 ta bl e 1 7 : performance and resource utilization benchmarks on a virtex-7 fpga (xc7v285tffg484-3) parameter values (other parameters at default values) device resources performance c_fifo_exist c_sck_ratio c_num_ss_bits c_num_transfer_bits slices slice flip- flops luts fmax (mhz) 0 2 2 8 101 156 200 200 1 2 2 8 96 156 253 200 0 4 2 8 111 167 222 200 1 4 2 8 115 167 273 200 0 32 2 8 101 171 232 200 1 32 2 8 128 171 271 200
DS742 january 18, 2012 www.xilinx.com 27 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) the core resource utilization for various parameter combinations measured with a virtex ? -6 fpga as the target device are detailed in table 19 . the axi spi ip core resource utilization for variou s parameter combinations measured with a spartan ? -6 fpga as the target device are detailed in table 20 . ta bl e 1 8 : performance and resource utilization benchmarks on a kintex-7 fpga (xc7v285tffg484-31) parameter values (other parameters at default values) device resources performance c_fifo_exist c_sck_ratio c_num_ss_bits c_num_transfer_bits slices slice flip- flops luts fmax (mhz) 0 2 2 8 109 156 200 200 1 2 2 8 119 156 253 200 0 4 2 8 92 167 222 200 1 4 2 8 118 167 270 200 0 32 2 8 107 171 223 200 1 32 2 8 119 171 270 200 ta bl e 1 9 : performance and resource utilization benchmarks on a virtex-6 fpga (xc6vlx130tff1156-1) parameter values (other parameters at default values) device resources performance c_fifo_exist c_sck_ratio c_num_ss_bits c_num_transfer_bits slices slice flip- flops luts fmax (mhz) 0 2 2 8 79 138 166 209 1 2 2 8 92 139 208 192 0 4 2 8 96 149 290 193 1 4 2 8 101 149 224 206 0 32 2 8 82 153 200 192 1 32 2 8 112 153 224 182
DS742 january 18, 2012 www.xilinx.com 28 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) system performance to measure the system performance (f max ) of this core, the core was added to a virtex-6 fpga system and a spartan-6 fpga system as the device under test (dut) as illustrated in figure 16 . because the axi spi core is used with other design mo dules in the fpga, the utilization and timing numbers reported in this section are estimates only. when this core is combined with other designs in the system, the design?s fpga resources and timing usage can vary from the results reported here. the target fpga was filled with logic to drive the lut and block ram utilization to approximately 60% and the i/o utilization to approximately 80%. using the default tool options and the slowest speed grade for the target fpga, the resulting target fmax numbers are shown in table 21 . ta bl e 2 0 : performance and resource utilization benchmarks on a spartan-6 fpga (xc6slx45tfgg484-3) parameter values (other parameters at default values) device resources performance c_fifo_exist c_sck_ratio c_num_ss_bits c_num_transfer_bits slices slice flip- flops luts fmax (mhz) 0 2 2 8 85 138 155 125 1 2 2 8 96 138 206 128 0 4 2 8 109 153 192 133 1 4 2 8 105 150 230 127 0 32 2 8 92 155 182 135 1 32 2 8 109 154 235 130
DS742 january 18, 2012 www.xilinx.com 29 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) the target f max is influenced by the exact system and is provided for guidance. it is not a guaranteed value across all systems. x-ref target - figure 16 figure 16: virtex-6 and spartan-6 devices f max margin system ta bl e 2 1 : axi spi system performance target fpga target fmax (mhz) axi-lite target fmax (mhz) axi4 target f max (mhz) microblaze ? xc6slx45t (1) 90 120 80 xc6vlx240t (2) 135 180 135 notes: 1. s6 lut utilization ~60%, block ram utilization ~70%, i/o utilization 80%, mb not on axi4 interconnect, axi4 interconnect configured with a single clock of 120mhz. 2. v6 lut utilization ~70%, block ram utilization ~70%, i/o utilization ~80%. DS742_16 axi4-lite domain microblaze controller axi intc axi gpio axi uartlite axi ddr memory controller axi cdma mdm microblaze proce ssor domain axi4 memory map domain block ram controller d_lmb i_lmb (m_axi_ic) device under te st (dut) (low speed sla ve) leds rs232 memory (m_axi_dp) axi4 memory map interconnect axi4-lite interconnect (m_axi_dc)
DS742 january 18, 2012 www.xilinx.com 30 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) specification exceptions exceptions from the motorola m 68hc11-rev. 4.0 reference manual 1. a slave mode-fault error interrupt is added to provide an interrupt if a spi device is configured as a slave and is selected when not enabled. 2. in this design, the spidtr and sp idrr registers have independent addresses. this is an exception to the m68hc11 specification which calls for two registers to have the same address. 3. all ss signals are required to be routed between spi devices internally to the fpga. this is because toggling of the ss signal is utilized in slaves to minimize fpga resources. 4. manual control of the ss signals is provided by setting bit(7) in the spicr register. when the device is configured as a master and is enabled an d bit(7) of the spicr register is set, the vector in the spissr register is asserted. when this mode is enabled, multiple el ements can be transferred without toggling the ss vector. 5. a control bit is provided to inhibit master transfers. this bit is effective in any master mode, but its main utility is for manual control of the ss signals. 6. in the m68hc11 implementation, the transmit register is transparent to the shift register which necessitates the write collision error (wcol) detection hardware. this is not implemented in this design. 7. the interrupt enable bit (spie) defined by the m68hc11 specifications which resides in the m68hc11 control register has been moved to the ipier register. in the position of the spie bit, there is a bit to select local master loopback mode for testing. 8. an option is implemented in this fpga design to implement fifos on both transmit and receive (full duplex only) mode. 9. m68hc11 implementation supports only byte transfer. in this design either a byte, half-word or word transfer can be configured via a generic c_num_transfer_bits. 10. the baud rate generator is specified by motorola to be programmable via bits in the control register; however, in this fpga design the baud rate generator is prog rammable via parameters in the vhdl implementation. therefore, in this implementation, run time configuratio n of the baud rate is not possible. furthermore, in addition to the ratios of 2, 4, 16 and 32, al l integer multiples of 16 up to 2048 are allowed. 11. the axi spi ip core is tested with atmel at45db161d and st microelectronics m25p 16 serial spi slave devices. these devices support spi modes 0 and 3. these devices have data valid time of 8 ns from the falling edge of sck. while operating with these devices at higher spee d of 50 mhz (most instructions supports this speed), the core should be configured in c_sc k_ratio = 2 mode (where the axi is configured to operate at 100 mhz). due to limited time availabili ty in the design as well as real spi slave behavior for data change, the data in the spi core is registered in the middle of each falling edge and the next consecutive rising edge. as per the m68hc11 document, the master should register data on each rising edge of sck in spi modes 1 and 3. note that the data registering mechanism when c_sck_ratio =2 follows a different pattern than specified in the standard (this is applicable to the data registering mechanism in the ip core only). the spi core when configured in master mode changes data on each fa lling edge and this behavior is as per the m68hc11 standard. 12. when the axi spi ip core is configured in slave mode, the data in the core is registered on the sck rising edge + 1 axi clock signal. internally, this data is registered on the next rising edge of axi. the core changes the data on the sck falling edge + axi clock cycle.
DS742 january 18, 2012 www.xilinx.com 31 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) list of acronyms acronym description amba advanced microcontroller bus architecture arm advanced risc machine axi advanced extensible interface brg baud rate generator cpha clock phase cpol clock polarity ddr double data rate dgier device global interrupt enable register drr data receive register dtr data transmit register dut device under test edk embedded development kit eeprom electrically erasable pr ogrammable read-only memory ff flip-flop fifo first in first out fpga field programmable gate array gpio general purpose input/output i/o input/output ip intellectual property ipic ip interconnect ipier ip interrupt enable register ipif ip interface ipisr ip interrupt status register ise integrated software environment lsb least significant bit lut lookup table miso master in slave out modf mode-fault error mosi master out slave in msb most significant bit ram random access memory rx receive sck serial clock spi serial peripheral interface spicr spi control register spidrr spi data receive register spidtr spi data transmit register spie spi interrupt enable
DS742 january 18, 2012 www.xilinx.com 32 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) support xilinx provides technical support for this logicore ip product when used as described in the product documentation. xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that are not defined in the documentation, if customized be yond that allowed in the product documentation, or if changes are made to any section of the design labeled do not modify . ordering information this xilinx logicore ip module is provided at no addi tional cost with the xilinx ise? design suite embedded edition software under the terms of the xilinx end user license . the core is generated using the xilinx integrated software environment (ise) embedded edition software (edk). information about this and other xilinx lo gicore ip modules is available at the xilinx intellectual property page. for information on pricing and availability of other xilinx logicore modules and software, please contact your local xilinx sales representative . reference documents to search for xilinx documentation, go to http://www.xilinx.com/support the following documents contain reference information im portant to understanding the axi spi ip core design: 1. motorola m68hc11-rev. 4.0 reference manual 2. motorola mpc8260 powerquicc ii? users manual 4/1999 rev. 0 3. axi4 amba? axi protocol version: 2.0 specification 4. logicore ip axi lite ipif (v1.01.a) data sheet ( ds765 ) 5. spartan-3an fpga in-system flash user guide ( ug333 ) 6. axi interconnect ip data sheet ( ds768 ) spisel spi slave select line spisr spi status register spissr spi slave select register srr software reset register ss (n) slave select tow toggle on write tx transmit uart universal asynchronous receiver transmitter ucf user constraints file vhdl vhsic hardware description language (vhsic an acronym for very high-speed integrated circuits) wcol write collision error xps xilinx platform studio xst xilinx synthesis technology acronym description (cont?d)
DS742 january 18, 2012 www.xilinx.com 33 product specification logicore ip axi serial peripheral interface (axi spi) (v1.02.a) revision history notice of disclaimer the information disclosed to you hereunder (the ?materials?) is provided solely for the selectio n and use of xilinx products. t o the maximum extent permitted by applicable law: (1) materials are made availa ble ?as is? and with al l faults, xilinx hereby disclaims all warranties and conditions, express, implied, or statutory, including but not limited to warranties of merchantability, non-infringement, or fitness for any particular purpose; and (2) xilinx shall not be liable (whether in contra ct or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the materials (includ ing your use of the materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffer ed as a result of any action br ought by a third party) even if such damage or loss was reasonably foreseeable or xilinx had b een advised of the possibility of the same. xilinx assumes no obligation to correct any errors contained in the materials or to notify you of updates to the materials or to product specifications. you may not reproduce, mo dify, distribute, or publicly display th e materials without prior written consent. certain products are subject to the terms and conditions of the limited warranties which can be viewed at http://www.xilinx.com/warranty.htm ; ip cores may be subject to warranty and suppo rt terms contained in a license issued to you by xilinx. xilinx products are not desi gned or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability fo r use of xilinx products in critical applications: http://www.xilinx.com/warranty.htm#critapps . date version revision 09/21/10 1.0 first release of the core with axi interface support. the previous release of this document was ds570. 09/21/10 1.0.1 documentation only. added inferred parameters text on page 4. 09/28/10 1.1 updated version and utilization table. 12/14/10 1.2 updated to v1.01.a version; up dated tools to 12.4. 6/22/11 1.3 updated for 13.2 release; removed design constraints section; added 7 series support; modified timing constraints section; modified allowable value for c_sck_ratio in table 1. 7/6/11 1.3.1 corrected verbiage for logicore facts table footnote 1. 10/19/11 1.4 summary of major core version changes ? updated to v1.02.a version ? updated tools to 13.3 ? fixed cr610995 - spi slave select endianness is corrected summary of major documentation changes ? updated notice of disclaimer ? updated list of acronyms ? in core performance section, listed the late st device to earliest device: artix-7, virtex-7, kintex-7, virtex-6, and spartan-6 ? added information about ipic on page 3 ? corrected figures 14 and 15 ? updated to newest framemaker template 01/18/12 1.5 added steps to be followed when the core is configured in slave mode, page 25 .

▲Up To Search▲

Price & Availability of DS742

Part #	Manufacturer	Description	Price	BuyNow Qty.
PPDS-742-IP67 2488-PPDS-742-IP67-ND	ICP DAS USA Inc	4 PORT PROGRAMMABLE WATERPROOF /	1: USD759	30

Part #	Manufacturer	Description	Price	BuyNow Qty.
PDS-742 70682476	ICP DAS USA Inc	Serial to Ethernet Controller w/One Ethernet, Three RS-232 and One RS-485 Ports \| ICP PDS-742	1: USD438.92 10: USD416.97 25: USD395.03	0
PDS-742D 70683441	ICP DAS USA Inc	PDS-742 with Display \| ICP PDS-742D	1: USD486.73 10: USD462.39 25: USD438.06	0
PDS-742-IP67 70683442	ICP DAS USA Inc	IP67 Case of PDS-742 \| ICP PDS-742-IP67	1: USD484.74 10: USD460.51 25: USD436.27	0

Part #	Manufacturer	Description	Price	BuyNow Qty.
SCDS74-220M-N		INSTOCK		26

	To Download DS742 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .