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1 ?2016 integrated device technology, inc. may 9, 2016 general description the 8v44s269 is a ten lvds/lvttl output clock synthesizer designed for instrumentation and wir eless applications. the device generates four copies of a 1 25mhz, two copies of a 100mhz differential lvds clock and one 50mhz (lvcmos) signal with excellent phase jitter performance. the pll is optimized for a reference frequency of 25mhz. both a crystal interface and a single-ended input are supported fo r the reference frequency. three lvcmos outputs duplicate the reference frequency and are provided for clock tree cascade purpose. each of the four lvcmos outputs can be supplied with either 3.3v, 2.5v or 1.8v, forming the respective lvcmos output levels of 3.3v, 2.5v or 1.8v. the device uses idt?s third generation femtoclock ? technology for an optimum of high clock frequency and low phase noise performance, combined with a low power consumption. t he device supports a 3.3v voltage supply and is packaged in a small, lead-free (rohs 6) 48-lead vfqfn package. features ? third generation femtoclock ? technology ? 125mhz, 100mhz and 50mhz output clocks synthesized from a 25mhz reference clock or fundamental mode crystal ? six differential lvds clock outputs ? qa[0:3] outputs (125mhz) are lvds compatible ? qb[0:1] outputs (100mhz) are lvds compatible ? four single-ended lvcmos-com patible reference clock outputs ? qc output (50mhz) is lvcmos 3. 3v, 2.5v or 1.8v compatible ? qref[0:2] (25mhz) are lvcmos 3. 3v, 2.5v or 1.8v compatible ? crystal interface de signed for 25mhz xtal ? rms phase jitter @ 125mhz, using a 25mhz crystal ? (12khz - 20mhz): 0.57 (typical) ? rms phase jitter @ 100mhz, using a 25mhz crystal ? (12khz - 20mhz): 0.58 (typical) ? lvcmos interface levels for the control input ? i/o supply voltages for lvds: ? core/output ? 3.3v/2.5v ? i/o supply voltages for lvcmos: ? core/output ? 3.3v/3.3v ? 3.3v/2.5v ? 3.3v/1.8v ? lead-free (rohs 6) 48-lead vfqfn packaging ? -55c to 105c ambient operating temperature femtoclock ? crystal-to-lvds, lvcmos 10-output clock synthesizer 8v44s269 datasheet
2 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet block diagram f ref = 25 mhz 25 mhz 125 mhz 100 mhz 4 2 2 50 mhz pull-down (2) pull-down pull-down (2) noea[0:3] bypass xtal_in xtal_out ref_clk ref_sel noeb[0:1] noec noer[0:1] 1 0 pull-down (4) pull-down pull-down pull-down osc 25 mhz pfd & lpf femtoclock ? vco 2500mhz qa0 nqa0 qa1 nqa1 qa2 nqa2 qa3 nqa3 qb0 nqb0 qb1 nqb1 qc qref0 qref1 qref2 20 25 2 100 1 0
3 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet pin assignment pin description and ch aracteristic tables table 1. pin descriptions 1 number name type description 1 ref_clk input pull-down single-ended reference clock input. lvcmos/lvttl interface levels. 2 gnd power ground power supply (0v). 3v ddoc power output supply for the qc output. 4 qc output single-ended clock output. lvcmos /lvttl interface levels. 5v ddor2 power output supply for the qref2 output. 6 qref2 output single-ended clock output (copy 2 of the reference clock). ? lvcmos/lvttl interface levels. 7 gnd power ground power supply (0v). 8v ddor1 power output supply for the qref1 output. 9 qref1 output single-ended clock output (copy 1 of the reference clock). ? lvcmos/lvttl interface levels. 10 v ddor0 power output supply for the qref0 output. 11 qref0 output single-ended clock output (copy 0 of the reference clock). ? lvcmos/lvttl interface levels. 12 gnd power ground power supply (0v). qref1 gnd qref2 v ddor2 qc v ddoc gnd ref_clk qref0 v ddor0 v ddor1 gnd qa3 qa2 v ddoa nqa1 qa1 nqa0 qa0 gnd gnd nqa3 nqa2 nc noec v dd noer1 noer0 noeb1 noeb0 v ddob nqb1 qb1 nqb0 qb0 nc xtal_in xtal_out gnd bypass ref_sel noea0 noea1 noea2 noea3 v dda v dd gnd 36 35 34 33 32 31 30 28 29 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 9 8 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 8v44s269
4 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet 13 noec input pull-down output enable inputs for the individual qc output. see table 3e on page 6 for function. lvcmos/lvttl interface levels. 14 v dd power core supply. 15 noer1 input pull-down output enable inputs for the qref2 output. see table 3f on page 6 for function. lvcmos/lvttl interface levels. 16 noer0 input pull-down output enable inputs for the qref[0:1] outputs. see table 3f on page 6 for function. lvcmos/lvttl interface levels. 17 noeb1 input pull-down output enable inputs for the qb1 output. see table 3d on page 6 for function. lvcmos/lvttl interface levels. 18 noeb0 input pull-down output enable inputs for the qb0 output. see table 3d on page 6 function. lvcmos/lvttl interface levels. 19 v ddob power output supply for the bank b outputs. 20 nqb1 output inverted differential clock outpu t pair. lvds interface levels. 21 qb1 output non-inverted differential clock outp ut pair. lvds interface levels. 22 nqb0 output inverted differential clock outpu t pair. lvds interface levels. 23 qb0 output non-inverted differential clock outp ut pair. lvds interface levels. 24 nc unused no internal connection. 25 nc unused no internal connection. 26 gnd power ground power supply (0v). 27 nqa3 output inverted differential clock outpu t pair. lvds interface levels. 28 qa3 output non-inverted differential clock outp ut pair. lvds interface levels. 29 nqa2 output inverted differential clock outpu t pair. lvds interface levels. 30 qa2 output non-inverted differential clock outp ut pair. lvds interface levels. 31 v ddoa power output supply for the bank a outputs. 32 nqa1 output inverted differential clock outpu t pair. lvds interface levels. 33 qa1 output non-inverted differential clock outp ut pair. lvds interface levels. 34 nqa0 output inverted differential clock outpu t pair. lvds interface levels. 35 qa0 output non-inverted differential clock outp ut pair. lvds interface levels. 36 gnd power ground power supply (0v). 37 gnd power ground power supply (0v). 38 v dd power core supply. 39 v dda power analog power supply. 40 noea3 input pull-down output enable inputs for the qa3 output. see table 3c on page 6 for function. lvcmos/lvttl interface levels. 41 noea2 input pull-down output enable inputs for the qa2 output. see table 3c on page 6 for function. lvcmos/lvttl interface levels. table 1. pin descriptions 1 number name type description
5 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet 42 noea1 input pull-down output enable inputs for the qa1 output. see table 3c on page 6 for function. lvcmos/lvttl interface levels. 43 noea0 input pull-down output enable inputs for the qa0 output. see table 3c on page 6 for function. lvcmos/lvttl interface levels. 44 ref_sel input pull-down reference select. see table 3a on page 6 for function. ? lvcmos/lvttl interface levels. 45 bypass input pull-down pll bypass mode select. see table 3b on page 6 for function. lvcmos/lvttl interface levels. 46 gnd power ground power supply (0v). 47 xtal_out crystal output crystal output. crystal oscillator interface. 48 xtal_in crystal input crystal i nput. crystal oscillator interface. ? exposed pad ground ground power supply (0v). the exposed pad is a ground return path of the circuit and requires a connection to 0v. note 1. pull-down refers to internal input resistors. see table 2 , ?pin characteristics? . table 2. pin characteristics 1 symbol parameter test conditio ns minimum typical maximum units c in input capacitance ref_clk, noea[0:3], noeb[0:1], ? noec, noer[0:1], ref_sel, bypass 2pf r pulldown input pull-down resistor 51 k ? r out output impedance qref[0:2], qc, v ddon = 3.3v 18 ? qref[0:2], qc, v ddon = 2.5v 23 ? qref[0:2], qc, v ddon = 1.8v 35 ? note 1. v ddon denotes v ddoc, v ddor0, v ddor1, v ddor2. table 1. pin descriptions 1 number name type description
table 3a. pll reference clock select function table 1 0 (default) the ref_clk input is selected as reference clock 1 the crystal interface is selected as reference clock 6 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet function tables table 3b. pll bypass select function table 1 0 (default) pll mode 1 pll bypass mode. the reference clock is routed to th e output dividers. ac specifications do not apply in pll bypass mode. table 3c. outputs qa[0:3] enable function table 1 0 (default) output qan, nqan is enabled 1 output qan, nqan is di sab led in high-impedance state table 3d. outputs qb[0:1] enable function table 1 0 (default) outputs qbn, nqbn are enabled 1 outputs qbn, nqbn are disabled in h igh-impedance state table 3e. outputs qc enable function table 1 0 (default) output qc is enabled 1 output qc is disabled in high-impedance state table 3f. outputs qref[0:2] enable function table 1 0 (default) 0 (default) enabled enabled 0 1 enabled disabled in high-impedance state 1 0 disabled in high-impedance state enabled 1 1 disabled in high-impedance state disabled in high-impedance state note 1. ref_sel is an asynchronous control input. input operation ref_sel note 1. bypass is an asynchronous control input. input operation bypass note 1. n = 0 to 3. each qan, nqan output is i ndividually controlled by the corresponding noean input. noean are asynchronous control inputs. input operation noean note 1. n = 0 to 1. each qbn, nqbn output is i ndividually controlled by the corresponding noebn input. noebn are synchronous control inputs. input operation noebn note 1. noec is an asynchronous control input. input operation noec note 1. noer[0:1] are asynchronous control inputs. input operation noer0 noer1 outputs qref[0:1] output qref2
7 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to th e device. these ratings are stress specifications only. functional operation of the product at t hese conditions or any condition s beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating condit ions for extended periods may affect product reliability. table 4. absolute maximum ratings supply voltage, v dd 4.6v inputs, v i xtal_in other inputs 0v to 2v -0.5v to v dd + 0.5v outputs, v o (lvcmos) -0.5v to v ddon 1 + 0.5v outputs, i o (lvds) continuous current surge current 10ma 15ma storage temperature, t stg -65 q c to 150 qc junction temperature, t j 125 q c dc electrical characteristics item rating note 1. v ddon denotes v ddoc, v ddor0, v ddor1, v ddor2. table 5a. power supply dc characteristics, v dd = 3.3v5%, v ddoa = v ddob = 2.5v5%, v ddorn, 1 v ddoc = (2.5v to 3.3v) 5%, 1.8v 0.2v, t a = -55c to 105c note 1. v ddon denotes v ddor0, v ddor1, v ddor2. symbol parameter test conditio ns minimum typi cal maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.16 3.3 v dd v v ddoa, b lvds output supply voltage 2.375 2.5 2.625 v v ddor0, v ddor1, v ddor2, v ddoc lvcmos output supply voltage 2 note 2. each v ddorn (n = 0 to 2) and v ddoc voltage may be left open, connected to g nd or supplied by 1.8v, 2.5v or 3.3v. 1.6 1.8 2.0 v 2.375 2.5 2.625 v 3.135 3.3 3.465 v i dd core supply current 80 91 ma i dda analog supply current 12 16 ma i ddoa + i ddob lvds output supply current 122 137 ma i ddorn 3 + i ddoc note 3. i ddorn denotes i ddor0, i ddor1, i ddor2. lvcmos output power current qc, qref[0:2]; no external load 23ma
8 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet table 5b. lvcmos/lvttl dc characteristics, ? v dd = 3.3v5%, v ddorn , 1 v dd oc = (2.5v to 3.3v) 5%, 1.8v 0.2v, t a = -55c to 105c symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd = 3.3v 2.2 v dd + 0.3 v v il input low voltage v dd = 3.3v -0.3 0.8 v i ih input ? high current ref_sel, noea[0:3], noeb[0:1], noer[0:1], bypass, ref_clk v dd = v in = 3.465v 150 a i il input ? low current ref_sel, noea[0:3], noeb[0:1], noer[0:1], bypass, ref_clk v dd = 3.465v, v in = 0v -5 a v oh output ? high voltage 3 qc, qref[0:2] v ddon 4 = 3.465v 2.6 v v ddon 4 = 2.625v 1.8 v v ddon 4 = 2v 1.5 v v ol output ? low voltage 3 qc, qref[0:2] v ddon 4 = 3.465v 0.5 v v ddon 4 = 2.625v 0.5 v v ddon 4 = 2v 0.4 v note 1. v ddorn denotes v ddor0, v ddor1, v ddor2. note 2. noea[0:3], noeb[0:1], noer[0:1], noec, bypass and ref_ clk inputs are 3.3v tolerant. note 3. output terminated with 50 ? to v dd / 2. see section, ?parameter measurement information? . note 4. v ddon denotes v ddoc, v ddor0, v ddor1, v ddor2. table 5c. lvds dc characteristics, v dd = 3.3v5%, v ddoa = v ddob = 2.5v5%, t a = -55c to 105c symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 488 mv ? v od v od magnitude change 50 mv v os offset voltage 0.975 1.375 v ? v os v os magnitude change 50 mv table 6. crystal characteristics parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 80 ? shunt capacitance 7pf capacitive loading (c l ) 12 pf
9 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet ac electrical characteristics table 7. ac characteristics, ? v dd = 3.3v5%, v ddoa = v ddob = 2.5v5%, v ddorn, 1 v dd oc = (2.5v to 3.3v) 5%, 1.8v 0.2v, t a = -55c to 105c 2 , 3 symbol parameter test conditio ns minimum typical maximum units f vco vco frequency bypass = 0 2500 mhz f out output frequency, qa[0:3] 125 mhz output frequency, qb[0:1] 100 mhz output frequency, qc 50 mhz output frequency, qref[0:2] 25 mhz f ref reference frequency 25 mhz t jit(?) rms phase jitter (random) qa[0:3] f out = 125mhz, integration range: 12khz ? 20mhz 0.57 0.8 ps qb[0:1] f out = 100mhz, integration range: 12khz ? 20mhz 0.58 0.8 ps qc f out = 50mhz, integration range: 12khz ? 20mhz 0.78 1.20 ps qref[0:2] f out = 25mhz, integration range: 12khz ? 5mhz 0.85 1.32 ps ? n (1k) single-side band phase noise 100mhz output frequency 1khz offset from carrier -126 -119 dbc/hz ? n (10k) 10khz offset from carrier -132 -126.9 dbc/hz ? n (100k) 100khz offset from carrier -130 -127.4 dbc/hz ? n (1m) 1mhz offset from carrier -141 -138 dbc/hz ? n (10m) 10mhz offset from carrier and noise floor -153 -150 dbc/hz ? n (1k) single-side band phase noise 125mhz output frequency 1khz offset from carrier -124 -116 dbc/hz ? n (10k) 10khz offset from carrier -129 -124.9 dbc/hz ? n (100k) 100khz offset from carrier -128 -125.4 dbc/hz ? n (1m) 1mhz offset from carrier -139 -137 dbc/hz ? n (10m) 10mhz offset from carrier and noise floor -151 -150 dbc/hz t jit(per) period jitter, peak-to-peak qa[0:3] f out = 125mhz 3.0 8.1 ps qb[0:1] f out = 100mhz 3.2 7.4 ps qc f out = 50mhz, v ddoc = 3.3v 6 28 ps f out = 50mhz, v ddoc = 2.5v 7 33 ps f out = 50mhz, v ddoc = 1.8v 11 39 ps qref[0:2] f out = 25mhz 2.4 4.0 ps
10 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet t jit(cc) cycle-to-cycle jitter qa[0:3] f out = 125mhz 9 16 ps qb[0:1] f out = 100mhz 11 20 ps qc f out = 50mhz, v ddoc = 3.3v 12 27 ps f out = 50mhz, v ddoc = 2.5v 13 41 ps f out = 50mhz, v ddoc = 1.8v 44 113 ps qref[0:2] f out = 25mhz 19 33 ps tsk(b) bank skew 4, 5 qa[0:3] 25 ps qb[0:1] 30 ps qref[0:2] 65 ps t r / t f output ? rise/fall time differential outputs 20% to 80% 150 250 ps single-ended outputs 20% to 80% 375 750 ps t lock pll lock time 73 ms odc output ? duty cycle qa[0:3] f out = 125mhz 48 50 52 % qb[0:1] f out = 100mhz 48 50 52 % qc f out = 50mhz 48 50 52 % note 1. v ddorn denotes v ddor0, v ddor1, v ddor2. note 2. electrical parameters are guarant eed over the specified ambient operating te mperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device wil l meet specifications after thermal equilibrium has been reached under these conditions. note 3. f ref = 25mhz. note 4. defined as skew within a bank of outputs at the same voltage and with equal load conditions. note 5. this parameter is defined in accordance with jedec standard 65. table 7. ac characteristics, (continued) ? v dd = 3.3v5%, v ddoa = v ddob = 2.5v5%, v ddorn, 1 v dd oc = (2.5v to 3.3v) 5%, 1.8v 0.2v, t a = -55c to 105c 2 , 3 symbol parameter test conditio ns minimum typical maximum units
11 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet typical phase noise at 12 5mhz, 2.5v (qa outputs) noise power dbc ? hz offset frequency (hz)
12 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet typical phase noise at 10 0mhz, 2.5v (qb outputs) noise power dbc ? hz offset frequency (hz)
13 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet parameter measurement information lvds 3.3v core/2.5v output load ac test circuit lvcmos 3.3v core/2.5v out put load ac test circuit rms phase jitter lvcmos 3.3v core/3.3v output load ac test circuit lvcmos 3.3v core/1.8v output load ac test circuit period jitter qx nqx float gnd ++ ? power supply scope 2.5v5% 3.3v5% v dd v ddoa, v dda v ddob scope qx gnd 2.05v5% -1.25v5% 1.25v5% 2.05v5% v dda v dd v ddoc, v ddor[0:2] scope qx gnd v dd, 1.65v5% -1.65v5% v ddoc, v ddor[0:2] 1.65v5% v dda scope qx gnd 2.4v0.065v -0.9v0.1v 0.9v0.1v v dda v dd v ddoc, v ddor[0:2] 2.4v0.065v v oh v ref v ol mean period (first edge after trigger) 10,000 cycles reference point (trigger edge) histogram t jit (pk-pk)
14 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet parameter measurement information, continued lvds cycle-to-cycle jitter lvds bank skew lvds output rise/fall time lvcmos cycle-to-cycle jitter lvcmos bank skew lvcmos output rise/fall time t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles nqa[0:3], nqb[0:1] qa[0:3], qb[0:1] t sk(b) qxx qxy nqxx nqxy x = bank a or bank b 20% 80% 80% 20% t r t f v od nqa[0:3], nqb[0:1] qa[0:3], qb[0:1] ? ? ? ? v ddox 2 v ddox 2 v ddox 2 t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles qc, qref[0:2] t sk(o) v ddo 2 v ddo 2 qrefx qrefy 20% 80% 80% 20% t r t f qc, qref[0:2]
15 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet parameter measurement information, continued lvds output duty cycle/pulse width/period pll lock time differential offset voltage setup lvcmos output duty cycle/pulse width/period offset voltage setup qa[0:3], qb[0:1] nqa[0:3], nqb[0:1] t period t pw t period odc = v ddo 2 x 100% t pw qc, qref[0:2]
16 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet applications information recommendations for unused input and output pins inputs: ref_clk for applications not requiring the use of the reference clock, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the ref_clk to ground. crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additi onal protection, a 1k ? resistor can be tied from xtal_in to ground. lvcmos control pins all control pins have internal pull-down resistors; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs all unused lvcmos outputs can be left floating we recommend that there is no trace attached. lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating there should be no trace attached.
17 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver thro ugh an ac coupling capacitor. the xtal_out output can be left floati ng. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 1a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this configuration requires that the sum of the output impedance of th e driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 1b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all component s in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. th e datasheet specifications are characterized and guaranteed by us ing a quartz crystal as the input. figure 1a. figure 2a. general diagram for lvcmos driver to xtal input interface figure 1b. figure 2b. gene ral diagram for lvpecl driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
18 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet vfqfn epad thermal release path in order to maximize both the re moval of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) with in the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 2 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb pr ovides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirement s. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount asse mbly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 2. figure 3. p.c. assembly for exposed pad the rmal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
19 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical po int-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection is sues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 3a can be used with either type of output structure. figure 3b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and co nfirm if the output structure is current source or voltage source type. in addition, since these outputs are lvds compatible, th e input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. figure 3a. standard lvds termination figure 3b. optional lvds termination lvds driver z o ? z t z t lvds receiver lvds driver z o ? z t lvds receiver c z t 2 z t 2
20 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet schematic layout figure 4 (next page) shows an example 8v44s269 application schematic in which the device is operated at v dd = v ddor0 = v ddor1 = v ddor2 = 3.3v and v ddoa = v ddob = 2.5v. this example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set for the application. two different differential termi nations are depicted. qa0 is the standard lvds termination. qa3 is an example demonstrating how the idt lvds outputs can be directly ac coupled to idt clk, nclk clock receiver inputs where the intern al bias resistors of the receiver guarantee that the ac coupled lv ds clock is within the common mode range of the receiver. as with any high speed analog circui try, the power supply pins are vulnerable to random noise. to achi eve optimum jitter performance, power supply isolation is required. the 8v44s269 provides separate power supplies to isolate any high switching noise from coupling into the internal pll. the murata blm18bb221sn1b ferrite bead shown in the schematic was selected for the flat frequency response realized with the associated filter c apacitors. the rated current for this bead is 450ma which will accommodate the maximum current for each power filter. in order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 10 ohm v cca resistor and the 0.1uf capacitor in each power pin filter should be placed on the device side. the other components can be on the opposite side of the pcb. pu ll-up and pull-down resistors to set configuration pins can all be placed on the pcb side opposite the device side to free up device side area if necessary. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for a wide range of noise frequencies. this low-pass filter starts to att enuate noise at approximately 10khz. if a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk c apacitance in the local area of all devices. for additional layout recommendations and guidelines, contact clocks@idt.com .
21 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet figure 4. 8v44s269 application schematic place 0.1uf bypass cap directly adjacent to the corresponding vddo pin. lvds termination to logic input pins to logic input pins set logic input to '1' logic control input examples set logic input to '0' idt 603-25-173 crystal 25 mhz (12pf) lvds termination lvcmos termination lvcmos termination ro ro+rz=zo place 0.1uf bypass cap directly adjacent to the corresponding vddo pin. 3.3v 2.5v vdd vdd 3.3v 3.3v 2.5v 3.3v c35 0.1uf c8 10uf c21 10uf r1 33 c38 0.1uf c20 0.1uf c46 0.1u zo = 50 ohm lvcmos receiver fb4 blm18bb221sn1 1 2 c31 0.1uf q2 lvcmos driver c30 0.1uf zo = 50 ohm rd2 1k r2 100 c34 0.1uf c10 0.1uf c2 15pf r18 33 c32 0.1uf zo = 50 ohm c29 0.1uf ru2 not install rd1 not install zo = 50 ohm r16 100 zo = 50 ohm zo = 50 ohm r17 100 zo = 50 ohm c44 0.1uf c45 0.1u ru1 1k c7 0.1uf r19 rz c37 0.1uf fb5 blm18bb221sn1 1 2 idt clk/nclk receiver + - zo = 50 ohm fb3 blm18bb221sn1 1 2 c40 10uf lvds receiver + - idt8v44s269i u24 xtal_in 48 xtal_out 47 noec 13 qc 4 ref_clk 1 vddoc 3 gnd 7 epad 49 vddor2 5 qref2 6 vddor1 8 qref1 9 vddor0 10 qref0 11 gnd 12 vdd 14 noer1 15 noer0 16 noeb1 17 noeb0 18 vddob 19 nqb1 20 qb1 21 qb0 23 nqb0 22 nc 24 nc 25 gnd 26 qa3 28 nqa3 27 qa2 30 nqa2 29 vddoa 31 qa1 33 nqa1 32 nqa0 34 qa0 35 gnd 36 gnd 37 vdd 38 vdda 39 noea3 40 noea2 41 noea1 42 noea0 43 ref_sel 44 bypass 45 gnd 46 gnd 2 lvds receiver + - c39 0.1uf r20 10 fb6 blm18bb221sn1 1 2 c41 0.1uf x2 1 3 2 4 zo = 50 ohm c43 10uf c1 15pf lvcmos receiver c36 10uf c42 0.1uf fb1 blm18bb221sn1 1 2 vdd nqa0 qa0 noec ref_sel bypass xtal_out noer1 noer0 noeb noeb0 noea3 noea2 noea1 noea0 nqa3 qa3 nqa2 qa2 nqa1 qa1 nqb1 qb1 nqb0 qb0 qc qref2 qref1 qref0 ref_clk xtal_in xtal_in xtal_out vdd
22 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet power considerations the 8v44s269 device was designed and characteri zed to operate within the am bient extended temperature range of -55c to 105c. ? the ambient temperature represent s the temperature around the device, not the junc tion temperature. extreme care must be taken to avoid exceeding the 125c junction temperature, potentially damaging the device. equations and example calculations are also provided below. 1. power dissipation. the power dissipation for the 8v44s269 is the product of supply voltage and total i dd . ? the following is the power dissipation for v dd = 3.3v + 5% = 3.465v at ambient temperat ure of 105c, qrefn = 25mhz, qc = 50mhz, ? qan = 125mhz, qbn = 100mhz. ? ? i dd_max = 91ma i dda_max = 16ma i ddoa_max + i dd0b_max + i ddoc_max + i ddorn_max = 141ma ? power(core)_ max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (91ma + 16ma) = 370.76mw ? lvds and lvcmos outputs power(output)_ max = 3.465v * 141ma = 488.57mw ? total power_ max (3.465v, with all outputs switching) = 370.76mw + 488.57mw = 859.33mw 2. junction temperature. junction temperature, tj, signifies the hottest point on the de vice and exceeding the specified limit could cause device reliab ility issues. ? the maximum recommended junction temperature is 125c. for devices like this and in systems where most heat escapes from the bottom exposed pad of the package, ? jb is the primary thermal resistance of interest. the equation to calculate tj using ? jb is: tj = ? jb * p d + t b tj = junction temperature ? jb = junction-to-board thermal resistance p d = device power dissipation (example calculation is in section 1 above) t b = board temperature in order to calculate junction te mperature, the appropriate juncti on-to-board thermal resistance ? jb must be used. assuming a 2-ground plane board, the appropriate value of ? jb is 1.93c/w per table 8 below. therefore, tj for a pcb maintained at 115c with the outputs switching is: 115c + 0.859w * 1.93c/w = 116.7c which is below the limit of 125c. this calculation is only an example. tj will obviously vary dep ending on the number of loaded ou tputs, supply voltage, air flow , heat transfer method, the type of board (multi-layer) and t he actual maintained board temperature. the below table is for two ground planes. the thermal resistance will change as the number of layers in the board chan ges or if the board size change and other changes in other fact ors impacts heat dissipation in the system. table 8. thermal resistances for a 48-lead vfqfn package 1, 2, 3 meters per second 0 1 2 theta j b 1.93c/w 1.93c/w 1.93c/w theta j a 26.11c/w 22.53 c/w 21.04c/w theta j c 18.8c/w 18.8c/w 18.8c/w note 1. applicable to pcbs with two ground planes. note 2. epad size is 5.65mm x 5.65mm and connected to ground plane in pcb through 5 x5 thermal via array. note 3. in devices where most of the heat exits through the bottom epad, ? jb is commonly used for thermal calculations.
23 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet reliability information transistor count 8v44s269 transistor count: 11,242 table 9. thermal resistances for a 48 lead vfqfn package meters per second 0 1 2 theta j b 1.93c/w 1.93c/w 1.93c/w theta j a 26.11c/w 22.53c/w 21.04c/w theta j c 18.8c/w 18.8c/w 18.8c/w
24 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet 48 lead vfqfn package information
25 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet 48 lead vfqfn package information
26 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet ordering information table 10. ordering information part/order number marking packag e shipping packaging temperature 8v44s269nlgi idt8v44s269nlgi 48 lead vfqfn, lead-free tray -55c to 105c 8V44S269NLGI8 idt8v44s269nlgi 48 lead vfqfn, lead-free tape & reel -55c to 105c
27 ?2016 integrated device technology, inc. may 9, 2016 8v44s269 datasheet revision history sheet table page description of change date 1 corrected datasheet title head. 5/9/2016
disclaimer integrated device technology, inc. (idt) and its subs idiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any li cense under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfun ction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this produ ct is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices o r critical medical instruments. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2016 integrated device technology, inc. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

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