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this is information on a product in full production. june 2014 docid024395 rev 5 1/43 led1642gw 16 channels led driver with error detection current gain control and 12/16-bit pwm brightness control datasheet - production data features ? 16 constant current output channels ? output current: from 3 ma to 40 ma ? current programmable through external resistor ? 7-bit global current gain adjustment in two ranges ? 12/16-bit pwm grayscale brightness control ? programmable output turn-on/off time ? error detection mode (both open and shorted- led) ? programmable shorted-led detection thresholds ? auto power saving/auto-wakeup ? selectable sdo synchronization on the clk falling edge ? gradual output delay (selectable) ? supply voltage: 3 v to 5.5 v ? thermal shutdown and overtemperature alert ? 30 mhz 4-wires interface ? 20 v current generator rated voltage applications ? full color/monochrome large displays ? led signage description the led1642gw is a monolithic, low voltage, low current power 16-bit shift register designed for led panel displays. the led1642gw guarantees 20 v output driving capability allowing the user to connect several leds in series. in the output stage, sixteen regulated current sources provide from 3 ma to 40 ma constant current to drive the leds. the current is programmed through an external resistor and can be adjusted by 7-bit current gain register in two subranges.the brightness can be adjusted separately for each channel through a 12/16-bit grayscale control. a programmable turn-on and turn-off time (four different values are available) improves the system low noise generation performances. in the led1642gw is available the open/short error detection mode. the auto power shutdown and auto power-on feature (this feature is selectable) allow the device to save power without any external intervention. thermal management is equipped with overtemperature data alert and the output thermal shutdown (170 c). the high clock frequency is up to 30 mhz and it makes the device suitable for high data rate transmission. a selectable gradual output delay reduces the inrush current whereas the selectable sdo synchronization feature works when the device is used in daisy chain configuration. the supply voltage range is between 3 v and 5.5 v. tssop24 tssop24 (exposed pad) qsop-24 www.st.com
contents led1642gw 2/43 docid024395 rev 5 contents 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 simplified internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 equivalent circuits of inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 gain control (from cfg 0 to 5) and current ranges (cfg- 6) . . . . . . . . . 19 8.2 error detection mode (cfg-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.3 error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.4 auto-wakeup/auto power shutdown (cfg-10) . . . . . . . . . . . . . . . . . . . . . 24 8.5 programmable turn-on/turn-off time (cfg-11/12) . . . . . . . . . . . . . . . . . . 24 8.6 sdo delay (cfg-13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.7 gradual output delay (cfg-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.8 pwm counter setting and brightness register (cfg-15) . . . . . . . . . . . . . 27 9 thermal flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10 dropout voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
docid024395 rev 5 3/43 led1642gw contents 43 12 packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
list of tables led1642gw 4/43 docid024395 rev 5 list of tables table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. programmable ton/toff (output rise and fall time). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. digital key summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 9. example of current ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. gain steps for the current range selected by rext = 11 kw . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. diagnostic thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. minimum dropout voltage for some current values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13. qsop-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. qfn-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 15. tssop24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 16. tssop24 exposed pad mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 17. tssop24 and tssop24 exposed pad tape and reel mechanical data. . . . . . . . . . . . . . . 40 table 18. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 19. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
docid024395 rev 5 5/43 led1642gw list of figures 43 list of figures figure 1. tssop24, tssop24ep, qsop-24 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. qfn-24 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. typical chip-to-chip accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. timing for clock, serial in, serial out, latch enable and outputs. . . . . . . . . . . . . . . . . . . . . . 14 figure 6. led1642gw simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. input and output equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. digital keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9. channel data and write switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10. channel current vs. gain register value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. error detection action sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. error detection power-on timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13. configuration register reading sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 figure 14. configuration register reading sequence (zoom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 15. configuration register reading sequence - sdo delay actives . . . . . . . . . . . . . . . . . . . . . . 23 figure 16. configuration register reading sequence - sdo delay actives (zoom) . . . . . . . . . . . . . . . . 23 figure 17. output ton (current rise time) cfg - 12 = cfg - 11 = 0. . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 18. output toff (current fall time) cfg -12 = cfg - 11 = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 19. output ton (current rise time) cfg -12 = cfg - 11 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 20. output toff (current fall time) cfg -12 = cfg - 11 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 21. sdo delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 22. gradual output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 23. pwclk counter and comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 24. brightness register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 25. thermal flag status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 26. typical channel dropout voltage vs. output current (vdd = 3.3 v). . . . . . . . . . . . . . . . . . . 30 figure 27. qsop-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 28. qfn-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 29. tssop24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 30. tssop24 exposed pad dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 31. ssop24 and tssop24 exposed pad tape and reel dimensions . . . . . . . . . . . . . . . . . . . . 39
pin description led1642gw 6/43 docid024395 rev 5 1 pin description figure 1. tssop24, tssop24ep, qsop-24 pinout figure 2. qfn-24 pinout table 1. pin description tssop24 tssop24ep qsop-24 qfn-24 symbol name and function 1 22 gnd ground terminal 2 23 sdi serial data input terminal 3 24 clk clock input terminal 4 1 le latch input terminal 5-20 2-17 out0-out15 output terminals 21 18 pwclk clock input for pwm counter gnd sdi clk le out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 pwclk sdo r-ext vdd am13686v1 am13687v1 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 le out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out14 out15 pwclk clk sdi gnd vdd r-ext sdo
docid024395 rev 5 7/43 led1642gw absolute maximum ratings 43 2 absolute maximum ratings stressing the device above the ratings listed in the table 2 may cause the device permanent damage. operating under conditions above those indicated in the operating section is not implied. exposure to absolute maximum rating conditions for extended periods may affect the device reliability. 22 19 sdo serial data output terminal 23 20 r-ext terminal for external resistor for constant current programming 24 21 vdd supply voltage terminal table 1. pin description (continued) tssop24 tssop24ep qsop-24 qfn-24 symbol name and function table 2. absolute maximum ratings symbol parameter value unit v dd supply voltage 0 to 7 v v out output voltage -0.5 to 20 v i out output current 50 ma v i input voltage -0.4 to v dd +0.4 v i gnd gnd terminal current 1400 ma esd electrostatic discharge protection hbm human body model 2 kv
thermal characteristics led1642gw 8/43 docid024395 rev 5 3 thermal characteristics 4 electrical characteristics v dd = 3.3 v, t j = 25 c, unless otherwise specified. table 3. thermal characteristics symbol parameter value unit t a operative free-air temperature range (1) -40 to +85 c t opr operative junction temperature range -40 to +125 t stg storage ambient temperature range -55 to +150 r thj-amb thermal resistance junction-ambient qfn-24 30 c/w tssop24 85 tssop24ep (2) 37.5 qsop-24 72 1. this data must be considered in adequate power dissipation conditions, the junction temperature must be maintained below 125 c. 2. the exposed pad should be soldered directly to the pcb to get the thermal benefits. table 4. electrical characteristics symbol parameter conditions min. typ. max. unit v dd supply voltage 3 5.5 v v out output voltage out 0 - out 15 - - 19 v ih input voltage 0.7 x v dd -v dd v il gnd - 0.3 x v dd v ol serial data output voltage (sdo) v dd = 3 to 5.5 v i = +/- 1 ma --0.4 v oh v dd -0.4 - - i oleak output leakage current v out = 19 v, all outputs off - - 0.5 a v uvlo uvlo threshold (rising) 2.7 2.9 v uvlo threshold (falling) 2.2 2.3 hy uvlo uvlo hysteresis 400 mv
docid024395 rev 5 9/43 led1642gw electrical characteristics 43 ? i ol1 output current precision channel-to-channel (all outputs on) (1)(2) v out = 0.1 v; (i out = 3 ma) r ext = 11 k ? cfg-0?cfg-5= ?000000? cfg-6 = ?0? --4 % ? i ol2 v out = 0.5 v; (i out = 20 ma) r ext = 11 k ? cfg-0?cfg-5 = ?011010? cfg-6 = ?1? --3 ? i ol3 v out = 0.8 v; (i out = 36 ma) r ext = 11 k ? cfg-0?cfg-5 = ?111111? cfg-6 = ?1? --3 ? i o l2a output current precision device-to-device (all outputs on) (1) v out = 0.5 v; (i out = 20 ma) r ext =1 1 k ? cfg-0?cfg-5 = ?011010? cfg-6 = ?1? --6% %/dv out output current vs. output voltage regulation (3) v out from 1 v to 3 v; (i out = 36 ma) r ext = 11 k ? cfg-0?cfg-5 = ?111111? cfg-6 = ?1? -0.1- %/v %/dv dd output current vs. supply voltage regulation (4) v dd from 3 v to 5.5 v v out = 0.8 v; (i out = 36 ma) r ext = 11 k ? cfg-0?cfg-5 = ?111111? cfg-6 = ?1? -1- rup pull-up resistor for pwclk pin 400 500 600 k ? rdw pull-down resistor for le pin 400 500 600 r ext external current setup resistance 100 i dd (off1) supply current (off) r ext = 11 k ? out 0 to 15 = off cfg = default --6 ma i dd (on1) supply current (on) r ext = 11 k ? ; i out = 20 ma out 0 to 15 = on cfg-0?cfg-5 = ?011010? cfg-6 = ?1? -8 i dd (on2) r ext = 11 k ? ; i out = 36 ma out 0 to 15 = on cfg-0?cfg-5 = ?111111? cfg-6 = ?1? -10 table 4. electrical characteristics (continued) symbol parameter conditions min. typ. max. unit
electrical characteristics led1642gw 10/43 docid024395 rev 5 i dd (auto off) supply current (auto off) r ext = 11 k ? ; out 0 to 15 = off cfg-0?cfg-5 = ?111111? cfg-6 = ?1? - 200 500 a t flg thermal flag 150 c t sd thermal shutdown (5) 170 t sd-hy thermal shutdown hysteresis (5) 15 20 1. tested with just one output loaded. 2. ((ioutn - ioutavg1-15)/ ioutavg1-15) x 100. 3. 4. 5. not tested, guaranteed by design. table 4. electrical characteristics (continued) symbol parameter conditions min. typ. max. unit 1 3 100 ) v 0 . 1 voutn @ ioutn ( ) v 0 . 1 voutn @ ioutn ( ) v 0 . 3 voutn @ ioutn ( ) v / (% ? = = ? = = 3 5 . 5 100 ) v 0 . 3 vdd @ ioutn ( ) v 0 . 3 vdd @ ioutn ( ) v 5 . 5 vdd @ ioutn ( ) v / (% ? = = ? = =
docid024395 rev 5 11/43 led1642gw electrical characteristics 43 figure 3. typical chip-to-chip accuracy figure 4. typical application schematic am13688v1 0 0.5 1 1.5 2 2.5 3 3.5 4 0 5 10 15 20 25 30 35 40 chip-to-chip (%) i out (ma) v dd =3.3/5 v; t=25 c am13689v1 led1642gw supply voltage sdi clk le pwclk vdd out0 out1 out15 r-ext current setting resistor data loaded through serial interface led common rail voltage ?.. sdo data output + cin cled gnd
switching characteristics led1642gw 12/43 docid024395 rev 5 5 switching characteristics v dd = 3.3 v, t j = 25 c, unless otherwise specified. table 5. switching characteristics (1) symbol parameter conditions min. typ. max. unit f clk clock frequency cascade operation - - 30 mhz f pwclk pwclock frequency - - 30 tr (sdo) sdo rise time r ext = 11 k ? ; i out = 20 ma v out = 0.8 v vih = v dd ; vil = gnd rl = 3.3 k ? ; cl = 10 pf cfg-0?cfg-5 = ?011010? cfg-6 = ?1? -5 - ns tf (sdo) sdo fall time - 5 - tplhle le - outn (2) propagation delay time (?l to ?h?) r ext = 11 k ? ; i out = 20 ma v out = 0.8 v vih = v dd ; vil = gnd rl = 5 0 ? ; cl = 10 pf cfg-0?cfg-5 = ?011010? cfg-6 = ?1? -200 - tplh clk - sdo cfg-13 = ?0? 81525 tphlle le - outn (2) propagation delay time (?h? to ?l?) -100 - tphl clk - sdo cfg-13 = ?0? 81525 tw(clk) clk pulse width 20 - - t w (pwclk) pwclk 20 - - tw(l) le 20 - - t gr-d gradual delay ch-to-ch 10 t su(l) setup time for le 5 - - t h(l) hold time for le 5 - - t su(d) setup time for sdi 5 - - t h(d) hold time for sdi 10 - - tclkr (3) maximum clk rise time - - 5 s tclkf (3) maximum clk fall time - - 5 i out-ov output current turn-on overshoot v out = 0.6 to 3 v cl = 10 pf; i out = 3 to 36 ma --10% t n-err normal error detection minimum output on time --1s
docid024395 rev 5 13/43 led1642gw switching characteristics 43 t shutdown auto power shutdown time (auto off) from le falling edge to r ext voltage reference at -10% -100 - ns t wakeup auto-wakeup from le falling edge to r ext voltage reference at 90% -3 -s 1. not tested in production. all ta ble limits are guaranteed by design. 2. cfg -11= 0 and cfg -12 = 0 (output tr = 30 ns; output tf = 20 ns); cfg-14=1 (no output gradual delay). 3. if devices are connected in cascade and tclk r or tclkf is large, it may be critic al to achieve the timing required for data transfer between two cascaded devices. table 5. switching characteristics (1) symbol parameter conditions min. typ. max. unit table 6. programmable t on /t off (output rise and fall time) configuration bits (cfg-12 - cfg-11) conditions typ . (20% to 80%) unit turn-on turn-off 0 - 0 r ext = 11 k ? ; i out = 20 ma v out = 0.8 v vih= v dd ; vil= gnd rl = 5 0 ? ; cl=10pf cfg-0...cfg-5=?011010? cfg-6 = ?1? 30 ns 20 ns ns 0 - 1 100 ns 40 ns 1 - 0 140 ns 80 ns 1 - 1 180 ns 150 ns
switching characteristics led1642gw 14/43 docid024395 rev 5 figure 5. timing for clock, serial in, serial out, latch enable and outputs the correct sampling of the data depends on the stability of the data at sdi on the rising edge of the clock signal and it is assured by a proper data setup and hold time (t su(d) and t h(d) ), as shown in figure 5 . the same figure shows the propagation delay from clk to sdo (t plh /t phl ). figure 5 describes also the minimum duration of clk, le pulses (t w(clk) ) and t w(l) respectively and the propagation delay from le to out n (t plhle and t phlle ) in the hypothesis that all channels have already been enabled by pwm counter. t plhle ,t phlle am13690v1
docid024395 rev 5 15/43 led1642gw simplified internal block diagram 43 6 simplified internal block diagram figure 6. led1642gw simplified block diagram 6.1 equivalent circuits of inputs and outputs le and pwclk input terminals have pull-down and pull-up connection respectively. clk and sdi must be connected to the external circuit to fix the logic level. figure 7. input and output equivalent circuits am13691v1 uvlo & por configuration register channel driver timing control turn on/off gradual delay ???? current gain adjustment sdi clk le v dd gnd r-ext sdo out0 out1 out2 out14 out15 16 output channels pwm counter pwclk thermal shutdown current ref. control logic & data registers error detection am13692v1 pwclk terminal le terminal clk, sdi terminal sdo terminal
digital blocks led1642gw 16/43 docid024395 rev 5 7 digital blocks the data input arrives through the serial interface at each clk rising edge. the le signal is used to latch the loaded data and also to address data loading to the appropriate register, thermal flag reading and error detection. the access to the different registers or functions of the device (configuration register, brightness register or current gain, error detection, etc.) is achieved by using different digital keys, defined as a number of clk pulses during which the le signal is asserted. the available digital keys are listed in table 7 and figure 8 . a typical channel data input is shown in figure 9 . table 7. digital key summary number # clk rising edge when the le is ?1? command description 1 1 ? 2 write switch (to turn on/off output channels) 2 3 ? 4 brightness data latch 3 5 ? 6 brightness global latch 4 7 write configuration register 5 8 read configuration register 6 9 start open error detection mode 7 10 start short error detection mode 8 11 start combined error detection mode 9 12 end error detection mode 10 13 thermal error reading 11 14 reserved 12 15 reserved
docid024395 rev 5 17/43 led1642gw digital blocks 43 figure 8. digital keys figure 9. channel data and write switch am13693v1 clk le le le le le le le le le write switch data latch global latch write cr read cr start open error detection start short error detection start combined detection end error detection le thermal error reading am13694v1 0e 0f 0c 0a 0b 0d 09 08 07 06 05 04 03 02 01 00 clk sdi le 16-bit data
configuration register led1642gw 18/43 docid024395 rev 5 8 configuration register the configuration register is used to enable or disable some device features, to program some parameters and to change other settings. the access to this register (read or write) is managed to find a description for each bit as described in table 8 . the default value of the configuration register (when the device is switched on or after a reset) is "0" for all bits. to change anything in the configuration register, a 16-bit digital word must be sent (cfg - 0 represents lsb, cfg -15 the msb). table 8. configuration register bit definition r/w description default cfg-0 current gain adjustment r/w 6-bit dac allows adjusting the device output current in 64 steps for each range (defined by cfg-6) 0 cfg-1 0 cfg-2 0 cfg-3 0 cfg-4 0 cfg-5 0 cfg-6 current range r/w ?0? low current range ?1? high current range 0 cfg-7 error detection mode r/w ?0? normal mode ?1? reserved mode 0 cfg-8 shorted-led detection thresholds r/w programmable output shorted-led detection thresholds cfg-9 cfg-8 th. volt. 0 00 1.8 v 01 2.5 v cfg-9 r/w 10 3 v 0 11 3.5 v cfg-10 auto off shutdown r/w ?0? device always on ?1? auto power shutdown active (auto off) 0 cfg-11 output turn- on/off time r/w programmable output rise and fall time (20% to 80%) cfg-12 cfg-11 turn-on turn-off 0 0 0 30 ns 20 ns 0 1 100 ns 40 ns cfg-12 r/w 1 0 140 ns 80 ns 0 1 1 180 ns 150 ns cfg-13 sdo delay r/w if ?0? no delay is present on sdo if ?1? the data are shifted out and they are synchronized with the falling edge of the clk signal 0
docid024395 rev 5 19/43 led1642gw configuration register 43 8.1 gain control (from cfg 0 to 5) and current ranges (cfg- 6) the led current can be programmed using an external resistor connected to gnd from r ext pin and can be fixed using the dedicated bits of the configuration register (from cfg - 0 to cfg - 5 bits define the gain, while cfg - 6 bit defines the current range within the which the gain can be adjusted). the device can regulate the current up to 36 ma and down to 0.5 ma. the accuracy of the led current depends on the selected range and it is guaranteed in the ranges indicated in the static electrical characteristics only (see tab le 3 and 9 ). when the device is switched on, the selected current range and the resistor connected to the r ext pin fix the default led current: where v ref = 1.23 v is the voltage of the r ext pin and k is the mirroring current ratio, whose value depends on the selected current range: ? k = 28 with low current range selected (cfg - 6 = "0") ? k = 80 with high current range selected (cfg - 6 = "1") the relation between the programmed current and the current gain settings is the following: where g is the current gain value (decimal value) defined by the dedicated bits of the current gain register. the current gain is managed by 6-bits of the configuration register (cfg - 0 to cfg - 5, cfg - 0 is lsb and cfg - 5 is msb) and can be adjusted within two ranges (selectable through the bit cfg - 6) over 64 steps. the width of each step depends on the default current (i ol_default ) as well as the selected r ext . finally, each step is as follows: cfg-14 gradual output delay r/w ?0? a progressive delay is applied to output (10 ns per channel) ?1? no delay is applied to output 0 cfg-15 12/16 pwm counter r/w ?0? to select 16-bit brightness register (65536 grayscale rightness steps). ?1? to select 12-bit brightness register (4096 grayscale brightness steps) 0 table 8. configuration register (continued) bit definition r/w description default k r v i ext ref default ol ? = _ ) ( _ step default ol ol i g i i ? + =
configuration register led1642gw 20/43 docid024395 rev 5 the ta ble 9 shows an example of the current setting with an external resistance (r ext ) = 11 k ? : the tab le 10 shows an example of current setting and gain control with r ext = 11 k ? , see also figure 10 . the external programming resistance must be connected as close as possible to the related device pins (r ext and gnd) to reduce as minimum as possible the routing length and prevent reference noise injection and electromagnetic interferences. moreover, a direct connection to the device gnd pin reduces the possible output current variation when the total device ground current changes (load effect). table 9. example of current ranges r ext [k ? ] cfg-6 cfg-0 to cfg-5 led current (1) [ma] 1. the indicated values may be slightly different on the current device. accuracy low range 11 0 000000 3.1 ma 4% ch-to-ch 11 0 111111 12.5 ma - high range 11 1 000000 8.9 ma 11 1 011010 20 ma 3% ch-to-ch table 10. gain steps for the current range selected by r ext = 11 k cfg-6 cfg(0 to 5) led current (1) [ma] 1. the indicated values may be slightly different on the current device. low range 0 000000 3.131 0 000001 3.280 ??? 0 111111 12.524 high range 1 000000 8.945 1 000001 9.371 ??? 1 111111 35.78 21 _ default ol step i i =
docid024395 rev 5 21/43 led1642gw configuration register 43 figure 10. channel current vs. gain register value 8.2 error detection mode (cfg-7) stopping the normal activity of the display and turning on all driver channels allows the error detection to be performed and failed led or display defects to be checked. the error detection is active when the cfg -7 bit of the configuration register is "0". the diagnostics is performed as shown in figure 11 : ? the led has to be selected turning on the relative channel on the switch register (powering on or off the output channels); the brightness register value for this channel cannot be zero. ? the normal error detection has to be selected in the configuration register (cfg-7= "0"). the appropriate digital key to choose the type of detection (open, short or combined) must be sent (see table 7 ). ? after the error detection starts, the channel under testing has to be turned on at least 1 s (the led is at the nominal current). please note that, the output power-on depends on pwclk signal and in several applications this signal is not synchronized with the serial interface clock (clk pin). therefore, to be sure that, between the detection start and the detection end, the output power-on is 1 s and moreover, that last power-on, in the interval, starts at least 0.5 s before the detection end pattern (see figure 12 ), it is suggested that the error detection should be performed just after the device startup (brightness counter reset) with all channels on, before applying pwclk signal. ? the result of the detection ("0" indicates a fault condition) is shifted out sdo, in 16 clock pulses after the "detection end command" is provided, first output bit represents channel 15 (error data can be read in a way similar to configuration register data reading as shown on figure 13 , 14 , 15 and 16 ). please note that (with sdo delay off) output 15 detection result will be available just after 1st clock pulse rising edge, so it can be sampled on the rising edge of second clock pulse. in the same way output 0 detection result will be available just after 16th clock pulse rising edge, so it can be sampled on the rising edge of 17th clk pulse. am13695v1 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 11 k r=0 11 k r=1 18 k r=0 i out o u t v s . g a i n (r = range selection, r ext = 11 k or 18 k ) gain register decimal value i out o u t (ma) ( m a ) 18 k r=1
configuration register led1642gw 22/43 docid024395 rev 5 figure 11. error detection action sequence figure 12. error detection power-on timing am13696v1 normal detection sequence read error detection result on sdo in 16 clock pulses after detection end command turn on led by pwclk pulses for at least 1 s send open, short or combined error detection start command by le digital keys select led to be turned on and checked in switch register data; brightness for selected channels cannot be zero. select normal error detection mode on cfg register (bit 7 = ?0?) send error detection end command by le digital key am13697v1 0.5us det. end det. start it must contain 1us output power on 1us spi pattern output current x0000 < brt < xffff
docid024395 rev 5 23/43 led1642gw configuration register 43 figure 13. configuration register reading sequence figure 14. configuration register reading sequence (zoom) cfg reg programming cfg reg reading command cfg reg data c1=clk c2=sdi c3=le c4=sdo first clk pulse after cfg reg reading command cfg reg data c1=clk c2=sdi c3=le c4=sdo first clk pulse after cfg reg reading command figure 15. configuration register reading sequence - sdo delay actives figure 16. configuration register reading sequence - sdo delay actives (zoom) cfg reg programming cfg reg reading command cfg reg data c1=clk c2=sdi c3=le c4=sdo first clk pulse after cfg reg reading command sync. change cfg13=1 c1=clk c2=sdi c3=le c4=sdo cfg reg data first clk pulse after cfg reg reading command
configuration register led1642gw 24/43 docid024395 rev 5 8.3 error detection conditions during the error detection phases for each channel, the following checks have to be performed: ? the output current in open detection mode (digital key: 9 clk rising edges when le is "1") ? the output voltage in short detection (digital key: 10 clk rising edges when le is "1") ? both parameters (output voltage and current) in combined error detection mode (digital key: 11 clk rising edges when le is "1"). the thresholds for the error diagnostics are listed in table 11 : 8.4 auto-wakeup/auto power shutdown (cfg-10) this feature reduces the power consumption when all outputs are off. it is active when the cfg -10 bit of configuration register is "1". the auto power shutdown (auto off) starts when the data latched is "0" for all channels, and device is active again (wakeup) at the first latched data string including at least one bit = "1" (at least one channel on). timings for shutdown and wakeup are present in the dynamics feature table. while the auto power shutdown is active, the device ignores any other command except the channel power-on. 8.5 programmable turn-on/turn-off time (cfg-11/12) the device gives the possibility to program the turn-on and turn-off time of the current generators. four different values can be selected using cfg -12 and cfg-11 bits of the configuration register (see tab le 8 ) to fit the application requirements: 30/20 ns (00), 100/40 ns (01), 140/80 ns (10) and 180/150 ns (11). the selected value refers to t on (current rise time) and t off (current fall time). table 11. diagnostic thresholds error detection modes checked malfunction cfg-9 cfg-8 thresholds (v) min. typ. max. open detection combined mode open line or output short to gnd xx- i out 0.5 x i out programmed - short detection short on led or short to v-led 001.15v out 1.8 2.05 012.25v out 2.5 2.75 102.75v out 3.0 3.25 113.25v out 3.5 3.80
docid024395 rev 5 25/43 led1642gw configuration register 43 8.6 sdo delay (cfg-13) usually in sdo terminal, data are shifted out the rising edge of clk signal (with a propagation delay of about 15 ns - signal (a) in figure 21 ). the device has the possibility to shift data out the falling edge of the clk signal (with few ns of propagation delay - signal (b) in figure 21 ). this feature is active when cfg -13 bit of the configuration register is "1". default setting for this bit is "0" hence the sdo delay is not activated by default. this feature is particularly useful when some devices are connected in daisy chain configuration with mismatched propagation delays, between clk and sdo data path (board routing). figure 17. output t on (current rise time) cfg - 12 = cfg - 11 = 0 figure 18. output t off (current fall time) cfg - 2 = cfg - 11 = 0 am13698v1 am13699v1 figure 19. output t on (current rise time) cfg - 12 = cfg - 11 = 1 figure 20. output t off (current fall time) cfg - 12 = cfg - 11 = 1 am13700v1 am13701v1
configuration register led1642gw 26/43 docid024395 rev 5 figure 21. sdo delay 8.7 gradual output delay (cfg-14) the gradual output delay consists of turning on gradually the current generators avoiding to turn on all channels at the same time. when pwm counter enables the device channels, the outputs can be turned on simultaneously or with a progressive delay. thanks to configuration register cfg -14 bit, the user can decide to put a delay among outputs (10 ns from each channel to the next one, around 150 ns between first and last channel). the typical output timing is shown in figure 22 . this feature prevents the inrush current and reduces the bypass capacitor value. am13702v1 (a) (b) (a) data shifted out of the sdo with the device propagation delay (b) data shifted out of the sdo by the falling edge of the clk
docid024395 rev 5 27/43 led1642gw configuration register 43 figure 22. gradual output delay 8.8 pwm counter setting and brightness register (cfg-15) the brightness of each channel can be adjusted through a 12/16-bit pwm grayscale brightness control according to the pwm counter selection (configuration register cfg -15 bit). brightness data is loaded by the sdi pin in a 16-bit shift register. once 16-bit has been loaded (first input bit of brightness word is msb, 16 th bit is lsb), the digital word is moved to the corresponding temporary buffer (first word is the brightness of channel 15, the last one is for channel 0) using the appropriate key shown in ta ble 7 ("data latch"). one "data latch" key must follow each 16-bit brightness word except the last one. when the last brightness word is loaded (channel 0 brightness data), the key indicated as "global latch" in table 7 must be used. this action moves the word from the shift register to the temporary buffer through the out0 and, at the same time, transfers all data of the 16 temporary buffers (16 x16-bit string) to the corresponding brightness registers (see also figure 28 ). the pwm signals are generated by comparing the content of the brightness registers to a 16-bit or 12-bit counter, according to the cfg-15 bit status. the counter's clock source is provided to the pwclk pin. in case of selection of 12-bit pwm counter, the four most significant bits of each brightness data word are ignored. however, each of sixteen brightness data words must be 16-bit long.the brightness register default value is "0", unless this value is changed, the led brightness is minimum. figure 27 shows this function in the schematic. pwclk must be a square wave signal, duty cycle is not important but the minimum width has to be above 20 ns, max. frequency has to be 30 mhz (pay attention the minimum output on time). just after the device startup (brightness counter reset), before applying pwclk signal, all channels are in power-on condition if the brightness register values are not zeroed. am13703v1
configuration register led1642gw 28/43 docid024395 rev 5 figure 23. pwclk counter and comparator figure 24. brightness register setting am13704v1 am13705v1 0e 0f 0c 0a 0b 0d 09 08 07 06 05 04 03 02 01 00 brt14 brt13 brt15 brt01 brt02 brt03 256-bit brightness data stream clk sdi le 16-bit data word data latch clk sdi le global latch 0e 0f 0c 0a 0b 0d 09 08 07 06 05 04 03 02 01 00 brt00 msb lsb
docid024395 rev 5 29/43 led1642gw thermal flag 43 9 thermal flag the device has a thermal control logic providing a flag status when the internal temperature exceeds 150 c (if temperature increases over 170 c a thermal shutdown protects the device). this status can be read running the digital key "thermal error reading", holding the le high for 13 clk rising edges (see figure 25 ). if thermal alert is asserted, a 16-bit string = "1" is sent by sdo. the error data is uploaded into edr register and this error notification is ready to be streamed through sdo to next 16 clk rising edges. hence, thermal flag status can be: figure 25. thermal flag status device temperature sdo under 150 c ?0000 0000 0000 0000? over 150 c ?1111 1111 1111 1111? thermal flag status previous data 13 clock pulses with le asserted am13706v1
dropout voltage led1642gw 30/43 docid024395 rev 5 10 dropout voltage in order to correctly regulate the channel current, a minimum output voltage (v drop ) across each current generator must be guaranteed. the figure 26 and ta ble 12 show the minimum v drop related to the regulated current; these measurements have been recorded with just one output on. when more than one output is active the drop voltage increases. at 36 ma per channel, the minimum output voltage must be increased about 200 mv. a v drop , lower than the minimum recommended, implies the regulation of a current lower than the expected one. however an excess of v drop increases the power dissipation. figure 26. typical channel dropout voltage vs. output current (v dd = 3.3 v) table 12. minimum dropout voltage for some current values output current [ma] minimum v drop @ v dd = 3.3 v [mv] 370 9180 12 250 20 410 36 730 40 820 45 955 50 1070 am13707v1 0 200 400 600 800 1000 1200 0 5 10 15 20 25 30 35 40 45 50 55 v drop [mv] i out [ma] drop vs. i out @ v dd = 3.3 v, t= 25 c (only one channel on)
docid024395 rev 5 31/43 led1642gw package mechanical data 43 11 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package mechanical data led1642gw 32/43 docid024395 rev 5 figure 27. qsop-24 package dimensions
docid024395 rev 5 33/43 led1642gw package mechanical data 43 table 13. qsop-24 mechanical data dim. mm min. typ. max. a 1.54 1.62 1.73 a1 0.1 0.15 0.25 a2 1.47 b 0.31 0.2 c 0.254 0.17 d 8.56 8.66 8.76 e 5.8 6 6.2 e1 3.8 3.91 4.01 e 0.635 l 0.4 0.635 0.89 h 0.25 0.33 0.41 < 8 0
package mechanical data led1642gw 34/43 docid024395 rev 5 figure 28. qfn-24 package dimensions
docid024395 rev 5 35/43 led1642gw package mechanical data 43 table 14. qfn-24 mechanical data dim. mm min. typ. max. a 0.80 0.90 1.00 a1 0 0.02 0.05 a3 0.20 b 0.18 0.25 0.30 d 3.85 4.00 4.15 d2 2.00 2.15 2.25 e 3.85 4.00 4.15 e2 2.00 2.15 2.25 e0.50 l 0.30 0.40 0.50
package mechanical data led1642gw 36/43 docid024395 rev 5 figure 29. tssop24 package dimensions table 15. tssop24 mechanical data dim. mm min. typ. max. a 1.1 a1 0.05 0.15 a2 0.9 b 0.19 0.30 c 0.09 0.20 d 7.7 7.9 e 4.3 4.5 e 0.65 bsc h 6.25 6.5 k 0 8 l 0.50 0.70
docid024395 rev 5 37/43 led1642gw package mechanical data 43 figure 30. tssop24 exposed pad dimensions 7100778_d
package mechanical data led1642gw 38/43 docid024395 rev 5 table 16. tssop24 exposed pad mechanical data dim. mm min. typ. max. a 1.20 a1 0.15 a2 0.80 1.00 1.05 b0.19 0.30 c0.09 0.20 d 7.70 7.80 7.90 d1 4.80 5.00 5.20 e 6.20 6.40 6.60 e1 4.30 4.40 4.50 e2 3.00 3.20 3.40 e0.65 l 0.45 0.60 0.75 l1 1.00 k0 8 aaa 0.10
docid024395 rev 5 39/43 led1642gw packaging mechanical data 43 12 packaging mechanical data figure 31. ssop24 and tssop24 exposed pad tape and reel dimensions
packaging mechanical data led1642gw 40/43 docid024395 rev 5 table 17. tssop24 and tssop24 exposed pad tape and reel mechanical data dim. mm min. typ. max. a - 330 c 12.8 - 13.2 d 20.2 - n 60 - t - 22.4 ao 6.8 - 7 bo 8.2 - 8.4 ko 1.7 - 1.9 po 3.9 - 4.1 p 11.9 - 12.1
docid024395 rev 5 41/43 led1642gw ordering information 43 13 ordering information table 18. ordering information order code package packaging led1642gwptr qsop-24 2500 parts per reel led1642gwqtr qfn-24 4000 parts per reel LED1642GWTTR tssop24 2500 parts per reel led1642gwxttr tssop24 exposed pad 2500 parts per reel
revision history led1642gw 42/43 docid024395 rev 5 14 revision history table 19. document revision history date revision changes 03-may-2013 1 initial release. 06-jun-2013 2 updated table 2: absolute maximum ratings , figure 10: channel current vs. gain register value and section 8.2: error detection mode (cfg-7) . added figure 13 , 14 , 15 and 16 . minor text changes. 19-aug-2013 3 updated the title, the features and the description. modified table 4: electrical characteristics , updated table 9: example of current ranges , table 10: gain steps for the current range selected by rext = 11 kw , section 8.2: error detection mode (cfg-7) , section 8.8: pwm counter setting and brightness register (cfg-15) . 18-mar-2014 4 added footnote 1 in table 5: switching characteristics and footnote 5 in table 4: electrical characteristics . 16-jun-2014 5 updated table 16: tssop24 exposed pad mechanical data . minor text changes.
docid024395 rev 5 43/43 led1642gw 43 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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