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november 2016 docid028929 rev 2 1 / 14 this is information on a product in full production. www.st.com STW40N90K5, stwa40n90k5 n - channel 900 v, 0.088 ? typ., 40 a mdmesh? k5 power mosfets in to - 247 and to - 247 long leads packages datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max i d STW40N90K5 900 v 0.099 40 a stwa40n90k5 ? industrys lowest r ds(on) x area ? industrys best fom (figure of merit) ? ultra - low gate charge ? 100% avalanche tested ? zener - protected applications ? switching applications description these very high voltage n - channel power mosfets are designed using mdmesh? k5 technology based on an innovative proprietary vertical structure. the result is a dramatic reduction in on - resistance and ultra - low gate charge for applications requiring superio r power density and high efficiency. table 1: device summary order code marking package packaging STW40N90K5 40n90k5 to - 247 tube stwa40n90k5 to - 247 long leads
contents STW40N90K5, stwa40n90k5 2 / 14 docid028929 rev 2 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 2.1 electrical characteri stics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 8 4 package mechanical data ................................ ............................... 9 4.1 to - 247 package information ................................ ............................. 9 4.2 to - 247 long leads p ackage information ................................ ......... 11 5 revision history ................................ ................................ ............ 13
STW40N90K5, stwa40n90k5 electrical ratings docid028929 rev 2 3 / 14 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 30 v i d drain current (continuous) at t c = 25 c 40 a i d drain current (continuous) at t c = 100 c 25 a i d (1) drain current (pulsed) 160 a p tot total dissipation at t c = 25 c 446 w dv/dt (2) peak diode recovery voltage slope 4.5 v/ns dv/dt (3) mosfet dv/dt ruggedness 50 v/ns t j operating junction temperature range - 55 to 150 c t stg storage temperature range notes: (1) pulse width limited by safe operating area (2) i sd 40 a, di/dt 100 a/s, v ds(peak) v (br)dss. , v dd =450 v (3) v ds 720 v table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case max 0.28 c/w r thj - amb thermal resistance junction - amb 50 c/w table 4: avalanche characteristics symbol parameter value unit i ar avalanche current, repetitive or not repetitive (pulse width limited by t jmax ) 13.5 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 750 mj
electrical characteristics STW40N90K5, stwa40n90k5 4 / 14 docid028929 rev 2 2 electrical characteristics (t case =25 c unless otherwise specified) table 5: on /off states symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 1 ma 900 v i dss zero gate voltage drain current v gs = 0 v, v ds = 900 v 1 a v gs = 0 v, v ds = 900 v, t c =125 c (1) 50 a i gss gate - body leakage current v ds =0 v, v gs = 20 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 100 a 3 4 5 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 20 a 0.088 0.099 notes: (1) defined by design, not subject to production test. table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v gs =0 v, v ds =100 v, f=1 mhz - 3263 - pf c oss output capacitance - 212 - pf c rss reverse transfer capacitance - 1.3 - pf c o(tr) (1) equivalent capacitance time related v gs = 0 v, v ds = 0 v to 720 v - 429 - pf c o(er) (2) equivalent capacitance energy related - 159 - pf r g intrinsic gate resistance f = 1 mhz, i d =0 a - 1.9 - q g total gate charge v dd = 720 v, i d = 40 a v gs =10 v (see figure 15: "test circuit for gate charge behavior" ) - 89 - nc q gs gate - source charge - 25 - nc q gd gate - drain charge - 37.5 - nc notes: (1) time related is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss (2) energy related is defined as a constant equivalent capacitance giving the same stored energy as c oss when v ds increases from 0 to 80% v dss
STW40N90K5, stwa40n90k5 electrical characteristics docid028929 rev 2 5 / 14 table 7: switching times symbol parameter test conditions min. typ. max unit t d(on) turn - on delay time v dd = 450 v, i d = 40 a, r g = 4.7 , v gs = 10 v (see figure 14: "test circuit for resistive load switching times" ) - 30.4 - ns t r rise time - 15.5 - ns t d(off) turn - off - delay time - 84.5 - ns t f fall time - 13.4 - ns table 8: source drain diode symbol parameter test conditions min. typ. max unit i sd source - drain current - 40 a i sdm (1) source - drain current (pulsed) - 160 a v sd (2) forward on voltage i sd = 40 a, v gs = 0 v - 1.5 v t rr reverse recovery time i sd = 40 a, di/dt = 100 a/s v dd = 60 v (see figure 17: "unclamped inductive load test circuit" ) - 693 ns q rr reverse recovery charge - 22 c i rrm reverse recovery current - 63 a t rr reverse recovery time i sd = 40 a, di/dt = 100 a/s v dd = 60 v, t j = 150 c (see figure 17: "unclamped inductive load test circuit" ) - 884 ns q rr reverse recovery charge - 29 c i rrm reverse recovery current - 65.5 a notes: (1) pulse width limited by safe operating area. (2) pulsed: pulse duration = 300 s, duty cycle 1.5% table 9: gate - source zener diode symbol parameter test conditions min typ. max. unit v (br)gso gate - source breakdown voltage i gs = 1ma, i d =0 a 30 - - v the built - in back - to - back zener diodes are specifically designed to enhance the esd performance of the device. the zener voltage facilitates efficient and cost - effective device integrity protection, thus eliminating the need for additional external componentry.
electrical characteristics STW40N90K5, stwa40n90k5 6 / 14 docid028929 rev 2 2.1 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfe r characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance d d t
STW40N90K5, stwa40n90k5 electrical characteristics docid028929 rev 2 7 / 14 figure 8 : capacitance variations figure 9 : normalized gate threshold voltage vs temperature figure 10 : normalized on - resistance vs temperature figure 11 : normalized v(br)dss vs temperature figure 12 : source - drain diode forward characteristics figure 13 : maximum avalanche energy vs starting tj
test circuits STW40N90K5, stwa40n90k5 8 / 14 docid028929 rev 2 3 test circuits figure 14 : test circuit for resistive load switching times figure 15 : test circuit for gate charge behavior figure 16 : test circuit for inductive load switching and diode recovery times figure 17 : unclamped inductive load test circuit figure 18 : unclamped inductive waveform figure 19 : switchi ng time waveform am01469v10 47 k 2.7 k 1 k i g = cons t 100 d.u. t . + pulse width v gs 2200 f v g v dd r l
STW40N90K5, stwa40n90k5 package mechanical data docid028929 rev 2 9 / 14 4 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their leve l of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.1 to - 247 package information figure 20 : to - 247 package outline
package mechanical data STW40N90K5, stwa40n90k5 10 / 14 docid028929 rev 2 table 10: to - 247 package mechanical data dim. mm min. typ. max. a 4.85 5.15 a1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 d 19.85 20.15 e 15.45 15.75 e 5.30 5.45 5.60 l 14.20 14.80 l1 3.70 4.30 l2 18.50 ?p 3.55 3.65 ?r 4.50 5.50 s 5.30 5.50 5.70
STW40N90K5, stwa40n90k5 packa ge mechanical data docid028929 rev 2 11 / 14 4.2 to - 247 long leads package information figure 21 : to - 247 long lead package outline
package mechanical data STW40N90K5, stwa40n90k5 12 / 14 docid028929 rev 2 table 11: to - 247 long lead package mechanical data dim. mm min. typ. max. a 4.90 5.00 5.10 a1 2.31 2.41 2.51 a2 1.90 2.00 2.10 b 1.16 1.26 b2 3.25 b3 2.25 c 0.59 0.66 d 20.90 21.00 21.10 e 15.70 15.80 15.90 e2 4.90 5.00 5.10 e3 2.40 2.50 2.60 e 5.34 5.44 5.54 l 19.80 19.92 20.10 l1 4.30 p 3.50 3.60 3.70 q 5.60 6.00 s 6.05 6.15 6.25
STW40N90K5, stwa40n90k5 revision history docid028929 rev 2 13 / 14 5 revision history table 12: document revision history date revision changes 26 - jan - 2016 1 first release. 25 - nov - 2016 2 updated section 1: "electrical ratings" and section 2: "electrical characteristics" added section 2.1: "electrical characteristics (curves)" . document status changed from preliminary to production data. minor text changes.
STW40N90K5, stwa40n90k5 14 / 14 docid028929 rev 2 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics C all rights reserved

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