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| this is preliminary information on a new product now in dev elopment or undergoing evaluati on. details are subject to change without notice. june 2017 docid030584 rev 2 1/84 STM8S001J3 16 mhz stm8s 8-bit mcu, 8-kbyt e flash memory, 128-byte data eeprom, 10-bit adc, 3 timers, uart, spi, i2c datasheet - preliminary data features core ? 16 mhz advanced stm8 core with harvard architecture and 3-stage pipeline ? extended instruction set memories ? program memory: 8 kbytes flash memory; data retention 20 years at 55 c after 100 cycles ? ram: 1 kbyte ? data memory: 128-byte true data eeprom; endurance up to 100 k write/erase cycles clock, reset and supply management ? 2.95 v to 5.5 v operating voltage ? flexible clock control, 3 master clock sources ? external clock input ? internal, user-trimmable 16 mhz rc ? internal low-po wer 128 khz rc ? clock security system with clock monitor ? power management ? low-power modes (wait, active-halt, halt) ? switch-off peripheral clocks individually ? permanently active, low-consumption power-on and power-down reset interrupt management ? nested interrupt contro ller with 32 interrupts ? up to 5 external interrupts timers ? advanced control timer: 16-bit, 2 capcom channels, 2 outputs, dead-time insertion and flexible synchronization ? 16-bit general purpose timer, with 3 capcom channels (ic, oc or pwm) ? 8-bit basic timer with 8-bit prescaler ? auto wakeup timer ? window and independent watchdog timers communications interfaces ? uart, smartcard, irda, lin master mode ? spi unidirectional interf ace up to 8 mbit/s (master simplex mode, slave receiver only) ? i2c interface up to 400 kbit/s analog to digital converter (adc) ? 10-bit adc, 1 lsb adc with up to 3 multiplexed channels, scan mode and analog watchdog i/os ? up to 5 i/os including 4 high-sink outputs ? highly robust i/o design, immune against current injection development support ? embedded single-wire interface module (swim) or fast on-chip programming and non- intrusive debugging so8n 4.9x6 mm or 150 mils width www.st.com
contents STM8S001J3 2/84 docid030584 rev 2 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 central processing unit stm8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 single wire interface module (swim) and debug module (dm) . . . . . . . . 12 4.3 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 flash program memory and data eeprom . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.9 tim1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.10 tim2 - 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.11 tim4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.12 analog-to-digital converter (adc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.13 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.13.1 uart1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.13.2 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13.3 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 STM8S001J3 so8n pinout and pin description . . . . . . . . . . . . . . . . . . . . 20 5.2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2.1 i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2.2 general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 docid030584 rev 2 3/84 STM8S001J3 contents 4 6.2.3 cpu/swim/debug module/interrupt contro ller registers . . . . . . . . . . . . 33 7 interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.1 alternate function remapping bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.3.1 vcap external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.3.2 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.3.3 external clock sources and timing characteristics . . . . . . . . . . . . . . . . . 53 9.3.4 internal clock sources and timing characte ristics . . . . . . . . . . . . . . . . . 53 9.3.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.3.6 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.3.7 spi serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.3.8 i2c interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.3.9 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.3.10 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.1 so8n package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 79 11 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12 stm8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.1 emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 81 contents STM8S001J3 4/84 docid030584 rev 2 12.2 software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.2.1 stm8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.2.2 c and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 docid030584 rev 2 5/84 STM8S001J3 list of tables 6 list of tables table 1. STM8S001J3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. peripheral clock gating bit assignments in clk_pckenr1/2 registers . . . . . . . . . . . . . . . 15 table 3. tim timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. legend/abbreviations for STM8S001J3 pin description tables. . . . . . . . . . . . . . . . . . . . . . 20 table 5. STM8S001J3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. flash, data eeprom and ram b oundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 7. i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8. general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 11. option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 13. STM8S001J3 alternate function remapping bits fo r 8-pin devices . . . . . . . . . . . . . . . . . . . 38 table 14. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 15. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 16. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 17. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 18. operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19. total current consumption wit h code execution in run mode at v dd = 5 v . . . . . . . . . . . . 44 table 20. total current consumption wit h code execution in run mode at v dd = 3.3 v . . . . . . . . . . . 45 table 21. total current consumption in wait mode at v dd = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 22. total current consumption in wait mode at v dd = 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 23. total current consumption in active halt mode at v dd = 5 v . . . . . . . . . . . . . . . . . . . . . . . 47 table 24. total current consumption in active halt mode at v dd = 3.3 v . . . . . . . . . . . . . . . . . . . . . 47 table 25. total current consum ption in halt mode at v dd = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 26. total current consum ption in halt mode at v dd = 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 27. wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 28. total current consumption and ti ming in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 49 table 29. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 30. hse user external clock characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 table 31. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 32. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 33. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 34. flash program memory and data eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 35. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 36. output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 37. output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 38. output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 39. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 40. i2c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 41. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 42. adc accuracy with r ain < 10 k , v dd = 5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 43. adc accuracy with r ain < 10 k r ain , v dd = 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 44. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 45. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 46. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 47. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 48. so8n ? 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, list of tables STM8S001J3 6/84 docid030584 rev 2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 49. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 50. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 docid030584 rev 2 7/84 STM8S001J3 list of figures 7 list of figures figure 1. STM8S001J3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. STM8S001J3 so8n pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 6. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 7. f cpumax versus v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 8. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 9. typ. i dd(run) vs v dd , hse user external clock, f cpu = 16 mhz . . . . . . . . . . . . . . . . . . . . 50 figure 10. typ. i dd(run) vs f cpu , hse user external clock, v dd = 5 v . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 11. typ. i dd(run) vs v dd , hsi rc osc, f cpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 12. typ. i dd(wfi) vs. v dd hse user external clock, f cpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . 51 figure 13. typ. i dd(wfi) vs. f cpu , hse user external clock, v dd = 5 v . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 14. typ. i dd(wfi) vs v dd , hsi rc osc, f cpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 15. hse external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 16. typical hsi frequency variation vs v dd at 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 17. typical lsi frequency variation vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 18. typical v il and v ih vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 19. typical pull-up resistance vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 20. typical pull-up current vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 21. typ. v ol @ v dd = 5 v (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 22. typ. v ol @ v dd = 3.3 v (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 23. typ. v ol @ v dd = 5 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 24. typ. v ol @ v dd = 3.3 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 25. typ. v ol @ v dd = 5 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 26. typ. v ol @ v dd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 27. typ. v dd - v oh @ v dd = 5 v (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 28. typ. v dd - v oh @ v dd = 3.3 v (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 29. typ. v dd - v oh @ v dd = 5 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 30. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 31. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 32. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 33. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 34. typical application with i2c bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 35. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 36. typical application with adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 37. so8n ? 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline . 76 figure 38. so8n ? 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 39. so8n ? 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 40. STM8S001J3 ordering information scheme (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 introduction STM8S001J3 8/84 docid030584 rev 2 1 introduction this datasheet contains the description of the STM8S001J3 features, pinout, electrical characteristics, mechanical data and ordering information. ? for complete information on the stm8s microcontroller memory, registers and peripherals, please refer to the stm8s and stm8a microc ontroller fam ilies reference manual (rm0016). ? for information on programming, erasing and protection of the internal flash memory please refer to the pm0051 (how to program stm8s and stm8a flash program memory and data eeprom). ? for information on the debug and swim (s ingle wire interface module) refer to the stm8 swim communication protocol and debug module user manual (um0470). ? for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044). docid030584 rev 2 9/84 STM8S001J3 description 23 2 description the STM8S001J3 8-bit microcontrollers offer 8 kbytes of flash program memory, plus integrated true data eeprom. it is referr ed to as low-density device in the stm8s microcontroller family reference manual (rm0016). the STM8S001J3 device provides the followi ng benefits: performance, robustness and reduced system cost. device performance and robu stness are ensured by true data eeprom supporting up to 100000 write/erase cycles, advanced core an d peripherals made in a state-of-the-art technology at 16 mhz clock frequency, robust i/os, independent watchdogs with separate clock source, and a clock security system. the system cost is reduced thanks to a high system integration leve l with internal clock oscillators, watchdog, and brown-out reset. full documentation is offered as well as a wide choice of development tools. table 1. STM8S001J3 features features STM8S001J3 pin count 8 max. number of gpios (i/o) 5 external interrupt pins 5 timer capcom channels 3 timer complementary outputs 1 a/d converter channels 3 high-sink i/os 4 low-density flash program memory (byte) 8 k ram (byte) 1 k true data eeprom (byte) 128 (1) 1. without read-while-write capability. peripheral set multi purpose timer (tim1), spi unidirectional, i2c, uart, window wdg, independent wdg, adc, pwm timer (tim2), 8-bit timer (tim4) block diagram STM8S001J3 10/84 docid030584 rev 2 3 block diagram figure 1. STM8S001J3 block diagram 0 6 y 9 5 h v h w e o r f n 5 h v h w 3 2 5 % 2 5 & o r f n f r q w u r o o h u ' h w h f w r u 5 & l q w 0 + ] 5 & l q w n + ] ( [ w & o r f n l q s x w 0 + ] 6 7 0 f r u h ' h e x j 6 : , 0 , & 8 q l g l u h f w l r q d o 6 3 , 8 $ 5 7 $ ' & : l q g r z : ' * , q g h s h q g h q w : ' * . e \ w h s u r j u d p ) o d v k e \ w h g d w d ( ( 3 5 2 0 . e \ w h 5 $ 0 e l w d g y d q f h g f r q w u r o w l p h u 7 0 e l w j h q h u d o s x u s r v h w l p h u 7 , 0 e l w e d v l f w l p h u 7 , 0 $ : 8 w l p h u $ g g u h v v d q g g d w d e x v & o r f n w r s h u l s k h u d o v d q g f r u h 8 s w r f k d q q h o v / , 1 p d v w h u 0 e l w v . e l w v 6 l q j o h z l u h g h e x j l q w h u i d f h 8 s w r & $ 3 & 3 2 0 f k d q q h o v 8 s w r & $ 3 & 3 2 0 f k d q q h o v docid030584 rev 2 11/84 STM8S001J3 functional overview 23 4 functional overview the following section intends to give an overvi ew of the basic featur es of the STM8S001J3 functional modules and peripherals. for more detailed information please refer to the corresponding family reference manual (rm0016). 4.1 central proc essing unit stm8 the 8-bit stm8 core is designed for code efficiency and performance. it contains six internal registers which are dire ctly addressable in each execution context, 20 addressing modes including indexed indirect an d relative addressing and 80 instructions. architecture and registers ? harvard architecture ? 3-stage pipeline ? 32-bit wide program memory bus - single cycle fetching for most instructions ? x and y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations ? 8-bit accumulator ? 24-bit program counter - 16-mbyte linear memory space ? 16-bit stack pointer - acce ss to a 64 k-level stack ? 8-bit condition code register - 7 condition fl ags for the result of the last instruction addressing ? 20 addressing modes ? indexed indirect addressing mode for look-up tables located anywhere in the address space ? stack pointer relative addressing mode for local variables and parameter passing instruction set ? 80 instructions with 2-byte average instruction size ? standard data movement and logic/arithmetic functions ? 8-bit by 8-bit multiplication ? 16-bit by 8-bit and 16-bit by 16-bit division ? bit manipulation ? data transfer between stack and accumu lator (push/pop) with direct stack access ? data transfer using the x and y registers or direct memory-to-memory transfers functional overview STM8S001J3 12/84 docid030584 rev 2 4.2 single wire interface module (swim) and debug module (dm) the single wire interface module and debug module permits non-intrusive, real-time in- circuit debugging and fast memory programming. swim single wire interface module for direct access to the debug module and memory programming. the interface can be activated in all device operation modes. the maximum data transmission speed is 145 byte/ms. debug module the non-intrusive debugging module features a performance close to a full-featured emulator. beside memory and peripherals, also cpu operation can be monitored in real- time by means of shadow registers. ? r/w to ram and peripheral registers in real-time ? r/w access to all resour ces by stalling the cpu ? breakpoints on all program-memory instructions (software breakpoints) ? two advanced breakpoints, 23 predefined configurations recommendation for swim pin (pin #8) sharing as the nrst pin is not available on this device, if the swim pin should be used with the i/o pin functionality, it is recommended to add a ~5 seconds delay in the firmware before changing the functionality on the pin with swim functions. this action allows the user to set the device into swim mode after the device power on and to be able to reprogram the device. if the pin with swim functionality is set to i/o mode immediately after the device reset, the device is unable to connect through the swim interface and it gets locked forever. this initial delay can be removed in the final (locked) code. 4.3 interrupt controller ? nested interrupts with three software priority levels ? 32 interrupt vectors with hardware priority ? up to 5 external interrupts including tli ? trap and reset interrupts 4.4 flash program memory and data eeprom ? 8 kbytes of flash program single voltage flash memory ? 128 byte true data eeprom ? user option byte area write protection (wp) write protection of flash program memory and data eeprom is provided to avoid unintentional overwriting of me mory that could result from a user software malfunction. docid030584 rev 2 13/84 STM8S001J3 functional overview 23 there are two levels of write protection. the first level is known as mass (memory access security system). mass is always enabled and protects the main flash program memory, data eeprom and option bytes. to perform in-application programming (iap), this write protection can be removed by writing a mass key sequence in a control register. this allo ws the applicatio n to modify the content of main program me mory and data eeprom, or to reprogram the device option bytes. a second level of write protection, can be en abled to further protect a specific area of memory known as ubc (user boot code). refer to figure 2 . the size of the ubc is programmable through the ubc option byte ( table 12 ), in increments of 1 page (64-byte block) by programming the ubc option byte in icp mode. this divides the program memory into two areas: ? main program memory: 8 kbyte minus ubc ? user-specific boot code (ubc): configurable up to 8 kbyte the ubc area remains write-protected during in-application programming. this means that the mass keys do not unlock the ubc area. it protects the memory used to store the boot program, specific code libraries, reset and in terrupt vectors, the reset routine and usually the iap and communication routines. figure 2. flash memory organization read-out protection (rop) the read-out protection blocks reading and writing the flash program memory and data eeprom memory in icp mode (and debug mode). once th e read-out protection is activated, any attempt to togg le its status triggers a global erase of the program memory. even if no protection can be considered as to tally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. 0 6 9 / r z g h q v l w \ ) o d v k s u r j u d p p h p r u \ . e \ w h v 3 u r j u d p p d e o h d u h d i u r p e \ w h v s d j h x s w r . e \ w h v l q s d j h v w h s v 3 u r j u d p p h p r u \ d u h d : u l w h d f f h v v s r v v l e o h i r u , $ 3 8 % & d u h d 5 h p d l q v z u l w h s u r w h f w h g g x u l q j , $ 3 ' d w d ( ( 3 5 2 0 e \ w h v 2 s w l r q e \ w h v functional overview STM8S001J3 14/84 docid030584 rev 2 recommendation for the device's programming: the device's 8 kbytes program memory is not em pty on virgin devices; there is code loop implemented on the reset vector. it is recommended to keep valid code loop in the device to avoid the program execution from an invalid memory address (which would be any memory address out of 8 kbytes program memory space). if the device's program memory is empty (0x00 content), it displays the behavior described below: ? after the power on, the ?empty? code is ex ecuted (0x0000 opcodes = instructions: neg (0x00, sp)) until the device reaches the en d of the 8 kbytes program memory (the end address = 0x9fff). it takes around 4 milliseconds to reach the end of the 8 kbytes memory space @2 mhz hsi clock. ? once the device reaches the end of the 8 kbytes program memory, the program continues and code from a non-existing memory is fetched and executed. the reading of non-existing memory is a random content which can lead to the execution of inva lid instructions. the execution of invalid instructions generates a software reset and the program starts again. a reset can be generat ed every 4 milliseconds or more. only the ?connect on-the-fly ? method can be used to program the device through the swim interface. the ?connect under-reset? method cannot be used because the nrst pin is not available on this device. the ?connect on-the-fly? mode can be used while th e device is executing code, but if there is a device reset (by software re set) during the swim connection, this connection is aborted and it must be performed again from the debug tool. note that the software reset occurrence can be of every 4 milliseconds, making it diff icult to successfully connect to the device's debug tool (there is practically only one successful connection trial for every 10 attempts). once that a successful connection is reach ed, the device can be programmed with a valid firmware without problems; therefore it is recommended that device is never erased and that is contains always a valid code loop. docid030584 rev 2 15/84 STM8S001J3 functional overview 23 4.5 clock controller the clock controller distributes the system clock (f master) coming from different oscillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. features ? clock prescaler : to get the best compromise between speed and current consumption the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler. ? safe clock switching : clock sources can be changed safely on the fly in run mode through a configuration register. the clock signal is not switched until the new clock source is ready. the design guarantees glitch-free switching. ? clock management : to reduce power consumption, th e clock controller can stop the clock to the core, individual peripherals or memory. ? master clock sources : three different clock sources can be used to drive the master clock: ? up to 16 mhz high-speed user-external clock (hse user-ext) ? 16 mhz high-speed internal rc oscillator (hsi) ? 128 khz low-speed internal rc (lsi) ? startup clock : after reset, the microcontroller restarts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ? clock security system (css) : this feature can be enabled by software. if an hse clock failure occurs, the internal rc (16 mh z/8) is automatically selected by the css and an interrupt can optionally be generated. ? configurable main clock output (cco) : this outputs an external clock for use by the application. table 2. peripheral clock gating bit a ssignments in clk_pc kenr1/2 registers bit peripheral clock bit peripheral clock bit peripheral clock bit peripheral clock pcken17 tim1 pcken13 uart1 pcken27 reserved pcken23 adc pcken16 reserved pcken12 reserved pcken26 reserved pcken22 awu pcken15 tim2 pcken11 spi pcken25 reserved pcken21 reserved pcken14 tim4 pcken10 i2c pcken24 reserved pcken20 reserved functional overview STM8S001J3 16/84 docid030584 rev 2 4.6 power management for efficient power management , the application can be put in one of four different low- power modes. you can configure each mode to obtain the best compromise between the lowest power consumption, t he fastest start-up time and available wakeup sources. ? wait mode : in this mode, the cpu is stopped, but peripherals are kept running. the wakeup is performed by an internal or external interrupt or reset. ? active halt mode with regulator on : in this mode, the cpu and peripheral clocks are stopped. an internal wakeup is generated at programmable intervals by the auto wake up unit (awu). the main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. wakeup is triggered by th e internal awu interrupt, ex ternal interrupt or reset. ? active halt mode with regulator off: this mode is the same as active halt with regulator on, except that the main voltage regul ator is powered off, so the wake up time is slower. ? halt mode : in this mode the microcontroller uses the least power. the cpu and peripheral clocks are stopped, the main voltage regulator is powered off. wakeup is triggered by exter nal event or reset. 4.7 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. activation of the watchdog timers is contro lled by option bytes or by software. once activated, the watchdogs cannot be disabled by the user program without performing a reset. window watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by un expected logical conditions, which cause the application program to abandon its normal sequence. the window function can be used to trim the watchdog behavior to match the application perfectly. the application software must refresh the coun ter before time-out and during a limited time window. a reset is generated in two situations: 1. timeout: at 16 mhz cpu clock the time-out period can be adjusted between 75 s up to 64 ms. 2. refresh out of window: the down-counter is refreshed before its value is lower than the one stored in the window register. docid030584 rev 2 17/84 STM8S001J3 functional overview 23 independent watchdog timer the independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the 128 khz lsi internal rc clock source, and thus stays active even in case of a cpu clock failure the iwdg time base spans from 60 s to 1 s. 4.8 auto wakeup counter ? used for auto wakeup from active halt mode ? clock source: internal 128 khz internal low frequency rc oscillator or external clock ? lsi clock can be internally connected to tim1 input capture channel 1 for calibration 4.9 tim1 - 16-bit advanced control timer this is a high-end timer designed for a wi de range of control applications. with its complementary outputs, dead-tim e control and center-aligned pw m capability, the field of applications is extended to lighting and half-bridge driver. ? 16-bit up, down and up/down autoreload counter with 16-bit prescaler ? four independent capture/compare channels (capcom) configurable as input capture, output compare, pwm generation (e dge and center aligned mode) and single pulse mode output ? synchronization module to contro l the timer with external signals ? break input to force the timer outputs into a defined state ? one complementary output (ch1 with ch1n option) with adjustable dead time ? interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break 4.10 tim2 - 16-bit ge neral purpose timer ? 16-bit autoreload (ar) up-counter ? 15-bit prescaler adjustable to fixed power of 2 ratios 1?32768 ? 3 individually configurable capture/compare channels ? pwm mode ? interrupt sources: 3 x input capture/output compare, 1 x overflow/update 4.11 tim4 - 8-bit basic timer ? 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 ? clock source: cpu clock ? interrupt source: 1 x overflow/update functional overview STM8S001J3 18/84 docid030584 rev 2 4.12 analog-to-digita l converter (adc1) STM8S001J3 contains a 10-bit successive app roximation a/d converter (adc1) with up to three external multiplexed input channels and the following main features: ? input voltage range: 0 to v dda ? conversion time: 14 clock cycles ? single and continuous, buffered continuous conversion modes ? buffer size (10 x 10 bits) ? scan mode for single and continuous conversion of a sequence of channels ? analog watchdog capability with progra mmable upper and lower thresholds ? analog watchdog interrupt ? external trigger input ? trigger from tim1 trgo ? end of conversion (eoc) interrupt 4.13 communication interfaces the following communication interfaces are implemented: ? uart1: full feature uart, synchronous mo de, smartcard mode, irda mode, lin2.1 master capability ? spi: master mode transmit/receive only, slave mode receive only, 8 mbit/s ? i2c: up to 400 kbit/s 4.13.1 uart1 main features ? 1 mbit/s full duplex sci ? high precision baud rate generator ? smartcard reader emulation ? irda sir encoder decoder ? lin master mode ? single wire half duplex mode table 3. tim timer features timer counter size (bits) prescaler counting mode capcom channels complem. outputs ext. trigger timer synchr- onization/ chaining tim1 16 any integer from 1 to 65536 up/down 2 1 (1) no no tim2 16 any power of 2 from 1 to 32768 up 3 0 no tim4 8 any power of 2 from 1 to 128 up 0 0 no 1. tim1_ch2n with tim1_ch1 docid030584 rev 2 19/84 STM8S001J3 functional overview 23 asynchronous communication (uart mode) ? full duplex communication - nrz standard format (mark/space) ? programmable transmit and receive baud rates up to 1 mbit/s (f cpu /16) and capable of following any standard baud rate regardless of the input frequency ? separate enable bits for transmitter and receiver ? two receiver wakeup modes: ? address bit (msb) ? idle line (interrupt) ? transmission error detection with interrupt generation ? parity control lin master mode ? emission: generates 13-bit synch. break frame ? reception: detects 11-bit break frame 4.13.2 spi ? maximum speed: 8 mbit/s (f master /2) both for master and slave ? unidirectional transfer: spi master mode transmit/receive only, spi slave mode receive only ? simplex master synchronous tr ansfers on two lines with a possible bidirectional data line ? master or slave operation - selectable by software ? crc calculation ? 1 byte tx and rx buffer 4.13.3 i2c ? i2c master features ? clock generation ? start and stop generation ? i2c slave features ? programmable i2c address detection ? stop bit detection ? generation and detection of 7-bit/10-bit addressing and general call ? supports different communication speeds ? standard speed (up to 100 khz) ? fast speed (up to 400 khz) pinouts and pin descriptions STM8S001J3 20/84 docid030584 rev 2 5 pinouts and pin descriptions this section presents the pinouts an d pin descriptions for STM8S001J3. table 4 introduces the legends and abbreviations that ar e used in the upcoming subsections. 5.1 STM8S001J3 so8n pino ut and pin description figure 3 presents the STM8S001J3 pinout image and table 5 below presents the device?s pins description. figure 3. STM8S001J3 so8n pinout 1. [ ] alternative function option (if the same alternate f unction is shown twice, it i ndicated an exclusive choice and not a duplication of the function). table 4. legend/abbreviations for STM8S001J3 pin description tables type i = input, o = output, s = power supply level input cm = cmos output hs = high sink output speed o1 = slow (up to 2 mhz) o2 = fast (up to 10 mhz) o3 = fast/slow programmability with slow as default state after reset o4 = fast/slow programmability with fast as default state after reset port and control configuration input float = floating, wpu = weak pull-up output t = true open drain, od = open drain, pp = push pull reset state bold x (pin state after in ternal reset release) unless otherwise specified, the pin stat e is the same during the reset phase and after the internal reset release. 0 6 y 9 6 7 0 6 3 ' $ , 1 8 $ 5 7 b 7 ; 3 ' $ , 1 7 , 0 b & + $ ' & b ( 7 5 3 ' 6 : , 0 3 & 6 3 , b 0 2 6 , > 7 , 0 b & + @ 3 & 6 3 , b 6 & . > 7 , 0 b & + @ 3 & & / . b & & 2 7 , 0 b & + > $ , 1 @ > 7 , 0 b & + 1 @ 3 & 7 , 0 b & + > 7 / , @ > 7 , 0 b & + 1 @ 3 % , & b 6 & / > $ ' & b ( 7 5 @ 3 % , & b 6 ' $ > 7 , 0 b % . , 1 @ 3 $ 7 , 0 b & + > 6 3 , b 1 6 6 @ > 8 $ 5 7 b 7 ; @ 3 ' $ , 1 8 $ 5 7 b 5 ; 3 $ 2 6 & , 1 9 6 6 9 6 6 $ 9 & $ 3 9 ' ' 9 ' ' $ docid030584 rev 2 21/84 STM8S001J3 pinouts and pin descriptions 23 table 5. STM8S001J3 pin description pin no. pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] so8n floating wpu ext. interr. high sink (1) speed od pp 1 pd6/ ain6/ uart1 _rx i/o x xx hs o3 xx port d6 analog input 6/ uart1 data receive - pa1/ oscin (2) i/o x x x - o1 x x port a1 external clock input (hse clock) - 2 vss/vssa s - - - - - - - ground - 3 vcap s - - - - - - - 1.8 v regulator capacitor - 4 vdd/vdda s - - - - - - - power supply - 5 pa3/ tim2_ ch3 [spi_ nss]\ [uart1_tx] i/o x x x hs o3 x x port a3 timer 2 channel 3 spi master/ slave select [afr1] uart1 data transmit [afr1 and afr0] pb5/ i2c_ sda [tim1_ bkin] i/o x - x - o1 t (3) - port b5 i2c data timer 1 - break input [afr4] 6 pb4/ i2c_ scl /[adc_etr] i/o x - x - o1 t (3) - port b4 i2c clock adc external trigger [afr4] 7 pc3/ tim1_ch3 [tli] [tim1_ ch1n] i/o x x x hs o3 x x port c3 timer 1 - channel 3 to p l e v e l interrupt [afr3] timer 1 - inverted channel 1 [afr7] pc4/ clk_cco/ tim1_ ch4/[ain2]/ [tim1_ ch2n] i/o x x x hs o3 x x port c4 configurable clock output/timer 1 - channel 4 analog input 2 [afr2], timer 1 - inverted channel 2 [afr7] pc5/ spi_sck [tim2_ ch1] i/o x x x hs o3 x x port c5 spi clock timer 2 - channel 1 [afr0] pinouts and pin descriptions STM8S001J3 22/84 docid030584 rev 2 note: the pa2, pb0, pb1, pb2, pb3 , pb6, pb7, pc1, pc2, pc7, pd 0, pd2, pd4, pd7, pe5 and pf4 gpios should be configured after device reset in output push-pull mode with output low-state to reduce the device?s consumption and to improve its emc immunity. the gpios mentioned above are not connected to pins, an d they are in input-floating mode after a device reset. note: as several pins provide a connection to mult iple gpios, the mode selection for any of those gpios impacts all the other gpios connected to the same pin. the user is responsible for the proper setting of the gpio modes in orde r to avoid conflicts between gpios bonded to the same pin (including their alternate functions). for example, pull-up enabled on pd1 is also seen on pc6, pd3 and pd5. push-pull co nfiguration of pc3 is also seen on pc4 and pc5, etc. 8 pc6/ spi_mosi [tim1_ ch1] i/o x (4) x x hs o3 x x port c6 spi master out/slave in timer 1 - channel 1 [afr0] pd1/ swim (4) i/o x x (4) x hs o4 x x port d1 swim data interface - pd3/ ain4/ tim2_ ch2/ adc_ etr i/o x (4) x x hs o3 x x port d3 analog input 4/ timer 2 - channel 2/adc external trigger - pd5/ ain5/ uart1 _tx i/o x (4) xx hs o3 xx port d5 analog input 5/ uart1 data transmit - 1. i/o pins used simultaneously for high current source/sink must be uniformly spaced around the package. in addition, the total driven current must respect the absolute maximum ratings. 2. when the mcu is in halt/active-halt mode, pa1 is automatically configured in input weak pull-up and cannot be used for waking up the device. in this mode, the output state of pa1 is not driven. it is recommended d to use pa1 only in input mode if halt/active-halt is used in the application. 3. in the open-drain output column, ?t? defines a true open-drain i/o (p-buffer, weak pull-up, and protection diode to vdd are not implemented). although pb5 itself is a true open drain gpio with its respective internal circuitry and characteristics, v in maximum of the pin number 5 is limited by the st andard gpio pa3 which is also bonded to pin number 5. 4. the pd1 pin is in input pull-up during the reset phase and after internal reset release. this pd1 default state influences al l gpios connected in parallel on pin# 8 (pc6, pd3, pd5). table 5. STM8S001J3 pin description (continued) pin no. pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] so8n floating wpu ext. interr. high sink (1) speed od pp docid030584 rev 2 23/84 STM8S001J3 pinouts and pin descriptions 23 5.2 alternate func tion remapping as shown in the rightmost column of the pin de scription table, some alternate functions can be remapped at different i/o ports by programming one of eight afr (alternate function remap) option bits. refer to section 8: option bytes . when the remapping option is active, the default alternate function is no longer available. to use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. alternate function remapping does not effect gpio capabilities of the i/o ports (see the gpio section of the family reference manual, rm0016). memory and register map STM8S001J3 24/84 docid030584 rev 2 6 memory and register map 6.1 memory map figure 4. memory map [ ) ) ) ) o d v k s u r j u d p p h p r u \ . e \ w h [ 5 $ 0 [ ) ) . e \ w h e \ w h v w d f n 5 h v h u y h g 5 h v h u y h g [ $ [ ) ) ) [ ) ) [ l q w h u u x s w y h f w r u v [ ) * 3 , 2 d q g s h u l s k u h j [ [ ) ) [ [ ) ) ) [ % [ ) ) ) [ ( ) ) & 3 8 6 : , 0 g h e x j , 7 & u h j l v w h u v [ ) 5 h v h u y h g 2 s w l r q e \ w h v [ $ [ [ [ 5 h v h u y h g [ ) ' d w d ( ( 3 5 2 0 [ 5 h v h u y h g 0 6 9 docid030584 rev 2 25/84 STM8S001J3 memory and register map 35 table 6 lists the boundary addresses for each memory size. the top of the stack is at the ram end address in each case. 6.2 register map 6.2.1 i/o port hardware register map table 6. flash, data eeprom and ram boundary addresses memory area size (byte) start address end address flash program memory 8 k 0x00 8000 0x00 9fff ram 1 k 0x00 0000 0x00 03ff data eeprom 128 0x00 4000 0x00 407f table 7. i/o port ha rdware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data output latch register 0x00 0x00 5001 pa_idr port a input pin value register 0xxx (1) 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x00 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0xxx (1) 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pb_idr port c input pin value register 0xxx (1) 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 port c control register 2 0x00 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0xxx (1) 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x02 0x00 5013 pd_cr2 port d control register 2 0x00 memory and register map STM8S001J3 26/84 docid030584 rev 2 6.2.2 general hardwa re register map 0x00 5014 port e pe_odr port e data output latch register 0x00 0x00 5015 pe_idr port e input pin value register 0xxx (1) 0x00 5016 pe_ddr port e data direction register 0x00 0x00 5017 pe_cr1 port e control register 1 0x00 0x00 5018 pe_cr2 port e control register 2 0x00 0x00 5019 port f pf_odr port f data output latch register 0x00 0x00 501a pf_idr port f input pin value register 0xxx (1) 0x00 501b pf_ddr port f data direction register 0x00 0x00 501c pf_cr1 port f control register 1 0x00 0x00 501d pf_cr2 port f control register 2 0x00 1. depends on the external circuitry. table 7. i/o port hardware register map (continued) address block register label register name reset status docid030584 rev 2 27/84 STM8S001J3 memory and register map 35 table 8. general hard ware register map address block register label register name reset status 0x00 501e to 0x00 5059 reserved area (60 byte) 0x00 505a flash flash_cr1 flash control register 1 0x00 0x00 505b flash_cr2 flash control register 2 0x00 0x00 505c flash_ncr2 flash complementary control register 2 0xff 0x00 505d flash _fpr flash protection register 0x00 0x00 505e flash _nfpr flash complementary protection register 0xff 0x00 505f flash _iapsr flash in-application programming status register 0x00 0x00 5060 to 0x00 5061 reserved area (2 byte) 0x00 5062 flash flash _pukr flash program memo ry unprotection register 0x00 0x00 5063 reserved area (1 byte) 0x00 5064 flash flash _dukr data eeprom unprotection register 0x00 0x00 5065 to 0x00 509f reserved area (59 byte) 0x00 50a0 itc exti_cr1 external interrupt control register 1 0x00 0x00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 to 0x00 50b2 reserved area (17 byte) 0x00 50b3 rst rst_sr reset status register 0xxx (1) 0x00 50b4 to 0x00 50bf reserved area (12 byte) 0x00 50c0 clk clk_ickr internal clock control register 0x01 0x00 50c1 clk_eckr external clock control register 0x00 0x00 50c2 reserved area (1 byte) 0x00 50c3 clk clk_cmsr clock master status register 0xe1 0x00 50c4 clk_swr clock master switch register 0xe1 0x00 50c5 clk_swcr clock switch control register 0xxx 0x00 50c6 clk_ckdivr clock divider register 0x18 0x00 50c7 clk_pckenr1 peripheral clock gating register 1 0xff 0x00 50c8 clk_cssr clock secu rity system register 0x00 0x00 50c9 clk_ccor configurable clock control register 0x00 0x00 50ca clk_pckenr2 peripheral clock gating register 2 0xff 0x00 50cb reserved area (1 byte) memory and register map STM8S001J3 28/84 docid030584 rev 2 0x00 50cc clk clk_hsitrimr hsi clock calibration trimming register 0x00 0x00 50cd clk_swimccr swim clock control register 0bxxxx xxx0 0x00 50ce to 0x00 50d0 reserved area (3 byte) 0x00 50d1 wwdg wwdg_cr wwdg control register 0x7f 0x00 50d2 wwdg_wr wwdr window register 0x7f 0x00 50d3 to 0x00 50df reserved area (13 byte) 0x00 50e0 iwdg iwdg_kr iwdg key register 0xxx (2) 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 byte) 0x00 50f0 awu awu_csr1 awu control/status register 1 0x00 0x00 50f1 awu_apr awu asynchronous prescaler buffer register 0x3f 0x00 50f2 awu_tbr awu timebase selection register 0x00 0x00 50f3 to 0x00 50ff reserved area (13 byte) 0x00 5200 spi spi_cr1 spi control register 1 0x00 0x00 5201 spi_cr2 spi control register 2 0x00 0x00 5202 spi_icr spi inte rrupt control register 0x00 0x00 5203 spi_sr spi status register 0x02 0x00 5204 spi_dr spi data register 0x00 0x00 5205 spi_crcpr spi crc polynomial register 0x07 0x00 5206 spi_rxcrcr spi rx crc register 0x00 0x00 5207 spi_txcrcr spi tx crc register 0x00 0x00 5208 to 0x00 520f reserved area (8 byte) 0x00 5210 i2c i2c_cr1 i2c control register 1 0x00 0x00 5211 i2c_cr2 i2c control register 2 0x00 0x00 5212 i2c_freqr i2c frequency register 0x00 0x00 5213 i2c_oarl i2c own address register low 0x00 0x00 5214 i2c_oarh i2c own address register high 0x00 0x00 5215 reserved table 8. general hardware register map (continued) address block register label register name reset status docid030584 rev 2 29/84 STM8S001J3 memory and register map 35 0x00 5216 i2c i2c_dr i2c data register 0x00 0x00 5217 i2c_sr1 i2c status register 1 0x00 0x00 5218 i2c_sr2 i2c status register 2 0x00 0x00 5219 i2c_sr3 i2c status register 3 0x00 0x00 521a i2c_itr i2c interrupt control register 0x00 0x00 521b i2c_ccrl i2c clock control register low 0x00 0x00 521c i2c_ccrh i2c clock control register high 0x00 0x00 521d i2c_triser i2c trise register 0x02 0x00 521e i2c_pecr i2c packet error checking register 0x00 0x00 521f to 0x00 522f reserved area (17 byte) 0x00 5230 uart1 uart1_sr uart1 status register 0xc0 0x00 5231 uart1_dr uart1 data register 0xxx 0x00 5232 uart1_brr1 uart1 baud rate register 1 0x00 0x00 5233 uart1_brr2 uart1 baud rate register 2 0x00 0x00 5234 uart1_cr1 uart1 control register 1 0x00 0x00 5235 uart1_cr2 uart1 control register 2 0x00 0x00 5236 uart1_cr3 uart1 control register 3 0x00 0x00 5237 uart1_cr4 uart1 control register 4 0x00 0x00 5238 uart1_cr5 uart1 control register 5 0x00 0x00 5239 uart1_gtr uart1 guard time register 0x00 0x00 523a uart1_pscr uart1 prescaler register 0x00 0x00 523b to 0x00 523f reserved area (5 bytes) 0x00 523b to 0x00523f reserved area (21 byte) table 8. general hardware register map (continued) address block register label register name reset status memory and register map STM8S001J3 30/84 docid030584 rev 2 0x00 5250 tim1 tim1_cr1 tim1 control register 1 0x00 0x00 5251 tim1_cr2 tim1 control register 2 0x00 0x00 5252 tim1_smcr tim1 slave mode control register 0x00 0x00 5253 tim1_etr tim1 external trigger register 0x00 0x00 5254 tim1_ier tim1 interrupt enable register 0x00 0x00 5255 tim1_sr1 tim1 status register 1 0x00 0x00 5256 tim1_sr2 tim1 status register 2 0x00 0x00 5257 tim1_egr tim1 even t generation register 0x00 0x00 5258 tim1_ccmr1 tim1 capture/compare mode register 1 0x00 0x00 5259 tim1_ccmr2 tim1 capture/compare mode register 2 0x00 0x00 525a tim1_ccmr3 tim1 capture/compare mode register 3 0x00 0x00 525b tim1_ccmr4 tim1 capture/compare mode register 4 0x00 0x00 525c tim1_ccer1 tim1 capture/ compare enable register 1 0x00 0x00 525d tim1_ccer2 tim1 capture/ compare enable register 2 0x00 0x00 525e tim1_cntrh tim1 counter high 0x00 0x00 525f tim1_cntrl tim1 counter low 0x00 0x00 5260 tim1_pscrh tim1 prescaler register high 0x00 0x00 5261 tim1_pscrl tim1 prescaler register low 0x00 0x00 5262 tim1_arrh tim1 aut o-reload register high 0xff 0x00 5263 tim1_arrl tim1 auto-reload register low 0xff 0x00 5264 tim1_rcr tim1 repetition counter register 0x00 0x00 5265 tim1_ccr1h tim1 capture/compare register 1 high 0x00 0x00 5266 tim1_ccr1l tim1 capture/compare register 1 low 0x00 0x00 5267 tim1_ccr2h tim1 capture/compare register 2 high 0x00 0x00 5268 tim1_ccr2l tim1 capture/compare register 2 low 0x00 0x00 5269 tim1_ccr3h tim1 capture/compare register 3 high 0x00 0x00 526a tim1_ccr3l tim1 capture/compare register 3 low 0x00 0x00 526b tim1_ccr4h tim1 capture/compare register 4 high 0x00 0x00 526c tim1_ccr4l tim1 capture/compare register 4 low 0x00 0x00 526d tim1_bkr tim1 break register 0x00 0x00 526e tim1_dtr tim1 dead-time register 0x00 0x00 526f tim1_oisr tim1 output idle state register 0x00 0x00 5270 to 0x00 52ff reserved area (147 byte) table 8. general hardware register map (continued) address block register label register name reset status docid030584 rev 2 31/84 STM8S001J3 memory and register map 35 0x00 5300 tim2 tim2_cr1 tim2 control register 1 0x00 0x00 5301 reserved 0x00 5302 reserved 0x00 5303 tim2_ier tim2 inte rrupt enable register 0x00 0x00 5304 tim2_sr1 tim2 status register 1 0x00 0x00 5305 tim2_sr2 tim2 status register 2 0x00 0x00 5306 tim2_egr tim2 event generation register 0x00 0x00 5307 tim2_ccmr1 tim2 capture/compare mode register 1 0x00 0x00 5308 tim2_ccmr2 tim2 capture/compare mode register 2 0x00 0x00 5309 tim2_ccmr3 tim2 capture/compare mode register 3 0x00 0x00 530a tim2_ccer1 tim2 captur e/compare enable register 1 0x00 0x00 530b tim2_ccer2 tim2 captur e/compare enable register 2 0x00 0x00 530c tim2_cntrh tim2 counter high 0x00 0x00 530d tim2_cntrl tim2 counter low 0x00 0x00 530e tim2_pscr tim2 prescaler register 0x00 0x00 530f tim2_arrh tim2 aut o-reload register high 0xff 0x00 5310 tim2_arrl tim2 auto-reload register low 0xff 0x00 5311 tim2_ccr1h tim2 capture/compare register 1 high 0x00 0x00 5312 tim2_ccr1l tim2 capture/compare register 1 low 0x00 0x00 5313 tim2_ccr2h tim2 capt ure/compare reg. 2 high 0x00 0x00 5314 tim2_ccr2l tim2 capture/compare register 2 low 0x00 0x00 5315 tim2_ccr3h tim2 capture/compare register 3 high 0x00 0x00 5316 tim2_ccr3l tim2 capture/compare register 3 low 0x00 0x00 5317 to 0x00 533f reserved area (43 byte) 0x00 5340 tim4 tim4_cr1 tim4 control register 1 0x00 0x00 5341 reserved 0x00 5342 reserved 0x00 5343 tim4_ier tim4 inte rrupt enable register 0x00 0x00 5344 tim4_sr tim4 status register 0x00 0x00 5345 tim4_egr tim4 event generation register 0x00 0x00 5346 tim4_cntr tim4 counter 0x00 0x00 5347 tim4_pscr tim4 prescaler register 0x00 0x00 5348 tim4_arr tim4 auto-reload register 0xff table 8. general hardware register map (continued) address block register label register name reset status memory and register map STM8S001J3 32/84 docid030584 rev 2 0x00 5349 to 0x00 53df reserved area (153 byte) 0x00 53e0 to 0x00 53f3 adc1 adc_dbxr adc data buffer registers 0x00 0x00 53f4 to 0x00 53ff reserved area (12 byte) 0x00 5400 adc1 adc _csr adc control/status register 0x00 0x00 5401 adc_cr1 adc configuration register 1 0x00 0x00 5402 adc_cr2 adc configuration register 2 0x00 0x00 5403 adc_cr3 adc configuration register 3 0x00 0x00 5404 adc_drh adc data register high 0xxx 0x00 5405 adc_drl adc data register low 0xxx 0x00 5406 adc_tdrh adc schmitt tr igger disable register high 0x00 0x00 5407 adc_tdrl adc schmitt trigger disable register low 0x00 0x00 5408 adc_htrh adc high threshold register high 0x03 0x00 5409 adc_htrl adc high threshold register low 0xff 0x00 540a adc_ltrh adc low threshold register high 0x00 0x00 540b adc_ltrl adc low threshold register low 0x00 0x00 540c adc_awsrh adc analog watchdog status register high 0x00 0x00 540d adc_awsrl adc analog watchdog status register low 0x00 0x00 540e adc_awcrh adc analog watchdog control register high 0x00 0x00 540f adc_awcrl adc analog watchdog control register low 0x00 0x00 5410 to 0x00 57ff reserved area (1008 byte) 1. depends on the previous reset source. 2. write only register. table 8. general hardware register map (continued) address block register label register name reset status docid030584 rev 2 33/84 STM8S001J3 memory and register map 35 6.2.3 cpu/swim/debug module/in terrupt controller registers table 9. cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu (1) a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x00 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a ccr condition code register 0x28 0x00 7f0b to 0x00 7f5f reserved area (85 byte) 0x00 7f60 cpu cfg_gcr global configuration register 0x00 0x00 7f70 itc itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 itc_spr7 interrupt software priority register 7 0xff 0x00 7f77 itc_spr8 interrupt software priority register 8 0xff 0x00 7f78 to 0x00 7f79 reserved area (2 byte) 0x00 7f80 swim swim_csr swim control status register 0x00 0x00 7f81 to 0x00 7f8f reserved area (15 byte) memory and register map STM8S001J3 34/84 docid030584 rev 2 0x00 7f90 dm dm_bk1re dm breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh dm breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl dm breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re dm breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh dm breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl dm breakpoint 2 register low byte 0xff 0x00 7f96 dm_cr1 dm debug module control register 1 0x00 0x00 7f97 dm_cr2 dm debug module control register 2 0x00 0x00 7f98 dm_csr1 dm debug module control/status register 1 0x10 0x00 7f99 dm_csr2 dm debug module control/status register 2 0x00 0x00 7f9a dm_enfctr dm enable function register 0xff 0x00 7f9b to 0x00 7f9f reserved area (5 byte) 1. accessible by debug module only table 9. cpu/swim/debug module/interr upt controller registers (continued) address block register label register name reset status docid030584 rev 2 35/84 STM8S001J3 interrupt vector mapping 35 7 interrupt vector mapping table 10. interrupt mapping irq no. source block description wakeup from halt mode wakeup from active-halt mode vector address - reset reset yes yes 0x00 8000 - trap software interrupt - - 0x00 8004 0 tli external top level interrupt - - 0x00 8008 1 awu auto wake up from halt - yes 0x00 800c 2 clk clock controller - - 0x00 8010 3 exti0 port a external interrupts yes (1) yes (1) 0x00 8014 4 exti1 port b external interrupts yes yes 0x00 8018 5 exti2 port c external interrupts yes yes 0x00 801c 6 exti3 port d external interrupts yes yes 0x00 8020 7 exti4 port e external interrupts yes yes 0x00 8024 8 - reserved 0x00 8028 9 - reserved 0x00 802c 10 spi end of transfer yes yes 0x00 8030 11 tim1 tim1 update/overflow/underflow/ trigger/break - - 0x00 8034 12 tim1 tim1 capture/compare - - 0x00 8038 13 tim2 tim2 update /overflow - - 0x00 803c 14 tim2 tim2 capture/compare - - 0x00 8040 15 - reserved 0x00 8044 16 - reserved 0x00 8048 17 uart1 tx complete - - 0x00 804c 18 uart1 receive register data full - - 0x00 8050 19 i2c i2c interrupt yes yes 0x00 8054 20 - reserved 0x00 8058 21 - reserved 0x00 805c 22 adc1 adc1 end of conversion/analog watchdog interrupt - - 0x00 8060 23 tim4 tim4 update/overflow - - 0x00 8064 24 flash eop/wr_pg_dis - - 0x00 8068 reserved 0x00 806c to 0x00 807c 1. except pa1 option bytes STM8S001J3 36/84 docid030584 rev 2 8 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated block of the memory. except for the rop (read-out protection) byte, ea ch option byte has to be stored twice, in a regular form (optx) and a complemented one (noptx) for redundancy. option bytes can be modified in icp mode (via swim) by access ing the eeprom address shown in table 11: option bytes below. option bytes can also be modified ?on the fly? by the application in iap mode, except the rop option that can only be modified in icp mode (via swim). refer to the stm8s flash programming manual (pm0051) and stm8 swim communication protocol and debug module user manual (um0470) for information on swim programming procedures. table 11. option bytes addr. option name option byte no. option bits factory default setting 76543210 0x4800 read-out protection (rop) opt0 rop[7:0] 0x00 0x4801 user boot code (ubc) opt1 ubc[7:0] 0x00 0x4802 nopt1 nubc[7:0] 0xff 0x4803 alternate function remapping (afr) opt2 afr7 afr6 afr5 afr4 afr3 afr2 afr1 afr0 0x00 0x4804 nopt2 nafr7 nafr6 nafr5 nafr4 nafr3 nafr2 nafr1 nafr0 0xff 0x4805 misc. option opt3 reserved hsitrim lsi _en iwdg _hw wwdg _hw wwdg _halt 0x00 0x4806 nopt3 reserved nhsi trim nlsi _en niwdg _hw nwwdg _hw nwwdg _halt 0xff 0x4807 clock option opt4 reserved ext clk ckawu sel prs c1 prs c0 0x00 0x4808 nopt4 reserved next clk nckaw usel npr sc1 npr sc0 0xff 0x4809 hse clock startup opt5 hsecnt[7:0] 0x00 0x480a nopt5 nhsecnt[7:0] 0xff table 12. option byte description option byte no. description opt0 rop[7:0] memory readout protection (rop) 0xaa: enable readout protection (w rite access via swim protocol) note: refer to the family reference manual (rm0016) section on flash/eeprom memory read out protection for details. docid030584 rev 2 37/84 STM8S001J3 option bytes 38 opt1 ubc[7:0] user boot code area 0x00: no ubc, no write-protection 0x01: pages 0 defined as ubc, memory write-protected 0x02: pages 0 to 1 defined as ubc, memory write-protected page 0 and page 1 contain the interrupt vectors. ... 0x7f: pages 0 to 126 defined as ubc, memory write-protected other values: pages 0 to 127 defined as ubc, memory-write protected. note: refer to the family reference manual (rm0016) section on flash/eeprom write protection for more details. opt2 afr[7:0] refer to the following section for alternate function remapping descriptions of bits [7:2] and [1:0] respectively. opt3 hsitrim : high-speed internal clock trimming register size 0: 3-bit trimming supported in clk_hsitrimr register 1: 4-bit trimming supported in clk_hsitrimr register lsi_en: low speed internal clock enable 0: lsi clock is not available as cpu clock source 1: lsi clock is available as cpu clock source iwdg_hw: independent watchdog 0: iwdg independent watchdog activated by software 1: iwdg independent watchd og activated by hardware wwdg_hw: window watchdog activation 0: wwdg window watchdog activated by software 1: wwdg window watchdog activated by hardware wwdg_halt: window watchdog reset on halt 0: no reset generated on halt if wwdg active 1: reset generated on halt if wwdg active opt4 extclk: external clock selection 0: external crystal connected to oscin/oscout 1: external clock signal on oscin ckawusel: auto wakeup unit/clock 0: lsi clock source selected for awu 1: hse clock with prescaler select ed as clock source for for awu prsc[1:0] awu clock prescaler 0x: 16 mhz to 128 khz prescaler 10: 8 mhz to 128 khz prescaler 11: 4 mhz to 128 khz prescaler opt5 hsecnt[7:0]: hse crystal oscillator stabilization time this configures the stabilization time. 0x00: 2048 hse cycles 0xb4: 128 hse cycles 0xd2: 8 hse cycles 0xe1: 0.5 hse cycles table 12. option byte description (continued) option byte no. description option bytes STM8S001J3 38/84 docid030584 rev 2 8.1 alternate functi on remapping bits table 13. STM8S001J3 alternate func tion remapping bits for 8-pin devices option byte number description opt2 afr7 alternate function remapping option 7 0: afr7 remapping option inactive: default alternate function (1) 1: port c3 alternate function = tim1_ch1n; port c4 alternate function = tim1_ch2n. afr6 alternate function remapping option 6 reserved. afr5 alternate function remapping option 5 reserved. afr4 alternate function remapping option 4 0: afr4 remapping option inactive: default alternate function (1) . 1: port b4 alternate function = a dc_etr; port b5 alternate function = tim1_bkin. afr3 alternate function remapping option 3 0: afr3 remapping option inactive: default alternate function (1) 1: port c3 alternate function = tli. afr2 alternate function remapping option 2 0: afr2 remapping option inactive: default alternate function (1) 1: port c4 alternate function = ain2. afr1 alternate function remapping option 1 (2) 0: afr1 remapping option inactive: default alternate function (1) 1: if afr0=0: port a3 alternate function = spi_nss if afr0=1: port a3 alternate function = uart_tx. afr0 alternate function remapping option 0 (2) 0: afr0 remapping option inactive: default alternate functions (1) 1: port c5 alternate function = ti m2_ch1; port c6 alternate function = tim1_ch1. 1. refer to the pinout description. 2. do not use more than one remapping option in the same port. docid030584 rev 2 39/84 STM8S001J3 electrical characteristics 75 9 electrical characteristics 9.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 9.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t amax (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 9.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 5 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ) . 9.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 5 . figure 5. pin loading conditions 9.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 6 . 50 pf stm8 pin electrical characteristics STM8S001J3 40/84 docid030584 rev 2 figure 6. pin input voltage 9.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 14: voltage characteristics , table 15: current characteristics , and table 16: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. device mission profile (application condit ions) is compliant with jedec jesd47 qualification standard, extended miss ion profiles are available on demand. v in stm8 pin table 14. voltage characteristics symbol ratings min max unit v ddx - v ss supply voltage (1) 1. all power (v dd ) and ground (v ss ) pins must always be connected to the external power supply -0.3 6.5 v v in input voltage on true open drain pins (2) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in docid030584 rev 2 43/84 STM8S001J3 electrical characteristics 75 table 18. operating conditi ons at power-up/power-down symbol parameter conditions min typ max unit t vdd v dd rise time rate - 2 - s/v v dd fall time rate (1) 1. reset is always generated after a t temp delay. the application must ensure that v dd is still above the minimum operating voltage (v dd min) when the t temp delay has elapsed. -2- t temp reset release delay v dd rising - - 1.7 ms v it+ power-on reset threshold -2.62.72.85v v it- brown-out reset threshold - 2.5 2.65 2.8 v v hys(bor) brown-out reset hysteresis --70-mv electrical characteristics STM8S001J3 44/84 docid030584 rev 2 9.3.1 vcap external capacitor stabilization for the main regula tor is achieved connecting an external capacitor c ext to the v cap pin. c ext is specified in table 17 . care should be taken to limit the series inductance to less than 15 nh. figure 8. external capacitor c ext 1. legend: esr is the equivalent series resist ance and esl is the equivalent inductance. 9.3.2 supply current characteristics the current consumption is measured as described in section 9.1.5: pin input voltage . total current consumption in run mode the mcu is placed under the following conditions: ? all i/o pins in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled (clock stopped by peripheral clock gating registers) except if explicitly mentioned. subject to general operating conditions for v dd and t a . 0 6 y 9 ( 6 5 5 / h d n ( 6 / & table 19. total current consumption with code execution in run mode at v dd = 5 v symbol parameter conditions typ max (1) unit i dd(run) supply current in run mode, code executed from ram f cpu = f master = 16 mhz hse user ext. clock (16 mhz) 2 2.35 ma hsi rc osc. (16 mhz) 1.7 2 f cpu = f master /128 = 125 khz hse user ext. clock (16 mhz) 0.86 - hsi rc osc. (16 mhz) 0.7 0.87 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.46 0.58 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.41 0.55 supply current in run mode, code executed from flash f cpu = f master = 16 mhz hse user ext. clock (16 mhz) 4.3 4.75 hsi rc osc.(16 mhz) 3.7 4.5 f cpu = f master = 2 mhz hsi rc osc. (16 mhz/8) (2) 0.84 1.05 f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 0.72 0.9 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.46 0.58 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.42 0.57 1. guaranteed by char acterization results. docid030584 rev 2 45/84 STM8S001J3 electrical characteristics 75 2. default clock configuration m easured with all peripherals off. table 20. total current consumption with code execution in run mode at v dd = 3.3 v symbol parameter conditions typ max (1) unit i dd(run) supply current in run mode, code executed from ram f cpu = f master = 16 mhz hse user ext. clock (16 mhz) 2 2.3 ma hsi rc osc. (16 mhz) 1.5 2 f cpu = f master /128 = 125 khz hse user ext. clock (16 mhz) 0.81 - hsi rc osc. (16 mhz) 0.7 0.87 f cpu = f master /128 = 15.625 khz hsi rc osc. (16mhz/8) 0.46 0.58 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.41 0.55 supply current in run mode, code executed from flash f cpu = f master = 16 mhz hse user ext. clock (16 mhz) 3.9 4.7 hsi rc osc. (16 mhz) 3.7 4.5 f cpu = f master = 2 mhz hsi rc osc. (16 mhz/8) (2) 0.84 1.05 f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 0.72 0.9 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.46 0.58 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.42 0.57 1. guaranteed by char acterization results. 2. default clock configuration, measured with all peripherals off. electrical characteristics STM8S001J3 46/84 docid030584 rev 2 total current consumption in wait mode table 21. total current consum ption in wait mode at v dd = 5 v symbol parameter conditions typ max (1) unit i dd(wfi) supply current in wait mode f cpu = f master = 16 mhz hse user ext. clock (16 mhz) 1.1 1.3 ma hsi rc osc. (16 mhz) 0.89 1.1 f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 0.7 0.88 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) (2) 0.45 0.57 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.4 0.54 1. guaranteed by char acterization results. 2. default clock configuration m easured with all peripherals off. table 22. total current consumption in wait mode at v dd = 3.3 v symbol parameter conditions typ max (1) unit i dd(wfi) supply current in wait mode f cpu = f master = 16 mhz hse user ext. clock (16 mhz) 1.1 1.3 ma hsi rc osc. (16 mhz) 0.89 1.1 f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 0.7 0.88 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) (2) 0.45 0.57 f cpu = f master /128 = 15.625 khz lsi rc osc. (128 khz) 0.4 0.54 1. guaranteed by char acterization results. 2. default clock configuration m easured with all peripherals off. docid030584 rev 2 47/84 STM8S001J3 electrical characteristics 75 total current consumption in active halt mode table 23. total current consumption in active halt mode at v dd = 5 v symbol parameter conditions typ max at 85 c (1) max at 125 c (1) unit main voltage regulator (mvr) (2) flash mode (3) clock source i dd(ah) supply current in active halt mode on operating mode hse user external clock (16 mhz) 1030 - - a lsi rc oscillator (128 khz) 200 260 300 power-down mode hse user external clock (16 mhz) 970 - - lsi rc oscillator (128 khz) 150 200 230 off operating mode lsi rc oscillator (128 khz) 66 85 110 power-down mode 10 20 40 1. guaranteed by char acterization results. 2. configured by the regah bit in the clk_ickr register. 3. configured by the ahalt bit in the flash_cr1 register. table 24. total current consumption in active halt mode at v dd = 3.3 v symbol parameter conditions typ max at 85 c (1) max at 125 c (1) unit main voltage regulator (mvr) (2) flash mode (3) clock source i dd(ah) supply current in active halt mode on operating mode hse user external clock (16 mhz) 550 - - a lsi rc osc. (128 khz) 200 260 290 power-down mode hse user external clock(16 mhz) 970 - - lsi rc osc. (128 khz) 150 200 230 off operating mode lsi rc osc. (128 khz) 66 80 105 power-down mode 10 18 35 1. guaranteed by char acterization results. 2. configured by the regah bit in the clk_ickr register. 3. configured by the ahalt bit in the flash_cr1 register. electrical characteristics STM8S001J3 48/84 docid030584 rev 2 total current consumption in halt mode low-power mode wakeup times table 25. total current consum ption in halt mode at v dd = 5 v symbol parameter conditions typ max at 85 c (1) max at 125 c (1) unit i dd(h) supply current in halt mode flash in operating mode, hsi clock after wakeup 63 75 105 a flash in power-down mode, hsi clock after wakeup 6.0 20 55 1. guaranteed by char acterization results. table 26. total current consumption in halt mode at v dd = 3.3 v symbol parameter conditions typ max at 85 c (1) max at 125 c (1) unit i dd(h) supply current in halt mode flash in operating mode, hsi clock after wakeup 60 75 100 a flash in power-down mode, hsi clock after wakeup 4.5 17 30 1. guaranteed by char acterization results. table 27. wakeup times symbol parameter conditions typ max (1) unit t wu(wfi) wakeup time from wait mode to run mode (3) 0 to 16 mhz - - (2) s f cpu = f master = 16 mhz. 0.56 - t wu(ah) wakeup time active halt mode to run mode. (3) mvr voltage regulator on (4) flash in operating mode (5) hsi (after wakeup) 1 (6) 2 (6) flash in power-down mode (5) 3 (6) - mvr voltage regulator off (4) flash in operating mode (5) 48 (6) - flash in power-down mode (5) 50 (6) - t wu(h) wakeup time from halt mode to run mode (3) flash in operating mode (5) 52 - flash in power-down mode (5) 54 - 1. guaranteed by design. 2. t wu(wfi) = 2 x 1/f master + 7 x 1/f cpu 3. measured from interrupt event to interrupt vector fetch. 4. configured by the regah bit in the clk_ickr register. 5. configured by the ahalt bit in the flash_cr1 register. 6. plus 1 lsi clock depending on synchronization. docid030584 rev 2 49/84 STM8S001J3 electrical characteristics 75 total current consumption and timing in forced reset state current consumption of on-chip peripherals subject to general operating conditions for v dd and t a . hsi internal rc/f cpu = f master = 16 mhz, vdd = 5 v. table 28. total current consumption and timing in forced reset state symbol parameter conditions typ max (1) unit i dd(r) supply current in reset state (2) v dd = 5 v 400 - a v dd = 3.3 v 300 - t resetbl reset release to vector fetch - - 150 s 1. guaranteed by design. 2. characterized with all i/os tied to v ss . table 29. peripheral current consumption symbol parameter typ. unit i dd(tim1) tim1 supply current (1) 1. data based on a differential i dd measurement between reset configuration and timer counter running at 16 mhz. no ic/oc programmed (no i/o pads toggling). not tested in production. 210 a i dd(tim2) tim2 supply current (1) 130 i dd(tim4) tim4 timer supply current (1) 50 i dd(uart1) uart1 supply current (1) 120 i dd(spi) spi supply current (1) 45 i dd(i2c) i2c supply current (1) 65 i dd(adc1) adc1 supply current when converting (1) 1000 electrical characteristics STM8S001J3 50/84 docid030584 rev 2 current consumption curves the following figures show the typical current consumption measured with code executing in ram. figure 9. typ. i dd(run) vs v dd , hse user external clock, f cpu = 16 mhz figure 10. typ. i dd(run) vs f cpu , hse user external clock, v dd = 5 v docid030584 rev 2 51/84 STM8S001J3 electrical characteristics 75 figure 11. typ. i dd(run) vs v dd , hsi rc osc, f cpu = 16 mhz figure 12. typ. i dd(wfi) vs. v dd hse user external clock, f cpu = 16 mhz electrical characteristics STM8S001J3 52/84 docid030584 rev 2 figure 13. typ. i dd(wfi) vs. f cpu , hse user external clock, v dd = 5 v figure 14. typ. i dd(wfi) vs v dd , hsi rc osc, f cpu = 16 mhz docid030584 rev 2 53/84 STM8S001J3 electrical characteristics 75 9.3.3 external clock sources and timing characteristics hse user external clock subject to general operating conditions for v dd and t a . figure 15. hse external clock source 9.3.4 internal clock source s and timing characteristics subject to general operating conditions for v dd and t a . table 30. hse user external clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency - 0-16mhz v hseh (1) 1. guaranteed by characterization results. oscin input pin high level voltage 0.7 x v dd -v dd + 0.3 v v v hsel (1) oscin input pin low level voltage v ss - 0.3 x v dd i leak_hse oscin input leakage current v ss < v in < v dd -1 - +1 a s , ^ , s , ^ > ?? ?vo o}l ?}? k ^ / e ( , ^ ^ d d? d ^?e?? s? electrical characteristics STM8S001J3 54/84 docid030584 rev 2 high speed internal rc oscillator (hsi) figure 16. typical hsi fr equency variation vs v dd at 4 temperatures low speed internal rc oscillator (lsi) subject to general operating conditions for v dd and t a . table 31. hsi oscillator characteristics symbol parameter conditions min typ max unit f hsi frequency - - 16 - mhz acc hsi accuracy of hsi oscillator user-trimmed with the clk_hsitrimr register for given v dd and t a conditions (1) 1. see the application note. --1.0 (2) % accuracy of hsi oscillator (factory calibrated) v dd = 5 v, t a = 25 c -2.5 - 1.5 v dd = 5 v, -40 c t a 125 c -5 - 5 t su(hsi) hsi oscillator wakeup time including calibration - - - 1.0 (2) 2. guaranteed by design. s i dd(hsi) hsi oscillator power consumption - - 170 250 (3) 3. guaranteed by characterization results. a table 32. lsi oscillator characteristics symbol parameter conditions min typ max unit f lsi frequency - - 128 - khz docid030584 rev 2 55/84 STM8S001J3 electrical characteristics 75 figure 17. typical lsi frequency variation vs v dd @ 4 temperatures t su(lsi) lsi oscillator wakeup time - - - 7 (1) s i dd(lsi) lsi oscillator power consumption - - 5 - a 1. guaranteed by design. table 32. lsi oscillator characteristics (continued) symbol parameter conditions min typ max unit electrical characteristics STM8S001J3 56/84 docid030584 rev 2 9.3.5 memory characteristics ram and hardware registers flash program memory and data eeprom general conditions: t a = -40 to 85 c . table 33. ram and hardware registers symbol parameter co nditions min unit v rm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by design. halt mode (or reset) v it-max (2) 2. refer to table 18 on page 43 for the value of v it-max . v table 34. flash program memory and data eeprom symbol parameter conditions min (1) 1. guaranteed by characterization results. typ max unit v dd operating voltage (all modes, execution/write/erase) f cpu 16 mhz 2.95 - 5.5 v t prog standard programming time (including erase) for byte/word/block (1 byte/4 bytes/64 bytes) --6.06.6ms fast programming time for 1 block (64 bytes) --3.03.3ms t erase erase time for 1 block (64 bytes) - - 3.0 3.3 ms n rw erase/write cycles (2) (program memory) 2. the physical granularity of the memory is 4 byte s, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. t a = 85 c 100 - - cycles erase/write cycles (2) (data memory) 100 k - - t ret data retention (program memory) after 100 erase/write cycles at t a = 85 c t ret = 55 c 20 - - years data retention (data memory) after 10 k erase/write cycles at t a = 85 c 20 - - data retention (data memory) after 100 k erase/write cycles at t a = 125 c t ret = 85 c 1.0 - - i dd supply current (flash programming or erasing for 1 to 128 bytes) --2.0-ma docid030584 rev 2 57/84 STM8S001J3 electrical characteristics 75 9.3.6 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor. table 35. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage v dd = 5 v -0.3 - 0.3 x v dd v v ih input high level voltage 0.7 x v dd -v dd + 0.3 v v v hys hysteresis (1) -700- mv r pu pull-up resistor v dd = 5 v, v in = v ss 30 55 80 k t r , t f rise and fall time (10% - 90%) fast i/os load = 50 pf --20 (2) ns standard and high sink i/os load = 50 pf - - 125 (2) ns i lkg input leakage current, analog and digital v ss v in v dd --1a i lkg ana analog input leakage current v ss v in v dd --250 (3) na i lkg(inj) leakage current in adjacent i/o injection current 4 ma - - 1 (3) a 1. hysteresis voltage between schmitt trigger switch ing levels. guaranteed by characterization results. 2. guaranteed by design. 3. guaranteed by char acterization results. electrical characteristics STM8S001J3 58/84 docid030584 rev 2 figure 18. typical v il and v ih vs v dd @ 4 temperatures figure 19. typical pull-up resistance vs v dd @ 4 temperatures docid030584 rev 2 59/84 STM8S001J3 electrical characteristics 75 figure 20. typical pull-up current vs v dd @ 4 temperatures 1. the pull-up is a pure resistor (slope goes through 0). table 36. output driving current (standard ports) symbol parameter conditions min max unit v ol output low level with 8 pins sunk i io = 10 ma, v dd = 5 v - 2 v output low level with 4 pins sunk i io = 4 ma, v dd = 3.3 v - 1 (1) v oh output high level with 8 pins sourced i io = 10 ma, v dd = 5 v 2.8 - v output high level with 4 pins sourced i io = 4 ma, v dd = 3.3 v 2.1 (1) - 1. guaranteed by char acterization results. table 37. output driving current (true open drain ports) symbol parameter conditions max unit v ol output low level with 2 pins sunk i io = 10 ma, v dd = 5 v 1 v i io = 10 ma, v dd = 3.3 v 1.5 (1) i io = 20 ma, v dd = 5 v 2 (1) 1. guaranteed by char acterization results. electrical characteristics STM8S001J3 60/84 docid030584 rev 2 typical output level curves figure 22 to figure 29 show typical output level curves measured with output on a single pin. figure 21. typ. v ol @ v dd = 5 v (standard ports) table 38. output driving current (high sink ports) symbol parameter conditions min max unit v ol output low level with 8 pins sunk i io = 10 ma, v dd = 5 v - 0.8 v output low level with 4 pins sunk i io = 10 ma, v dd = 3.3 v - 1.0 (1) output low level with 4 pins sunk i io = 20 ma, v dd = 5 v - 1.5 (1) v oh output high level with 8 pins sourced i io = 10 ma, v dd = 5 v 4.0 - output high level with 4 pins sourced i io = 10 ma, v dd = 3.3 v 2.1 (1) - output high level with 4 pins sourced i io = 20 ma, v dd = 5 v 3.3 (1) - 1. guaranteed by char acterization results. docid030584 rev 2 61/84 STM8S001J3 electrical characteristics 75 figure 22. typ. v ol @ v dd = 3.3 v (standard ports) figure 23. typ. v ol @ v dd = 5 v (true open drain ports) electrical characteristics STM8S001J3 62/84 docid030584 rev 2 figure 24. typ. v ol @ v dd = 3.3 v (true open drain ports) figure 25. typ. v ol @ v dd = 5 v (high sink ports) docid030584 rev 2 63/84 STM8S001J3 electrical characteristics 75 figure 26. typ. v ol @ v dd = 3.3 v (high sink ports) figure 27. typ. v dd - v oh @ v dd = 5 v (standard ports) electrical characteristics STM8S001J3 64/84 docid030584 rev 2 figure 28. typ. v dd - v oh @ v dd = 3.3 v (standard ports) figure 29. typ. v dd - v oh @ v dd = 5 v (high sink ports) docid030584 rev 2 65/84 STM8S001J3 electrical characteristics 75 figure 30. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) 9.3.7 spi serial peripheral interface unless otherwise specified, the parameters given in table 39 are derived from tests performed under ambient temperature, f master frequency and v dd supply voltage conditions. t master = 1/f master . refer to i/o port characteristics for more de tails on the input/output alternate function characteristics (nss, sck, mosi, miso). table 39. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 0 8 mhz slave mode 0 7 electrical characteristics STM8S001J3 66/84 docid030584 rev 2 figure 31. spi timing diagram - slave mode and cpha = 0 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf - 25 ns t su(nss) (1) nss setup time slave mode 4 x t master - t h(nss) (1) nss hold time slave mode 70 - t w(sckh) (1) t w(sckl) (1) sck high and low time master mode t sck /2 - 15 t sck /2 + 15 t su(mi) (1) t su(si) (1) data input setup time master mode 5 - slave mode 5 - t h(mi) (1) t h(si) (1) data input hold time master mode 7 - slave mode 10 - t a(so) (1)(2) data output access time slave mode - 3 x t master t dis(so) (1)(3) data output disable time slave mode 25 - t v(so) (1) data output valid time slave mode (after enable edge) - 65 t v(mo) (1) data output valid time master mode (after enable edge) - 30 t h(so) (1) data output hold time slave mode (after enable edge) 27 - t h(mo) (1) master mode (after enable edge) 11 - 1. values based on design simulation and/or char acterization results, and not tested in production. 2. min time is for the minimum time to drive the output and t he max time is for the maximum time to validate the data. 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z. table 39. spi characteristics (continued) symbol parameter conditions min max unit docid030584 rev 2 67/84 STM8S001J3 electrical characteristics 75 figure 32. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd. figure 33. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd. d l e 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 6 & . l q s x w & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w d 6 2 w y 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 w v x 6 , w k 6 , 0 6 % 2 8 7 0 6 % , 1 % , 7 2 8 7 / 6 % 2 8 7 / 6 % , 1 % , 7 , 1 d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 electrical characteristics STM8S001J3 68/84 docid030584 rev 2 9.3.8 i2c interface characteristics table 40. i2c characteristics symbol parameter standard mode i2c fast mode i2c (1) 1. f master , must be at least 8 mhz to achieve max fast i2c speed (400 khz) unit min (2) 2. data based on standard i2c protocol requirement, not tested in production max (2) min (2) max (2) t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low time -0 (4) 4. the device must internally provide a hold time of at least 300 ns for t he sda signal in order to bridge the undefined region of the falling edge of scl 900 (3) t r(sda) t r(scl) sda and scl rise time - 1000 - 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf docid030584 rev 2 69/84 STM8S001J3 electrical characteristics 75 figure 34. typical application with i2c bus and timing diagram 1. measurement points are made at cmos levels: 0.3 x v dd and 0.7 x v dd d l 9 6 7 $ 5 7 6 ' $ , e & e x v 9 ' ' 9 ' ' 6 7 0 6 ' $ 6 & / w i 6 ' $ w u 6 ' $ 6 & / w k 6 7 $ w z 6 & / + w z 6 & / / w v x 6 ' $ w u 6 & / w i 6 & / w k 6 ' $ 6 7 $ 5 7 5 ( 3 ( $ 7 ( ' 6 7 $ 5 7 w v x 6 7 $ w v x 6 7 2 6 7 2 3 w v x 6 7 $ 6 7 2 n ? n ? ? ? electrical characteristics STM8S001J3 70/84 docid030584 rev 2 9.3.9 10-bit adc characteristics subject to general operating conditions for v dda , f master , and t a unless otherwise specified. table 41. adc characteristics symbol parameter conditions min typ max unit f adc adc clock frequency v dda = 3 to 5.5 v 1 - 4 mhz v dda = 4.5 to 5.5 v 1 - 6 v ain conversion voltage range (1) 1. during the sample time the input capacitance c ain (3 pf max) can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s. after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t s depend on programming. -v ss -v dd v c adc internal sample and hold capacitor --3-pf t s (1) sampling time f adc = 4 mhz - 0.75 - s f adc = 6 mhz - 0.5 - t stab wakeup time from standby - - 7 - s t conv total conversion time (including sampling time, 10-b it resolution) f adc = 4 mhz 3.5 s f adc = 6 mhz 2.33 s -141/f adc table 42. adc accuracy with r ain < 10 k , v dd = 5 v symbol parameter conditions typ max (1) unit |e t | total unadjusted error (2) f adc = 2 mhz 1.6 3.5 lsb f adc = 4 mhz 2.2 4 f adc = 6 mhz 2.4 4.5 |e o | offset error (2) f adc = 2 mhz 1.1 2.5 f adc = 4 mhz 1.5 3 f adc = 6 mhz 1.8 3 |e g | gain error (2) f adc = 2 mhz 1.5 3 f adc = 4 mhz 2.1 3 f adc = 6 mhz 2.2 4 |e d | differential linearity error (2) f adc = 2 mhz 0.7 1.5 f adc = 4 mhz 0.7 1.5 f adc = 6 mhz 0.7 1.5 |e l | integral linearity error (2) f adc = 2 mhz 0.6 1.5 f adc = 4 mhz 0.8 2 f adc = 6 mhz 0.8 2 docid030584 rev 2 71/84 STM8S001J3 electrical characteristics 75 1. guaranteed by characterization results. 2. adc accuracy vs. negative injection current: inject ing negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (p in to ground) to standard analog pins which may potentially inject negative current. any positive inject ion current within the limits specified for i inj(pin) and i inj(pin) in section 9.3.6 does not affect the adc accuracy. table 43. adc accuracy with r ain < 10 k r ain , v dd = 3.3 v symbol parameter conditions typ max (1) 1. guaranteed by characterization results. unit |e t | total unadjusted error (2) 2. adc accuracy vs. negative injection current: inject ing negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (p in to ground) to standard analog pins which may potentially inject negative current. any positive inject ion current within the limits specified for i inj(pin) and i inj(pin) in section 9.3.6 does not affect the adc accuracy. f adc = 2 mhz 1.6 3.5 lsb f adc = 4 mhz 1.9 4 |e o | offset error (2) f adc = 2 mhz 1 2.5 f adc = 4 mhz 1.5 2.5 |e g | gain error (2) f adc = 2 mhz 1.3 3 f adc = 4 mhz 2 3 |e d | differential linearity error (2) f adc = 2 mhz 0.7 1.0 f adc = 4 mhz 0.7 1.5 |e l | integral linearity error (2) f adc = 2 mhz 0.6 1.5 f adc = 4 mhz 0.8 2 electrical characteristics STM8S001J3 72/84 docid030584 rev 2 figure 35. adc accuracy characteristics 1. example of an actual transfer curve. 2. the ideal transfer curve 3. end point correlation line e t = total unadjusted error: maximum deviation betw een the actual and the ideal transfer curves. e o = offset error: deviation between the firs t actual transition and the first ideal one. e g = gain error: deviation between the last ideal transition and the last actual one. e d = differential linearity error: maximum deviation between actual steps and the ideal one. e l = integral linearity error: maximum deviation between any actual transition an d the end point correlation line. figure 36. typical application with adc e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 1024 ---------------------------------------- - = 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021102210231024 (1) (2) e t e d e l (3) v dda v ssa ainx stm8 v dd i l 1a v t 0.6v v t 0.6v c adc v ain r ain 10-bit a/d conversion c ain docid030584 rev 2 73/84 STM8S001J3 electrical characteristics 75 9.3.10 emc characteristics susceptibility tests are perfor med on a sample basis during product characterization. functional ems (electromagnetic susceptibility) while executing a simple application (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the leds). ? esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. th is test conforms with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (p ositive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a function al disturbance occurs. this test conforms with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 44. ems data symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = 25 c, f master = 16 mhz, conforming to iec 61000-4-2 tbd (1) 1. data obtained with hsi clock configuration, af ter applying hw recommendations described in an2860 - emc guidelines for stm8smicrocontrollers. v eftb fast transient voltage burst limits to be applied through 100pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = 25 c, f master = 16 mhz, conforming to iec 61000-4-4 tbd (1) electrical characteristics STM8S001J3 74/84 docid030584 rev 2 electromagnetic interference (emi) based on a simple application running on the product (toggling two leds through the i/o ports), the product is monitored in terms of emission. emission tests conform to the iec 61967-2 standard for test software, board layout and pin loading. absolute maximum ratings (electrical sensitivity) based on three different tests (esd, dlu and lu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (one positive then one negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). one model can be simulated: the human body model (h bm). this test conforms to the jesd22- a114a/a115a standard. for more details, refer to the application note an1181. table 45. emi data symbol parameter conditions unit general conditions monitored frequency band max f hse /f cpu (1) 1. guaranteed by characterization results. 16 mhz/ 8 mhz 16 mhz/ 16 mhz s emi peak level v dd = 5 v t a = 25 c so8n package conforming to iec 61967-2 0.1 mhz to 30 mhz tbd tbd dbv 30 mhz to 130 mhz tbd tbd 130 mhz to 1 ghz tbd tbd emi level - tbd tbd - table 46. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. guaranteed by characterization results. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = 25c, conforming to jesd22-a114 atbdv v esd(cdm) electrostatic discharge voltage (charge device model) t a = 25c, conforming to jesd22-c101 iv tbd v docid030584 rev 2 75/84 STM8S001J3 electrical characteristics 75 static latch-up two complementary static tests are required on 10 parts to assess the latch-up performance: ? a supply overvoltage (applied to each power supply pin) ? a current injection (applied to each input, output and configurable i/o pin) is performed on each sample. this test conforms to the eia/jesd 78 ic la tch-up standard. for more details, refer to the application note an1181. table 47. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jede c criteria (international standard). lu static latch-up class t a = 25 c tbd t a = 85 c tbd package information STM8S001J3 76/84 docid030584 rev 2 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their le vel of environmental compliance. ecopack? specifications, grade definitions a nd product status are available at: www.st.com . ecopack? is an st trademark. failure analysis and guarantee the small number of pins available induces limit ations on failure analysis depth in case of isolated symptoms, typically wi th an impact lower than 0.1%. please contact your sales office for additional inform ation for any failure analysis. stmicroelectronics will make a feasibility study for investigat ion based on failure rate and symptom description prior to responsibility endorsement. 10.1 so8n package information figure 37. so8n ? 8-lead, 4.9 x 6 mm, plas tic small outline, 150 mils body width, package outline 1. drawing not to scale. table 48. so8n ? 8-lead 4.9 x 6 mm, plast ic small outline, 150 mils body width, package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 1.750 - - 0.0689 a1 0.100 - 0.250 0.0039 - 0.0098 a2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.170 - 0.230 0.0067 - 0.0091 docid030584 rev 2 77/84 STM8S001J3 package information 79 figure 38. so8n ? 8-lead 4.9 x 6 mm, plast ic small outline, 150 mils body width, package recommended footprint device marking for so8n ? 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width the following figure gives an example of topsid e marking orientation versus pin 1/ball a1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. d 4.800 4.900 5.000 0.1890 0.1929 0.1969 e 5.800 6.000 6.200 0.2283 0.2362 0.2441 e1 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0 - 8 0 - 8 l 0.400 - 1.270 0.0157 - 0.0500 l1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. values in inches are converted fr om mm and rounded to four decimal digits. table 48. so8n ? 8-lead 4.9 x 6 mm, plast ic small outline, 150 mils body width, package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. 2 b ) 3 b 9 [ package information STM8S001J3 78/84 docid030584 rev 2 figure 39. so8n ? 8-lead 4.9 x 6 mm, plast ic small outline, 150 mils body width, marking example 1. parts marked as es or e or accompanied by an engi neering sample notification letter are not yet qualified and therefore not approved for use in production. st is not responsible for any consequences resulting from such use. in no event will st be liable for t he customer using any of these engineering samples in production. st's quality department must be contac ted prior to any decision to use these engineering samples to run a qualification activity. 10.2 thermal characteristics the maximum chip junction temperature (t jmax ) must never exceed the values given in table 17: general operating conditions . the maximum chip-junction temperature, t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: ? t amax is the maximum ambient temperature in c ? ja is the package junction-to-ambient thermal resistance in c/w ? p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) ? p intmax is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. ? p i/omax represents the maximum power di ssipation on output pins, where: p i/omax = (v ol *i ol ) + ((v dd -v oh) *i oh ), and taking account of the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. 0 6 y y 6 - 5 < : : 3 u r g x f w l g h q w l i l f d w l r q $ g g l w l r q d o l q i r u p d w l r q ' d w h f r g h 8 q p d u n d e o h v x u i d f h 3 , 1 u h i h u h q f h docid030584 rev 2 79/84 STM8S001J3 package information 79 10.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. 10.2.2 selecting the product temperature range when ordering the microcontroller, the temperature range is specified in the order code (see figure 40: STM8S001J3 ordering information scheme(1) ). the following example shows how to calculate the temperature range needed for a given application. assuming the following ap plication conditions: ? maximum ambient temperature t amax = 75 c (measured according to jesd51-2) ? i ddmax = 8 ma, v dd = 5.0 v ? maximum 4 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 8 ma x 5.0 v = 40 mw p dmax = 40 mw + (8 x 0.4 x 4) mw thus: p dmax = 52.8 mw using the values obtained in section table 49.: thermal characteristics t jmax is calculated as follows for so8n package 102 c/w : t jmax = 75 c + (102 c/w x 52.8 mw) = 75 c + 5.4 c = 80.4 c. above information is within the range (-40 < t j < 130 c) table 49. thermal characteristics (1) 1. thermal resistances are based on jedec jesd51- 2 with 4-layer pcb in a natural convection environment. symbol parameter value unit ja thermal resistance junction-ambient so8n 102 c/w ordering information STM8S001J3 80/84 docid030584 rev 2 11 ordering information figure 40. STM8S001J3 ordering information scheme (1) 1. for a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the st sales office nearest to you. stm8 s 001 j 3 m 3 tr product class stm8 microcontroller pin count j = 8 pins package type m =so8n example: sub-family type 001 = low density family type s = standard temperature range 3 = -40c to 125c program memory size 3 = 8 kbyte packing no character = tube tr = tape and reel docid030584 rev 2 81/84 STM8S001J3 stm8 development tools 82 12 stm8 development tools development tools for the stm8 microcontrollers include the full-featured stice emulation system supported by a complete software tool package including c compiler, assembler and integrated development environment with high-l evel language debugger. in addition, the stm8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 12.1 emulation and in-c ircuit debugging tools the stice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effec tiveness. in addition, stm8 application development is supported by a low-cost in-circuit debugger/programmer. the stice is the fourth generation of full fe atured emulators from stmicroelectronics. it offers new advanced debugging capabilities including profilin g and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. in addition, stice offers in-circuit debugging and programming of stm8 microcontrollers via the stm8 single wir e interface module (swim), which allows non-intrusive debugging of an application while it runs on the target microcontroller. for improved cost effectiveness, stice is bas ed on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future st microcontrollers. stice key features ? occurrence and time profiling and code coverage (new features) ? advanced breakpoints with up to 4 levels of conditions ? data breakpoints ? program and data trace recording up to 128 kb records ? read/write on the fly of memory during emulation ? in-circuit debugging/prog ramming via swim protocol ? 8-bit probe analyzer ? 1 input and 2 output triggers ? power supply follower managing application voltages between 1.62 to 5.5 v ? modularity that allows users to specify the components users need to meet their development requirements and adapt to future requirements ? supported by free software tools that include integrated development environment (ide), programming software interface and assembler for stm8. stm8 development tools STM8S001J3 82/84 docid030584 rev 2 12.2 software tools stm8 development tools are supported by a complete, free software package from stmicroelectronics that includes st vis ual develop (stvd) ide and the st visual programmer (stvp) software interface. stvd provides seamless integration of the cosmic and raisonance c compilers for stm8. a free version that outputs up to kbytes of code is available. 12.2.1 stm8 toolset stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www.st.com . this package includes: st visual develop ? full-featured integrated development environment from st, featuring ? seamless integration of c and asm toolsets ? full-featured debugger ? project management ? syntax highlighting editor ? integrated programming interface ? support of advanced emulatio n features for stice such as code profiling and coverage st visual programmer (stvp) ? easy-to-use, unlimited graphical interface allowing read, write and verify the user stm8 microcontro ller flash program memory, data eeprom and option bytes. stvp also offers project mo de for saving programming configurations and automating programming sequences. 12.2.2 c and assembly toolchains control of c and assembly toolchains is seam lessly integrat ed into the stvd integrated development environment, making it possible to configure and control the building of user application directly from an easy-to-use graphical interface. available toolchains include: ? cosmic c compiler for stm8 ? one free version that outputs up to kbytes of code is available. for more information, see www.cosmic-software.com. ? raisonance c compiler for stm8 ? one free version that outputs up to kbytes of code. for more information, see www.raisonance.com. ? stm8 assembler linker ? free assembly toolchain included in the stvd toolset, which allows users to assemble and link the user application source code. 12.3 programming tools during the development cycle, stice provides in-circuit pr ogramming of the stm8 flash microcontroller on user application board via the swim protocol. additional tools are to include a low-cost in-circuit programmer as well as st socket boards, which provide dedicated programming platforms with sockets for programming the user stm8. for production environments, programmers will include a comp lete range of gang and automated programming solutions from thir d-party tool developers already supplying programmers for the stm8 family. docid030584 rev 2 83/84 STM8S001J3 revision history 83 13 revision history table 50. document revision history date revision changes 24-may-2017 1 initial release. 29-jun-2017 2 updated: section 10: package information figure 3: STM8S001J3 so8n pinout table 5: STM8S001J3 pin description table 13: STM8S001J3 alternate function remapping bits for 8-pin devices added: section : device marking for so8n ? 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width STM8S001J3 84/84 docid030584 rev 2 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2017 stmicroelectronics ? all rights reserved |
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