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0.25 db lsb, 7-bit, silicon digital attenuator, 0.1 ghz to 6.0 ghz data sheet hmc1119 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com features attenuation range: 0.25 db lsb steps to 31.75 db low insertion loss: 1.1 db at 1.0 ghz 1.3 db at 2.0 ghz typical step error: less than 0.1 db excellent attenuation accuracy: less than 0.2 db low phase shift error: 6 phase shift at 1.0 ghz safe state transitions high linearity 1 db compression (p1db): 31 dbm typical input third-order intercept (ip3): 54 dbm typical rf settling time (0.05 db final rf output): 250 ns single supply operation: 3.3 v to 5.0 v esd rating: class 2 (2 kv human body model (hbm)) 24-lead, 4 mm 4 mm lfcsp package: 16 mm 2 applications cellular infrastructure microwave radios and very small aperture terminals (vsats) test equipment and sensors if and rf designs functional block diagram figure 1. general description the hmc1119 is a broadband, highly accurate, 7-bit digital attenuator, operating from 0.1 ghz to 6.0 ghz with 31.5 db attenuation control range in 0.25 db steps. the hmc1119 is implemented in a silicon process, offering very fast settling time, low power consumption, and high esd robustness. the device features safe state transitions and is optimized for excellent step accuracy and high linearity over frequency and temperature range. the rf input and output are internally matched to 50 and do not require any external matching components. the design is bidirectional; therefore, the rf input and output are interchangeable. the hmc1119 has an on-chip regulator that can support a wide supply operating range from 3.3 v to 5.0 v with no performance change in electrical characteristics. the hmc1119 incorporates a driver that supports serial (3-wire) and parallel controls of the attenuator. the hmc1119 comes in a rohs-compliant, compact, 4 mm 4 mm lfcsp package. a fully populated evaluation board is available. 24 23 22 21 20 19 789101112 1 2 3 4 5 6 18 17 16 15 14 13 d0 v dd p/s gnd attnin gnd sernin clk le gnd attnout package base gnd gnd gnd gnd gnd gnd gnd gnd d6 d5 d4 d3 d2 d1 12962-001 serial/ parallel control 7-bit digital attenuator
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hmc1119 data sheet rev. 0 | page 2 of 15 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical specifications ............................................................... 3 ? absolute maximum ratings ....................................................... 4 ? esd caution .................................................................................. 4 ? pin configuration and function descriptions ............................. 5 ? interface schematics..................................................................... 6 ? typical performance characteristics ............................................. 7 ? insertion loss, return loss, state error, step error, and relative phase................................................................................ 7 ? input power compression and third-order intercept ............9 ? theory of operation ...................................................................... 10 ? serial control interface ............................................................. 10 ? parallel control interface .......................................................... 10 ? rf input output ......................................................................... 10 ? power-up sequence ................................................................... 10 ? applications information .............................................................. 13 ? evaluation printed circuit board ............................................ 13 ? packaging and ordering information ......................................... 15 ? outline dimensions ................................................................... 15 ? ordering guide .......................................................................... 15 ? revision history 9/2016revision 0: initial version
data sheet hmc1119 rev. 0 | page 3 of 15 specifications electrical specifications v dd = 3.3 v to 5.0 v, t a = 25c, 50 system, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit frequency range 0.1 6.0 ghz insertion loss 0.1 ghz to 1.0 ghz 1.1 1.8 db 0.1 ghz to 2.0 ghz 1.3 2.0 db 0.1 ghz to 4.0 ghz 1.6 2.3 db 0.1 ghz to 6.0 ghz 2.0 2.8 db attenuation 0.2 ghz to 6.0 ghz range delta between minimum and maximum attenuation states 31.75 db accuracy referenced to insertion loss; all attenuation states ?(0.05 + 4% of attenuation setting) +(0.05 + 4% of attenuation setting) db step error all attenuation states 0.1 db overshoot between all attenuation states 0.1 db return loss all attenuation states attnin, attnout 1.0 ghz 23 dbm 2.0 ghz 22 dbm 4.0 ghz 19 dbm 6.0 ghz 17 dbm relative phase 1.0 ghz 6 degrees 2.0 ghz 18 degrees 4.0 ghz 38 degrees 6.0 ghz 58 degrees switching characteristics t rise , t fall 10%/90% rf output 60 ns t on , t off 50% ctl to 10%/90% rf output 150 ns settling time 50% ctl to 0.05 db final rf output 250 ns 50% ctl to 0.10 db final rf output 200 ns input linearity all attenuation states, 0.2 ghz to 6 ghz 0.1 db compression (p0.1db) 30 dbm 1 db compression (p1db) 31 dbm input third-order intercept (ip3) two-tone input power = 16 dbm/tone, ?f = 1 mhz 54 dbm supply current (i dd ) v dd = 3.3 v 0.3 ma v dd = 5.0 v 0.6 ma control voltage threshold <1 a typical low v dd = 3.3 v 0 0.5 v v dd = 5.0 v 0 0.8 v high v dd = 3.3 v 2.0 3.3 v v dd = 5.0 v 3.5 5.0 v recommended operating conditions supply voltage range (v dd ) 3.0 5.4 v digital control voltage range for p/s, clk, sernin, le, d0 to d6 pins 0 v dd v rf input power all attenuation states, t case = 85c 24 dbm case temperature (t case ) ?40 +85 c
hmc1119 data sheet rev. 0 | page 4 of 15 absolute maximum ratings table 2. parameter rating rf input power (t case = 85c) 25 dbm digital control inputs (p/s, clk, sernin, le, d0 to d6) ?0.3 v to v dd + 0.5 v supply voltage (v dd ) ?0.3 v to +5.5 v continuous power dissipation (p diss ) 0.31 w thermal resistance (at maximum power dissipation) 156c/w temperature channel temperature 135c storage ?65c to +150c maximum reflow temperature 260c (msl3 rating) esd sensitivity (hbm) 2 kv (class 2) stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
data sheet hmc1119 rev. 0 | page 5 of 15 pin configuration and fu nction descriptions figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic description 1, 19 to 24 d0, d6 to d1 parallel control voltage inputs. these pins attain the re quired attenuation (see table 5). there is no internal pull-up or pull-down on these pins; therefore, these pins must always be kept at a valid logic level (v ih or v il ) and must not be left floating. 2 v dd supply voltage pin. 3 p/s parallel/serial control input. there is no internal pull-up or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (v ih or v il ) and must not be left floating. for parallel mode, set pin 3 to low; for serial mode, set pin 3 to high. 4, 6 to 13, 15 gnd ground. the package bottom has an exposed metal pad that must connect to the printed circuit board (pcb) rf/dc ground. see figure 4 for the gnd interface schematic. 5 attnin attenuator input. this pin is dc-coupled and matched to 50 . a blocking capacitor is required. select the value of the capacitor based on the lowest frequency of operation. see figure 5. 14 attnout attenuator output. this pin is dc-coupled and matched to 50 .a blocking capacitor is required. select the value of the capacitor based on the lowest frequency of operation. see figure 5. 16 le serial/parallel interface latch enable input. there is no internal pull-up or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (v ih or v il ) and must not be left floating. see the theory of operation section for more information. 17 clk serial interface clock input. there is no internal pull-u p or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (v ih or v il ) and must not be left floating. see the theory of operation section for more information. 18 sernin serial interface data input. there is no internal pull-u p or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (v ih or v il ) and must not be left floating. see the theory of operation section for more information. epad exposed pad. the exposed pad must be connected to rf/dc ground. d0 v dd p/s gnd a ttnin gnd sernin notes 1. the exposed pad and gnd pins must be connected to rf dc ground. clk le gnd attnout gnd gnd gnd gnd gnd gnd gnd d6 d5 d4 d3 d2 d1 24 23 22 21 20 19 789101112 1 2 3 4 5 6 18 17 16 15 14 13 12962-002 hmc1119 top view (not to scale)
hmc1119 data sheet rev. 0 | page 6 of 15 interface schematics figure 3. d0 to d6 interface figure 4. gnd interface figure 5. attin and attout interface figure 6. p/s, le, clk, and sernin interface v dd d0 to d5 12962-021 gnd 12962-022 at tin, a ttout 12962-023 v dd p/s, le, clk, sernin 12962-024
data sheet hmc1119 rev. 0 | page 7 of 15 typical performance characteristics insertion loss, return loss, state erro r, step error, and relative phase figure 7. insertion loss vs. frequency at various temperatures figure 8. input return loss (major states only) figure 9. state error vs. attentuation state, 0.1 ghz to 0.5 ghz figure 10. normalized attenuation (major states only) figure 11. output return loss (major states only) figure 12. state error vs. attentuation state, 1 ghz to 6 ghz ?4 ?3 ?2 ?1 0 0123456 +85c +25c ?40c insertion loss (db) frequency (ghz) 12962-003 0123456 frequency (ghz) ?50 ?40 ?30 ?20 ?10 0 input return loss (db) il 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db 12962-004 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 04 32 8 1216202428 st a te error (db) attenuation state (db) 100mhz 200mhz 400mhz 500mhz 12962-007 0123456 frequency (ghz) ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 normalized a ttenu a tion (db) 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db 12962-005 0123456 frequency (ghz) ?60 ?50 ?40 ?30 ?20 ?10 0 output return loss (db) il 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db 12962-006 ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1 st a te error (db) 04 32 8 1216202428 attenuation state (db) 1ghz 2ghz 3ghz 4ghz 5ghz 6ghz 12962-009
hmc1119 data sheet rev. 0 | page 8 of 15 figure 13. state error vs. frequency, major states only figure 14. relative phase vs. frequency, major states only figure 15. step error vs. frequency, major states only ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 st a te error (db) 0123456 frequency (ghz) 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db 12962-008 ?60 ?40 ?20 0 20 40 60 80 rel a tive phase (deg) frequency (ghz) 0123456 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db 12962-011 0123456 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 step error (db) frequency (ghz) 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db 12962-010
data sheet hmc1119 rev. 0 | page 9 of 15 input power compression and third-order intercept figure 16. p1db vs. frequency at various temperatures, minimum attentuation state, 0.05 ghz to 1 ghz figure 17. p0.1db vs. frequency at various temperatures, minimum attentuation state, 0.05 ghz to 1 ghz figure 18. ip3 vs. frequency at various temperatures, minimum attentuation state, 0.1 ghz to 1 ghz figure 19. p1db vs. frequency at various temperatures, minimum attentuation state, 0.05 ghz to 6 ghz figure 20. p0.1db vs. frequency at various temperatures, minimum attentuation state, 0.05 ghz to 6 ghz figure 21. ip3 vs. frequency at various temperatures, minimum attentuation state, 0.1 ghz to 6 ghz 15 20 25 30 35 40 p1db (dbm) frequency (ghz) +85c +25c ?40c 0 0.2 0.4 0.6 0.8 1.0 12962-012 15 20 25 30 35 40 p0.1db (dbm) frequency (ghz) 0 0.2 0.4 0.6 0.8 1.0 +85c +25c ?40c 12962-013 frequency (ghz) 30 40 50 60 70 ip3 (dbm) 0.2 0 0.4 0.6 0.8 1.0 +85c +25c ?40c 12962-014 15 20 25 30 35 40 p1db (dbm) frequency (ghz) 0123456 +85c +25c ?40c 12962-015 15 20 25 30 35 40 p0.1db (dbm) frequency (ghz) 0123456 +85c +25c ?40c 12962-016 frequency (ghz) 30 40 50 60 70 ip3 (dbm) 0 1 23 4 56 +85c +25c ?40c 12962-017
hmc1119 data sheet rev. 0 | page 10 of 15 theory of operation the hmc1119 incorporates a 7-bit fixed attenuator array that offers an attenuation range of 0.25 db to 31.75 db, with 0.25 db steps. an integrated driver provides both serial and parallel mode control of the attenuator array (see figure 22). the hmc1119 can be in either serial or parallel mode control by setting the p/s pin to high or low, respectively (see table 4). the 7-bit data, loaded in either serial or parallel mode, then latches with the control signal, le, to determine the attenuator value. table 4. mode selection table 1 p/s pin state control mode low parallel high serial 1 the p/s pin must always be kept at a valid logic level (v ih or v il ) and must not be left floating. serial control interface the hmc1119 utilizes a 3-wire serial to parallel (spi) configuration, as shown in the serial mode timing diagram (see figure 23): serial data input (serin), clock (clk), and latch enable (le). the serial control interface activates when the p/s pin is set to high. in serial mode, the 7-bit serin data is clocked msb first on rising clk edges into the shift register; then, le must be toggled high to latch the new attenuation state into the device. the le must be set low to clock a set of 7-bit data into the shift register because clk is masked to prevent the attenuator value from changing if le is kept high. in serial mode operation, both the serial control inputs (le, clk, sernin) and the parallel control inputs (d0 to d6) must always be kept at a valid logic level (v ih or v il ) and must not be left floating. it is recommended to connect the parallel control inputs to ground and to use pull-down resistors on all serial control input lines if the device driving these input lines goes high impedance during hibernation. parallel control interface the parallel control interface has seven digital control input lines (d6 to d0) to set the attenuation value. d6 is the most significant bit (msb) that selects the 16 db attenuator stage, and d0 is the least significant bit (lsb) that selects the 0.25 db attenuator stage (see figure 22). in parallel mode operation, both the serial control inputs (le, clk, sernin) and the parallel control inputs (d0 to d6) must always be kept at a valid logic level (v ih or v il ) and must not be left floating. it is recommended to connect the serial control inputs to ground and to use pull-down resistors on all parallel control input lines if the device driving these input lines goes high impedance during hibernation. setting p/s to low enables parallel mode. there are two modes of parallel operation: direct parallel mode and latched parallel mode. direct parallel mode for direct parallel mode, the latch enable (le) pin must be kept high. change the attenuation state using the control voltage inputs (d0 to d6) directly. this mode is ideal for manual control of the attenuator and using hardware, switches, or a jumper. latched parallel mode the latch enable (le) pin must be low when changing the control voltage inputs (d0 to d6) to set the attenuation state. when the desired state is set, le must be toggled high to transfer the 7-bit data to the bypass switches of the attenuator array, then toggled low to latch the change into the device (see figure 24). rf input output the attenuator in the hmc1119 is bidirectional; the attnin and attnout pins are interchangeable as the rf input and output ports. the attenuator is internally matched to 50 at both input and output; therefore, no external matching components are required. the rf pins are dc-coupled; therefore, dc blocking capacitors are required on rf lines. power-up sequence the ideal power-up sequence is as follows: 1. power up gnd. 2. power up v dd . 3. power up the digital control inputs (the relative order of the digital control inputs is not important). 4. power up the rf input. for latched parallel mode operation, le must be toggled. the relative order of the digital inputs is not important as long as the inputs are powered up after gnd and v dd . power-up states the logic state of the device is at maximum attenuation when, at power up, le is set to low. the attenuator latches in the desired power-up state approximately 200 ms after power up.
data sheet hmc1119 rev. 0 | page 11 of 15 figure 22. attenuator array functional block diagram table 5. truth table digital control input 1 attenuation state (db) d6 d5 d4 d3 d2 d1 d0 low low low low low low low 0 (reference) low low low low low low high 0.25 low low low low low high low 0.5 low low low low high low low 1.0 low low low high low low low 2.0 low low high low low low low 4.0 low high low low low low low 8.0 high low low low low low low 16.0 high high high high high high high 31.75 1 any combination of the control voltage input states shown in ta ble 5 provides an attenuation equal to the sum of the bits sele cted. sernin d0 d q d1 d2 d3 d4 d5 d6 clk p/s select p/s le rf input rf output d q d q d q d q d q d q 7-bit latch 0.25db 0.5db 1db 2db 4db 8db 16db 12962-018
hmc1119 data sheet rev. 0 | page 12 of 15 figure 23. serial control timing diagram figure 24. latched parallel mode timing diagram table 6. timing specifications parameter description min typ max unit t sck minimum serial period, see figure 23 70 ns t cs control setup time, see figure 23 15 ns t ch control hold time, see figure 23 20 ns t ln le setup time, see figure 23 15 ns t lew minimum le pulse width, see figure 24 10 ns t les minimum le pulse spacing, see figure 23 630 ns t ckn serial clock hold time from le, see figure 23 0 ns t ph hold time, see figure 24 10 ns t ps setup time, see figure 24 2 ns serin clk p/s le x x d6 msb [first in] t cs t ch t sck t les t ckn t lew t ln d5 d4 d3 d2 d1 d0 x d[6:0] next word x msb [first in] 12962-019 le d6 to d0 p/s xx x t lew t ph t ps d[6:0] paralle l control 12962-020
data sheet hmc1119 rev. 0 | page 13 of 15 applications information evaluation printed circuit board the schematic of the evaluation board, ev2hmc1119lp4m , is shown in figure 25. the pcb is four-layer material with a copper thickness of 0.7 mils on each layer. each copper layer is separated with a dielectric material. the top dielectric material is 10-mil ro4350 with a typical dielectric constant of 3.48. the middle and bottom dielectric materials are fr-4 material, used for mechanical strength and to meet the overall board thickness of approximately 62 mils, which allows sma connectors to be slipped in at board edges. all rf and dc traces are routed on the top copper layer. the rf transmission lines are designed using coplanar waveguide model (cpwg) with a width of 18 mils, spacing of 17 mils, and dielectric thickness of 10 mils to maintain 50 characteristic impedance. the inner and bottom layers are solid ground planes. for optimal electrical and thermal performance, an ample number of vias are populated around the transmission lines and under the package exposed pad. the evaluation board layout serves as a recommend- ation for the optimal performance on both electrical and thermal aspects. figure 25. ev2hmc1119lp4m evaluation pcb table 7. bill of materials item value 1 description manufacturer 2 j1, j2 pcb mount sma connector j3 18-pin dc connector tp1, tp2 through hole mount test point c1, c3 100 pf capacitor, 0402 package c6 10 f capacitor, 0603 package c7 1000 pf capacitor, 0402 package r1 to r11 0 resistor, 0402 package r12 to r25 100 k resistor, 0402 package sw1, sw2 spdt four-position dip switch u1 hmc1119 digital attenuator analog devices, inc. pcb 3 600-00963-00 evaluation pcb ev2hmc1119lp4m 4 from analog devices 1 blank cells in the value column indicate that there is no specific value recommendation for the listed component. 2 blank cells in the manufacturer column indicate that there is no specific manufacturer recommend ation for the listed component . 3 circuit board material is arlon 25fr. 4 reference this number when ordering the full evaluation pcb. see the ordering guide section. 12962-026
hmc1119 data sheet rev. 0 | page 14 of 15 figure 26. applications circuit 12962-027
data sheet hmc1119 rev. 0 | page 15 of 15 packaging and ordering information outline dimensions figure 27. 24-lead lead frame chip scale package [lfcsp] 4 mm 4 mm body and 0.90 mm package height (cp-24-16) dimensions shown in millimeters ordering guide model 1 temperature range msl rating 2 package description package option branding 3 hmc1119lp4me ?40c to +85c msl3 24-lead lead frame chip scale package [lfcsp] cp-24-16 xxxx 1119h HMC1119LP4METR ?40c to +85c msl3 24-lead lead frame chip scale package [lfcsp] cp-24-16 xxx x 111 9 h ev2hmc1119lp4m evaluation board 1 hmc1119lp4me and HMC1119LP4METR are rohs compliant parts. 2 see the absolute maximum ratings section. 3 xxxx is the 4-digit lot number. 0.50 bsc 0.50 0.40 0.30 compliant to jedec standards mo-220-vggd-8. bottom view top view 4.10 4.00 sq 3.90 seating plane 1.00 0.90 0.80 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 pin 1 indicator 1 24 7 12 13 18 19 6 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 01-13-2015-a 0.30 0.25 0.18 p i n 1 i n d i c a t o r 0.20 min 2.85 2.70 sq 2.55 exposed pad pkg-000000 ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12962-0-9/16(0) www.analog.com/hmc1119

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