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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr21b1411 enhanced 1-ch full-speed usb uart july 2016 rev. 1.2.0 general description the xr21b1411 (b1411) is an enhanced universal asynchronous receiver and transmitter (uart) with a usb interface. the usb in terface is fully compliant to full speed usb 2.0 specification that supports 12 mbps usb data transfer rate. the usb interface also supports usb suspend, resume and remote wakeup operations. the b1411 operates from an internal clock that is programmable to 6, 12, 24 or 48 mhz. therefore, no external crystal / oscillator is required as in previous generation uarts. with the fractional baud rate generator, any baud rate up to 12 mbps can be accurately generated using the internal clock. the large 128-byte tx fifo and 384-byte rx fifo of the b1411 help to optimize the overall data throughput for various applications. the automatic transceiver direction contro l feature simplifies both the hardware and software for half-duplex rs-485 applications. if required, th e multidrop (9-bit) mode with automatic half-duplex transceiver control feature further simplifies typi cal multidrop rs-485 applications. the vendor id, product id, bus-powered mode, self- powered mode, remote wakeup support or maximum power consumption values, as well as default baud rate settings can be programmed using the on-board otp through the usbd+ / usbd- pins. the b1411 operates from a single 5v power supply and is available in a 16-pin qfn package. whql certified software drivers for windows 2000, xp, vista, 7, 8, 8.1, 10 and ce, as well as linux and mac are supported for the xr21b1411. applications ? portable appliances ? external converters (dongles) ? battery-operated devices ? cellular data devices ? factory automation and process controls ? industrial applications features ? 15kv hbm esd on usbd+/usbd- ? usb 2.0 compliant, full-speed (12 mbps) supports usb suspend, resume and remote wakeup operations ? unique preprogrammed usb serial number ? enhanced uart features data rates up to 12 mbps fractional baud rate generator 128 byte tx fifo 384 byte rx fifo 7, 8 or 9 data bits 1 or 2 stop bits odd, even, mark, space or no parity automatic hardware (rts/cts or dtr/dsr) flow control automatic software (xon/xoff) flow control multidrop mode auto rs-485 half-duplex control half-duplex mode selectable gpio or modem i/o ? internal 48 mhz clock with clock divisors programmable down to 6 mhz ? single 5v power supply ? 5v tolerant inputs ? 16-pin qfn package ? virtual com port whql/hck windows certified drivers windows 2000, xp, vista, 7, 8, 8.1 and 10 windows ce 4.2, 5.0, 6.0, 7.0 ? linux, mac drivers
f igure 1. xr21b1411 b lock d iagram usb slave interface 128-byte tx fifo gpios/ modem io tx rx internal programmable oscillator (6mhz ? 48mhz) usbd+ usbd- 384-byte rx fifo gpio5/rts#/rs485 gpio4/cts# gpio3/dtr# gpio2/dsr# gpio1/cd# gpio0/ri# uart fractional brg internal status and control registers 5v vcc gnd 1.6v-3.6v vio_ref otp usb descriptors xr21b1411 2 enhanced 1-ch full-speed usb uart rev. 1.2.0 f igure 2. p in o ut d iagram 16-pin qfn usbd+ vcc usbd- gnd nc lowpower gpio5/rts#/rs485 gpio4/cts# gpio2/dsr# gpio3/dtr# gpio1/cd# gpio0/ri#/rwk# 1 2 3 4 5678 16 1315 14 12 11 10 9 vbus_sense vio_ref rx tx p art n umber p ackage o perating t emperature r ange d evice s tatus xr21b1411il16-f 16-pin qfn -40c to +85c active XR21B1411IL16TR-F 16-pin qfn -40c to +85c active xr21b1411il16mtr-f 16-pin qfn -40c to +85c active ordering information n ote : tr = tape and reel, mtr = mini tape and reel, f = green / rohs
xr21b1411 3 rev. 1.2.0 enhanced 1-ch full-speed usb uart pin descriptions pin description n ame 16-qfn p in # t ype d escription uart signals rx 10 i uart receive data. this pin has a programmable pull-up or pull-down resistor which may be enabled by otp programming. pull-up resistor will be disabled without valid voltage on vio_ref pin. tx 9 o uart transmit data. gpio0/ri#/rwk# 8 i/o general purpose i/o or uart ring-indicator input (active low) or remote wakeup input. this pin has a programmable pull-up or pull- down resistor which may be enabled by otp programming. this pin may also be used by any device to signal the usb host to exit the sus - pend state. see ?section 1.3.10, usb suspend? on page 9. gpio1/cd# 7 i/o general purpose i/o or uart carrier-detect input (active low). this pin has a programmable pull-up or pull-down resistor which may be enabled by otp programming. gpio2/dsr# 6 i/o general purpose i/o or uart data-set-ready input (active low). see ?section 1.3.5.2, automatic dtr/dsr hardware flow con - trol? on page 8. this pin has a programmable pull-up or pull-down resistor which may be enabled by otp programming. gpio3/dtr# 5 i/o general purpose i/o or uart data-terminal-ready output (active low). see ?section 1.3.5.2, automa tic dtr/dsr hardware flow control? on page 8. this pin has a programmable pull-up or pull- down resistor which may be enabled by otp programming. this bit will be automatically configured as an output when using the standard cdc- acm driver. gpio4/cts# 4 i/o general purpose i/o or uart clear-to-send input (active low). see ?section 1.3.5.1, automatic rts/cts hardware flow con - trol? on page 8. this pin has a programmable pull-up or pull-down resistor which may be enabled by otp programming. gpio5/rts#/rs485 3 i/o general purpose i/o or uart reques t-to-send output (active low) or auto rs-485 half-dupl ex control. see ?section 1.3.5. 1, automatic rts/cts hardware flow control? on page 8 or ?section 1.3.6, auto rs-485 half -duplex control? on page 8 . this pin has a programmable pull-up or pull-down resistor which may be enabled by otp programming. this bit will be automatically configured for hard - ware flow control as rts# output when using the standard cdc-acm driver. usb interface signals usbd+ 15 i/o usb port differential data positive input. this pin has internal pull-up resistor compliant to usb 2.0 specification. the esd protection on this pin is +/-15 kv hbm. usbd- 14 i/o usb port differential data negative input. the esd protection on this pin is +/-15 kv hbm.
xr21b1411 4 enhanced 1-ch full-speed usb uart rev. 1.2.0 n otes : 1. pin type: i=input, o=output, i/o= input/ output, pwr=power, od=o utput open drain. 2. io pins are undefined during usb bus reset and por (pow er on reset). to ensure defined state during reset conditions, use a weak external resi stor to pull to the desired state. miscellaneous signals lowpower 1 o the lowpower pin will be asserted when ever it is not safe to draw the amount of current requested from vbus in the device maximum power field of the configuration descriptor. the lowpower pin will behave differently for a low power device and a high power device. low-power device (<= 1 unit load or 100 ma i.e. bmaxpower <= 0x32): lowpower pin is asserted when the usb uart is in suspend mode. high-power deivce (bmaxpower > 0x32): lowpower pin is asserted when the usb uart is in suspend mode or when it is not yet configured. the lowpower pin will be de-asserted wh enever it is safe to draw the amount of current from vbus reques ted in the device maximum power field. the default active low polarity may be changed via the otp. connect this pin to vio_ref or to ground through a weak (10k) pull-up or pull- down resistor to match the polarity of the asserted state in high power applications. in low power applications, no external resistor is required. vbus_sense 11 i vbus sense input. this pin is used to disable the pull-up resistor on the usbd+ signal when vbus is not pres ent in self-powered mode. in self- powered mode, the vbus from the u sb connector should be connected to this pin through a voltage divider circuit (vbus = 5v), such that vbus_sense = vio_ref, using large resistance values to minimize power. it should also be decoupled by a 0.1 uf capacitor. this feature must be enabled via the otp. in bus-powered mode, this pin is ignored but should be tied to a defined logic state. nc 2 no connect power / ground signals vio_ref 12 pwr reference voltage for the modem i/o signals. the voltage range for vio_ref is + 1.6v to + 3.6v. vcc 16 pwr 5v power supply. input voltage rang e for vcc is + 4.4v to + 5.25v. gnd 13 pwr power supply common, ground. gnd center pad pwr the center pad on the back side of the qfn package is metallic and should be connected to gnd on the pcb. the thermal pad size on the pcb should be the approximate size of this center pad and should be solder mask defined. the solder mask opening should be at least 0.0025" inwards from the edge of the pcb thermal pad. pin description n ame 16-qfn p in # t ype d escription
xr21b1411 5 rev. 1.2.0 enhanced 1-ch full-speed usb uart 1.0 functional descriptions 1.1 usb interface the usb interface of the b1411 is compliant with the usb 2.0 full-speed specifications. the b1411 uses the following set of parameters: x 1 control endpoint endpoint 0 as outlined in the usb specifications x 1 configuration is supported x 2 interfaces for the uart channel single interrupt endpoint bulk-in and bulk-out endpoints 1.1.1 usb vendor id exar?s usb vendor id is 0x04e2. this is the default ve ndo r id that is used for the b1411. this value can be changed by programming the internal otp via the usb link. 1.1.2 usb product id the default usb product id for the b1411 is 0x1411. th is value can be changed by programming the internal otp via the usb link. note that exar?s custom drivers for all windows os require that the product id be an odd number for the b1411 device for proper identification of the device. 1.2 usb device driver the b1411 device can be used with either a standard cdc-acm driver or a custom driver. when the cdc- acm driver is used, the driver has no capability to read or write the b 1411 device registers. because of this, the b1411 device is initialized to the settings in table 1 . with a custom driver, all gpi os default in hardware to inputs but these settings may be modified by the custom driver. t able 1: b1411 r egister d efaults with cdc-acm d river r egister v alue n otes flow_control 0x001 hardware flow control gpio_mode 0x001 rts / cts flow control gpio_direction 0x008 gpio3/dtr# configured as an output gpio_int_mask 0x030 gpio0/ri#, gpio1/cd# and gpio2/dsr# are interr upt sensitive, i.e. can cause a usb interrupt to be generated these default settings can be overridden by pr ogramming the otp via the address value feature. although there is no abilit y to read / wri te registers when using the cdc-acm driver, basic uart functions, including setting baud rate, character format and sending line break is supported by the cdc driver. refer to the 4 cdc_acm_if usb control commands listed in table 2 . if a custom driver is used, the custo m _driver_active bit should be immediately set to ?1? by the driver. once the custom_driver_active bit is set, the custom driver can use standard cdc-acm commands without configuring the device to the def ault register settings used with the cdc-acm driver. any changes to the register settings for the gpios and flow control will specifically need to be configured by the driver. 1.3 uart the uart can be configured via usb control transfers fr om th e usb host. the uart transmitter and receiver sections are described separately below.
xr21b1411 6 enhanced 1-ch full-speed usb uart rev. 1.2.0 1.3.1 transmitter the transmitter consists of a 128-byte tx fifo and a tr ansmit shift register (tsr). once a bulk-out packet has been received and the crc has been validated, the data bytes in that packet are written into the tx fifo. data from the tx fifo is transferred to the tsr when the tsr is idle or has completed sending the previous data byte. the tsr shifts the data out onto the tx output pin at the selected baud rate. the transmitter sends the start bit followed by the data bits (starting with the l sb), inserts the proper parity-bit if enabled, and adds the stop-bit(s). the transmitter can be configured for 7 or 8 data bits with or without parity or 9 data bits without parity. if 7 or 8 bit data with parity is sele ct ed, the tx fifo contains 8 bits data and the parity bit is automatically generated and tr ansmitted. if 9 bit data is selected, parity cann ot be generat ed. the 9th bit will always be a ?0? unless the wide mode is enabled. 1.3.1.1 wide mode transmit when 9 bit data and the wide mode are both selected, 2 b ytes from the usb host are used to form 9 bit data which is serialized and transmitted on t he uart tx pin. the first byte receiv ed into the tx fifo forms the first 8 bits of data and the least significant bit of the second byte forms the 9th data bit. the remaining 7 bits of the second byte are discarded. the wide mode can be e nabled via the wide_mode re gister at address 0xd02. 1.3.2 receiver the receiver consists of a 384-byte rx fifo and a receiv e shif t register (rsr). data that is received in the rsr via the rx pin is transferred into the rx fifo. data from the rx fifo is sent to the usb host in response to a bulk-in request. depending on the mode, error / status information for that data character may or may not be stored in the rx fifo with the data. 1.3.2.1 normal receive operation with 7 or 8-bit data data that is received is stor ed in the rx fifo. any parity, framing or overrun error or break status information related to the data is discarded. receive data format is shown in figure 3 . 1.3.2.2 normal receive operation with 9-bit data the first 8 bits of data received is stored in the rx fifo. the 9th bit as well as any parity, framing or overrun error or break status information related to the data is discarded. f igure 3. 1 st byte 7, 8, or 9 bit data 7 6 5 4 3 2 1 0 7 = ?0? in 7 bit mode n ormal o peration r eceive d ata f ormat 1.3.2.3 wide mode operation with 7 or 8-bit data two bytes of data are loaded into the rx fifo for each by te o f data received. the first byte is the received data. the second byte consists of the error bits and br eak status. wide mode receive data format is shown in figure 4 . 1.3.2.4 wide mode operation with 9-bit data two bytes of data are loaded into the rx fifo for each byte of data received. the first byte is the first 8 bits of the received data. the 9th bit received is stored in the bit 0 of the second byte. the parity bit is not received / checked. the remainder of the 2nd byte consists of the framing and overrun error bits and break status.
xr21b1411 7 rev. 1.2.0 enhanced 1-ch full-speed usb uart f igure 4. w ide m ode r eceive d ata f ormat 1st byte 2nd byte 9 bit mode 7 6 5 4 3 2 1 0 x x x x o f b p 1st byte b = break f = framing error o = overrun error 2nd byte 7 or 8 bit mode p = parity error (= ?0? if not enabled) 7 = ?0? in 7 bit mode x = ?0? 7 6 5 4 3 2 1 0 x x x x o f b 8b = break f = framing error o = overrun error x = ?0? error flags are also available from the error_status register and the interrupt packet, however these flags are historical flags indicating that an error has occurred since the previous request. therefore, no conclusion can be drawn as to which specific byte(s) may have contained an actual error in this manner. 1.3.3 rx fifo low latency in normal operation all bulk -in transfers will be of maxpacketsize ( 64) bytes to improv e throughpu t and to minimize host processing. when th ere are 64 bytes of da ta in the rx fifo, th e b1411 will acknowledge a bulk-in request from the host and transfer the data packe t. if there is less than 64 bytes in the rx fifo, the b1411 may nak the bulk-in request indicating that data is not ready to transfer at that time. however, if there is less than 64 bytes in the rx fifo and no data has bee n received for more than 3 character times, the b1411 will acknowledge the bulk-i n request and transfer any data in the rx fifo to the usb host. in some cases, especially whe n the baud rate is low, this increases latency unacceptably. the b1411 has a low latency register bit that will caus e the b1411 to immediately transfer an y received data in the rx fifo to the usb host, i.e. it will not wait for 3 character times. the custom driver can automatically set the rx_fifo_low_latency register bit to force the b1411 to be in the low latency mode, or the user may manually set this bit. with the cdc-acm driver, the lo w latency mode is automatically set whenever the baud rate is set to a value of less than 40961 bps using the cdc_acm_if_set_line_coding command. 1.3.4 gpio the uart has 6 gpios. by hardware default the gp ios are configured as inputs but may be modified by a custom driver. however, they can also be configured to add additional features such as auto rts/cts flow control, auto dtr/dsr flow control or auto rs-485 ha lf duplex control. both gpio modes 3 and 4 may be used to automatically assert gpio5 as auto rs-485 half duplex control. see table 7 for the register control and details of gpio modes. note that settings in the gpio mo de register should coordinate with settings in the flow control mode register described in ?section 1.3.5, flow control? on page 7 . not all combinations of these two registers will be valid. see ?section 1.3.7, multidrop mode wit h address matching? on page 9 for more details regarding rx address matching. 1.3.5 flow control the b1411 can perform both hardware and software flow co ntrol. sof tware flow cont rol is selected by flow control mode 2. hardware flow control can either be rts/cts or dtr/dsr controlled and is selected by flow control mode 1. see table 6 for the register control and details of fl ow control modes. the following sections describe the three types of flow control which may be used.
xr21b1411 8 enhanced 1-ch full-speed usb uart rev. 1.2.0 1.3.5.1 automatic rts/cts hardware flow control gpio5 and gpio4 of the uart channel can be enabled as the rts# and cts# signals for auto rts/cts flow control when gpio_mode[2:0] = ?0 01?. automatic rts flow control is used to prevent data overrun errors in local rx fifo by de-asserting the rts signal to the remote uart. when there is room in the rx fifo, the rts pin will be re-asserted. automatic cts flow control is used to prevent data overrun to the remote rx fifo. the cts# input is monitored to suspend/restart the local transmitter (refer to figure 5 ): f igure 5. a uto rts and cts f low c ontrol o peration t ra n s m itte r a u to c t s m onitor receiver fifo trigger reached a u to r t s trigger level remote uart uartb rtsa# ctsb# txb rxa on on off on on off 1 2 3 4 1) co m port opened, rx fifo em pty, rtsa# output is asserted 2) signal propagated to ctsb# input 3 ) d a ta b y te s e n te r t x f if o , b e g in tra n s m ittin g o n t x b 4) data propagates to receiving device rxa 5) rx fifo reaches threshold 6) rtsa# de-asserts 7) signal propagates to ctsb# input 8) transm ission stops on txb 9) usb bulk-in em pties rx fifo below threshold, rtsa# is asserted 10) signal propagated to ctsb# input 11) data bytes resum e transm itting on txb 5 6 7 8 9 10 11 rtsa# ctsb# txb rxa ctsa# txa rtsb# rxb receiver fifo trigger reached a u to r t s trigger level t ra n s m itte r a u to c t s m onitor local uart uarta 1.3.5.2 automatic dtr/dsr hardware flow control auto dtr/dsr hardware flow cont r ol behaves the same as the auto rts/cts hardware flow control described above except that it uses the dtr# and dsr# signals. gpio3 and gpio2 become dtr# and dsr#, respectively, when gpio_mode[2:0] = ?010? and flow_control[2:0] = ?001?. 1.3.5.3 automatic xon/xoff so ftware flow control when software flow control is enabled, the b1411 compares the receive data characters with the programmed xon or xof f characters. if the rece ived character matches th e programmed xoff charac ter, the b1411 will halt transmission as soon as the current character has co mpleted transmission. data transmission is resumed when a received character matches the xon charac ter. software flow co ntrol is enabled when flow_control[2:0] = ?010?. 1.3.6 auto rs-485 half-duplex control the auto rs-485 half-duplex control feature changes the behavior of the gpio5/rts#/rs485 pin when en abled by the gpio_mode register bits 2-0. see ?section 3.1.1.13, gpio_m ode regist er description (read / write)? on page 18. the flow_control register must also be set appropriately for use in
xr21b1411 9 rev. 1.2.0 enhanced 1-ch full-speed usb uart multidrop applications. see ?section 3.1.1.7, flow_control regi ster description (read / write)? on page 15. if enabled, the transmitter automatically asserts the gpio5/rts#/rs485 output prior to sending the data. by default, it de-asserts gpio5/rts#/rs485 followi ng the last stop bit of t he last character that has been transmitted, but the rs485_delay register may be us ed to delay the deassertion. the polarity of the gpio5/rts#/rs485 signal may also be modifi ed using the gpio_mode register bit 3. 1.3.7 multidrop mode with address matching the b1411 device has two address matching modes which are also set by the flow mode control register using modes 3 and 4. these modes are intended for a mult i-drop network application. in these modes, the xon_char register holds a unicast address and the xoff_char holds a multicast address. a unicast address is used by a transmitting master to broadcast an address to all attached slav e devices that is intended for only one slave device. a multicast address is used to broadcast an address intended for more than one recipient device. each attached slave device should have a unique unicast address value stored in the xon_char register, while multiple slaves may have the same multicast adderss stored in the xoff_char register. an address match occurs when an address byte (9 th bit or parity bit is ?1?) is received that matches the value stored in either the xon_char or xoff_char register. 1.3.7.1 receiver if an address match occurs in either flow control mode 3 or 4, the addre ss byte will not be loaded into the rx fifo, but all subsequent data bytes will be loaded into th e rx fifo. the uart rece iver will automatically be disabled when an address byte is received that does not match the values in the xon_char or xoff_char register. 1.3.7.2 transmitter in flow control mode 3, the uart transmitter will transmit irrespective of the rx address match. in flow control mode 4, the uart will only transmit following an rx address match. 1.3.8 programmable turn-around delay by default, the gpio5/rts#/rs485 pin will be de-asserted immediately after th e stop bit of the last byte has been shifted when auto rs-485 half-duplex control is enabled by the gpio_mode register. however, this may not be ideal for systems where the signal needs to propagate over long cables. therefore, the de- assertion of gpio5/rts#/rs485 pin can be delayed from 1 to 15 bit times via the rs485_delay register to allow for the data to reach distant uarts. 1.3.9 half-duplex mode half-duplex mode is enabled when fl ow_control[3] = 1. in half du plex mode, the uart will ignore any data on the rx input when the uart is transmitting data. 1.3.10 usb suspend all usb peripheral devices must s upport the usb suspend mode. per usb standard, the b1411 device will begin to enter the suspend state if it does not detect an y activity (including start of frame or sof packets) on its usb data lines for 3 ms. the device must then reduce power consumption from vbus power within the next 7 ms to the allowed limit of 2.5 ma for the suspended state. note that in this context, the "device" is all circuitry (including the b1411) that draws power from the host vbus. 1.3.11 remote wakeup when the b1411 is suspended, the gpio0/ri#/rwk# pin can be used to request that the host exit the suspend state. a high to lo w transition on this pin will cause the device to signal a remote wakeup request to the host via a custom driver. note that the sta ndard cdc-acm driver does not support this feature. in order for the remote wakeup to work, several things must be properly configured. first, the gpio0/ri# pin must be configured as an input. additionally, the b1411 device must have the remote wakeup feature support indicated in the usb attributes - see ?section 3.2.1.11, usb_attr ibutes (read / write otp)? on page 25. lastly, the host must detect the b1411 support fo r remote wake up and enable this feature. note that per usb standard, any remote wakeup signaling to the host will be suppressed for the first 5 ms after the device enters the suspend state.
xr21b1411 10 enhanced 1-ch full-speed usb uart rev. 1.2.0 1.4 otp the otp is an on-chip non-volatile memory, that is one-t ime programmable via the usb interface. some bits are pre-programmed at the factory and caution must be ta ken not to program any locations except those user defined addersses given in this data sheet. the otp memory contains user programmable location s for customer vendor and product id and device attributes. table 11 lists all of the otp memory contents.
xr21b1411 11 rev. 1.2.0 enhanced 1-ch full-speed usb uart 2.0 usb control commands the following table shows all of the usb control comm ands that are supported by the b1411. commands include standard usb commands, cdc-acm commands and custom exar commands. . t able 2: s upported usb c ontrol c ommands n ame r equest t ype r equest v alue i ndex l ength d escription dev get_status 0x80 0 0 0 0 0 2 0 device: remote wake-up + self-powered if get_status 0x81 0 0 0 0, 1 0 2 0 interface: zero ep get_status 0x82 0 0 0 0,1, 129, 133 0 2 0 endpoint: halted dev clear_feature 0x00 1 1 0 0 0 0 0 device remote wake-up ep clear_feature 0x02 1 0 0 0,1, 129, 133 0 0 0 endpoint halt dev set_feature 0x00 3 1 0 0 0 0 0 device remote wake-up dev set_feature 0x00 3 2 0 0 test 0 0 test mode - factory use only ep set_feature 0x02 3 0 0 1, 129, 133 0 0 0 endpoint halt set_address 0x00 5 addr 0 0 0 0 0 get_descriptor 0x80 6 0 1 0 0 len lsb len msb device descriptor get_descriptor 0x80 6 0 2 0 0 len lsb len msb configuration descriptor get_descriptor 0x80 6 0 3 0 0 len lsb len msb string descriptor get_configuration 0x80 8 0 0 0 0 1 0 set_configuration 0x00 9 n 0 0 0 0 0 n = 0,1 get_interface 0x81 10 0 0 0-1 0 1 0 cdc_acm_if set_line_coding 0x21 32 0 0 0 0 7 (note 1) 0 set the uart baud rate, parity, stop bits, etc. cdc_acm_if get_line_coding 0xa1 33 0 0 0 0 7 0 get the uart baud rate, parity, stop bits, etc. cdc_acm_if set_ - con - trol_line_state 0x21 34 val (note 2) 0 0 0 0 0 set uart control lines cdc_acm_if send_break 0x21 35 val lsb val msb 0 0 0 0 send a break for the speci - fied duration
xr21b1411 12 enhanced 1-ch full-speed usb uart rev. 1.2.0 n ote : 1) line coding length field are defined in table 3 n ote : 2) t able 3: set_line_coding o ffset f ield s ize v alue d escription 0 dwdterate 4 number data terminal rate, in bits per second 4 bcharformat 1 number stop bits: 0 = 1 stop bit 2 = 1 stop bits (1.5 stop bits not supported in b1411) 5 bparitytype 1 number parity: 0 = none 1 = odd 2 = even 3 = mark 4 = space 6 bdatabits 1 number data bits (7, 8 or 9) control signal bitmap values for setcontrollinestate are defined in table 4 t able 4: b it p osition d escription d15..d2 reserved (reset to zero) d1 carrier control for half duplex modems. this signal corresponds to rs-232 signal rt s. 0 = deactivate carrier (clear rts) 1 = activate carrier (set rts) the device ignores the value of this bit when operating in full duplex mode d0 indicates to dce if dte is present or not. this signal corresponds to rs-232 sig - nal dtr. 0 = not present (clear dtr) 1 = present (set dtr) set_control_line_state xr_set_reg 0x40 0 val lsb val msb regis - ter add r. lsb regis - ter addr . msb 0 0 exar custom command: set on e 12-bit register val: 12-bit register value register address: see table 5 xr_get_reg 0xc0 1 0 0 regis - ter add r. lsb regis - ter addr . msb 2 0 exar custom register: get on e 12-bit register register address: see table 5 t able 2: s upported usb c ontrol c ommands n ame r equest t ype r equest v alue i ndex l ength d escription
xr21b1411 13 rev. 1.2.0 enhanced 1-ch full-speed usb uart 3.0 register set description the internal register set of the b1411 controls the uart channel functionality, basic functionality of the fifos, otp controls, as well as registers a ssociated with the processing of driv er commands. these registers are accessible via the usb interface using the xr_set_reg and xr_get_reg usb comma nds. note that the uart_enable register should be used to disable the uart prior to any register write and re-enable the uart following any single or sequence of register writes. several exceptions are the gpio_set and gpio_clear registers as well as the tx_break and erro r_status registers. th e uart does not need to be disabled when writing these four registers. 3.1 b1411 register map t able 5: b1411 r egisters a ddress r egister n ame b it -11 b it - 10 b it -9 b it -8 b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 0x20d custom_driver 0 0 0 0 0 0 0 0 0 0 0 acti ve 0x216 cdc_acm_ - flow_control 0 0 0 0 0 0 0 0 half- duplex flow control mode select 0x217 cdc_acm_gpio_ - mode 0 0 0 0 0 0 0 0 xcvr enable polarity mode select 0x218 cdc_acm_gpio_ - direction 0 0 0 0 0 0 gpio 5 gpio 4 gpio 3 gpio 2 gpio 1 gpio 0 0x219 cdc_acm_gpi - o_int_mask 0 0 0 0 0 0 gpio 5 gpio 4 gpio 3 gpio 2 gpio 1 gpio 0 0xc00 uart_enable 0 0 0 0 0 0 0 0 0 0 rx tx 0xc06 flow_control 0 0 0 0 0 0 0 0 half- duplex flow control mode select 0xc07 xon_char 0 0 0 0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0xc08 xoff_char 0 0 0 0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0xc09 error_status 0 0 0 0 break status over - run error parity error fram - ing error break error 0 0 0 0xc0a tx_break bit-11 bit-10 bit-9 bit-8 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0xc0b rs485_delay 0 0 0 0 0 0 0 0 delay 0xc0c gpio_mode 0 0 0 0 0 0 0 0 rs485 polarity mode select 0xc0d gpio_direction 0 0 0 0 0 0 gpio 5 gpio 4 gpio 3 gpio 2 gpio 1 gpio 0 0xc0e gpio_set 0 0 0 0 0 0 gpio 5 gpio 4 gpio 3 gpio 2 gpio 1 gpio 0 0xc0f gpio_clear 0 0 0 0 0 0 gpio 5 gpio 4 gpio 3 gpio 2 gpio 1 gpio 0 0xc10 gpio_status 0 0 0 0 0 0 gpio 5 gpio 4 gpio 3 gpio 2 gpio 1 gpio 0
xr21b1411 14 enhanced 1-ch full-speed usb uart rev. 1.2.0 3.1.1 b1411 register descriptions note that all register reset default va lues are ?0? unless otherwise specified. 3.1.1.1 custom_driver (write only) custom_driver[0]: active this register holds the flag to determine which device driver is used (custom or cdc driver). for proper operation, a custom driver must set the active bit prior to sending any of the 4 cdc_acm commands that the b1411 supports. ? logic 0 = informs the b1411 that the standard cdc_acm driver is being used. values from the cdc_acm_xxx_xxxx registers will be loaded into their non-cdc_acm equivalents. ? logic 1 = informs the b1411 that a custom driver is being used. values from cdc_acm_xxx_xxxx registers are not used. custom_driver[11:1]: reserved these bits are reserved and should remain ?0?. 3.1.1.2 cdc_acm_flow_control regi ster description (read / write) the contents of this register, if programmed, are used to overwrite the flow_control register at address 0xc06 when a cdc command is sent from a standard cdc- acm driver to the b1411 device. note that this register can only be programmed from the otp. since a standard cdc_acm driver is unaware of uart registers in the b1411, this register may be utilized to program uart settings from power-up. when a custom driver is used, the custom driver should program thes e settings directly into the flow_control register. bit fields in this register are the same as those in the flow_control register. refer to ?section 3.1.1.7, flow_control register description (read / write)? on page 15 . 0xc11 gpio_int_mask 0 0 0 0 0 0 gpio 5 gpio 4 gpio 3 gpio 2 gpio 1 gpio 0 0xc12 customized_int 0 0 0 0 0 0 0 0 0 0 0 en 0xc14 pin_pullup_en 0 0 0 0 tx rx gpio 5 gpio 4 gpio 3 gpio 2 gpio 1 gpio 0 0xc15 pin_pull - down_en 0 0 0 0 tx rx gpio 5 gpio 4 gpio 3 gpio 2 gpio 1 gpio 0 0xc16 loopback 0 0 0 0 0 0 0 0 0 dtr_ dsr rts_ cts tx_ rx 0xc80 tx_fifo_reset 0 0 0 0 0 0 0 0 0 0 0 tx 0xc81 tx_fifo_count 0 0 0 0 count 0xcc0 rx_fifo_reset 0 0 0 0 0 0 0 0 0 0 0 rx 0xcc1 rx_fifo_count 0 0 0 count 0xcc2 rx_fi - fo_low_la - tency 0 0 0 0 0 0 0 0 0 0 0 en 0xd02 wide_mode 0 0 0 0 0 0 0 0 0 0 0 en t able 5: b1411 r egisters a ddress r egister n ame b it -11 b it - 10 b it -9 b it -8 b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0
xr21b1411 15 rev. 1.2.0 enhanced 1-ch full-speed usb uart 3.1.1.3 cdc_acm_gpio_mode regist er description (read / write) the contents of this register, if programmed, are used to overwrite the gpio_mode register at address 0xc0c when a cdc command is sent from a standard cdc-acm driv er to the b1411 device. note that this register can only be programmed from the otp. since a standar d cdc_acm driver is unaware of uart registers in the b1411, this register may be utiliz ed to program uart settings from pow er-up. when a custom driver is used, the custom driver should program these se ttings directly into the gpio_mode register. bit fields in this register are the same as those in the gpio_mode register. refer to ?section 3.1.1.13, gpio_mode register description (read / write)? on page 18 . 3.1.1.4 cdc_acm_gpio_direction regi ster description (read / write) the contents of this register, if programmed, are used to overwrite the gpio_direc tion register at address 0xc0d when a cdc command is sent from a standard cd c-acm driver to the b1411 device. note that this register can only be programmed from the otp. si nce a standard cdc_acm driver is unaware of uart registers in the b1411, this register may be utilized to program uart settings from power-up. when a custom driver is used, the custom driver should program thes e settings directly into the gpio_direction register. bit fields in this register are the same as those in the gpio_directio n register. refer to ?section 3.1.1.14, gpio_direction regist er description (read / write)? on page 18 . 3.1.1.5 cdc_acm_gpio_int_mask regi ster description (read / write) the contents of this register, if programmed, are used to overwrite the gpio_int_m ask register at address 0xc11 when a cdc command is sent from a standard cdc-acm driver to th e b1411 device. note that this register can only be programmed from the otp. si nce a standard cdc_acm driver is unaware of uart registers in the b1411, this register may be utilized to program uart settings from power-up. when a custom driver is used, the custom driver should program th ese settings directly into the gpio_int_mask register. bit fields in this register are the same as those in the gpio_int_mask register. refer to ?section 3.1.1.18, gpio_int_mask register description (read / write)? on page 19 . 3.1.1.6 uart_enable register description (read / write) ensure that both uart tx and uart rx are disabled be fore writing to any other uart registers except for the gpio_set, gpio_clear and tx break registers. uart_enable[0]: enable uart tx ? logic 0 = uart tx disabled. ? logic 1 = uart tx enabled. uart_enable[1]: enable uart rx ? logic 0 = uart rx disabled. ? logic 1 = uart rx enabled. uart_enable[11:2]: reserved these bits are reserved and should remain ?0?. 3.1.1.7 flow_control register description (read / write) these registers select the flow cont rol mode. these registers should only be written to when the uart is disabled. writing to the flow_con trol register when the uart is enabled will result in undefined behavior.
xr21b1411 16 enhanced 1-ch full-speed usb uart rev. 1.2.0 flow_control[2:0]: flow control mode select t able 6: f low c ontrol m ode s election m ode b it -2 b it -1 b it -0 m ode d escription 0 0 0 0 no flow control, no address matching. 1 0 0 1 hw flow control enabled. auto rts/cts or dtr/dsr must be selected by g pio_mode. 2 0 1 0 sw flow control enabled 3 0 1 1 multidrop mode - rx only after address match, tx ind ependent. (typically used with gpio_mode 3) 4 1 0 0 multidrop mode - rx / tx only after address match. (typically used with gpi - o_mode 4) flow_control[3]: half-duplex mode x logic 0 = normal (full-duplex) mode. the uart can transmit and receive data at the same time. x logic 1 = half-duplex mode. in half-duplex mode, any data on the rx pin is ignored when the uart is transmitting data. flow_control[11:4]: reserved these bits are reserved and should remain ?0?. 3.1.1.8 xon_char register descript ion (read / write - default 0x17) the xon_char stores the xon character that is us ed in the automatic software flow control. xon_char[7:0]: xon character in automatic software flow control mode, the uart w ill resume dat a transmission when the xon character has been received. for behavior in the address match mode, see ?section 1.3.7, multidrop mode with address matching? on page 9 . xon_char[11:8]: reserved these bits are reserved and should remain ?0?. 3.1.1.9 xoff_char register descript ion (read / write - default 0x19) the xoff_char stores the xoff character that is used in the automatic software flow control. xoff_char[7:0]: xoff character in automatic software flow contro l mode, the uart will suspend data tr ansmission when th e xoff character has been received. for behavior in the address match mode, see ?section 1.3.7, multidrop mode with address matching? on page 9 . xoff_char[11:8]: reserved these bits are reserved and should remain ?0?.
xr21b1411 17 rev. 1.2.0 enhanced 1-ch full-speed usb uart 3.1.1.10 error_status regist er description - read-clear this register reports any historical errors that have oc curred on the line such as break, framing, parity and overrun. note that these errors cannot be directly associated with any bytes within the rx fifo. for diagnostic purposes, the wide_mode can be enabled. in this mode, errors are real time, i.e. are directly associated with the current byte. error_status[2:0]: reserved these bits are reserved. any values read from these bits should be ignored. error_status[3]: break error ? logic 0 = no break condition ? logic 1 = a break condition has been detected (clears after read). error_status[4]: framing error ? logic 0 = no framing error ? logic 1 = a framing error has been detected (clears after r ead). a framing error occurs when a stop bit is not present when it is expected. error_status[5]: parity error ? logic 0 = no parity error ? logic 1 = a parity error has been detected (clears after read). error_status[6]: overrun error ? logic 0 = no overrun error ? logic 1 = an overrun error has been detected (clears af ter read). an overrun error occurs when the rx fifo is full and another byte of data is received. error_status[7]: break status ? logic 0 = break condition is no longer present. ? logic 1 = break condition is currently being detected. error_status[11:8]: reserved ? these bits are reserved and should remain ?0?. 3.1.1.11 tx_break register description (read / write) writing a value between 1 and 0xffe to this register causes a break condition to be generated continuously until the register is cleared. the register decrements at 1 ms intervals until the count is zero. if another non- zero value, othe r than 0xfff is written to th e tx_break register before the co unter decrements to zero, the decrement continues from the newly written value. a value of 0xfff will cause the br eak condition to be generated until a different value is written to the register. if data is being shifted out of the tx pin, the data will be completely shifted out befo re the break condition is generated. note that the break condition may be delayed by up to 1 ms following the write of the tx_break register. additionally, the break condition may persist for up to 2 bit times after the counter has decremented to zero. 3.1.1.12 rs485_delay register description (read / write) rs485_delay[3:0]: turn-around delay this is the number of bit times the b1411 waits before de-asserting the gpio5/rt s#/rs485 pin when it is configured for automatic rs-485 half-duplex control.
xr21b1411 18 enhanced 1-ch full-speed usb uart rev. 1.2.0 rs485_delay[11:4]: reserved these bits are reserved and should be ?0?. 3.1.1.13 gpio_mode register des cription (read / write) gpio_mode[2:0]: gpio mode select there are 4 modes of operation for the gp ios. th e descriptions can be found in ?section 1.3, uart? on page 5 . t able 7: gpio m odes [2:0] gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 m ode d escription 000 gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio mode, all gpio pins available as gpio 001 gpio0 gpio1 gpio2 gpio3 cts# rts# gpio4 and gpio5 used for auto rts/cts hw fl ow control 010 gpio0 gpio1 dsr# dtr# gpio4 gpio5 gpio2 and gpio3 used for auto dtr/dsr hw fl ow control 011 gpio0 gpio1 gpio2 gpio3 gpio4 rs485 gpio5 used for auto rs-485 half-duplex control 100 gpio0 gpio1 gpio2 gpio3 gpio4 rs485 gpio5 used for auto rs-485 half-duplex control af ter address match (see flow_control mode 4). gpio_mode[3]: rs485 polarity x logic 0 = gpio5/rts#/rs485 low for tx x logic 1 = gpio5/rts#/rs485 high for tx gpio_mode[11:4]: reserved these register bits are reserved. when writing to these bits, the value should be ?0?. when reading from these b its, they are undefined and should be ignored. 3.1.1.14 gpio_direction register description (read / write) this register controls the direction of pins configured as gpio. (pins configured for uart functions via the gpio_mode register, e.g. rts# are not controlled or reported in the gp io_direction register.) gpio_direction[5:0]: gpiox direction x logic 0 = gpiox is an input. x logic 1 = gpiox is an output. gpio_direction[11:6]: reserved these register bits are reserved and should be ?0?. 3.1.1.15 gpio_set register desc ription (read / write) writing a ?1? in this register sets the corresponding gpio o utput high. writing a ?0? in this register sets the corresponding gpio output low. for gpio pins configured as an input via the gpio_direction register this register has no effect. bits 11-6 are unused and should be ?0?. 3.1.1.16 gpio_clear register description (read / write) writing a ?1? in this register clears the corresponding gpio ou tput low. writing a ?0? to a bit has no effect. bits 11-6 are unused and should be ?0?. bits
xr21b1411 19 rev. 1.2.0 enhanced 1-ch full-speed usb uart 3.1.1.17 gpio_status register description (read only) this register reports the current state of each of the gpio pins. 3.1.1.18 gpio_int_mask register description (read / write) dictates whether a change in gpio pin state causes the de vice to generate a usb interrupt packet. in either case, the gpio status register will still report the pin's st ate when read, and if an interrupt packe t is formed due to other interrupt trigger, th e interrupt packet will contain the current stat e of the pin. gpio_int_mask[5:0 ]: gpi0[5:0] x logic 0 = a change in the pin's state causes the device to generate an interrupt packet. x logic 1 = a change in the pin's state does not cause the device to generate an interrupt packet. gpio_int_mask[11:6]: reserved x these bits are reserved and should remain ?0?. 3.1.1.19 customized_in t re gister description (read / write) enables the customized interrupt p acket format to report all gpio status in the interrupt packet. customized_int[0]: enable x logic 0 = use standard interrupt packet. see table 9 x logic 1 = use customized interrupt packet. see table 10 customized_int[11:1]: reserved x these bits are reserved and should remain ?0?. t able 8: i nterrupt p acket f ormat o ffset f ield s ize (b ytes ) v alue d escription 0 bmrequesttype 1 8?b10100001 d7 = device-to-host direction d6:5 = class type d4-0: = interface recipient 1 bnotification 1 8?h20 defined encoding for serial_state 2 wvalue 2 16?h0000 4 windex 2 16?h0000 d15-8 = reserved (0) d7-0 = interface number, 8?h00 for the cdc com - mand interface 6 wlength 2 16?h0002 2 bytes of transferred data 8 data 2 standard in t_status (see table 9 or table 10 ) d15-7 = reserved (0) d6 = boverrun d5 = bparity d4 = bframing d3 = bringsignal (ri) d2 = bbreak d1 = btxcarrier (dsr) d0 = brxcarrier (cd)
xr21b1411 20 enhanced 1-ch full-speed usb uart rev. 1.2.0 t able 9: b its f ield d escription d15..d7 reserved (future use) d6 boverrun received data has been discarded due to overrun in the device. d5 bparity a parity error has occured. d4 bframing a framing error has occured. d3 bringsignal state of ring signal detection of the device. d2 bbreak state of break detection mechanism of the device. d1 btxcarrier state of transmission carrier. this signal corresponds to v.24 signal 106 and rs-232 signal dsr. d0 brxcarrier state of receiver carrier detection me ch anism of device. this signal corre - sponds to v.24 signal 109 and rs-232 signal dcd. d ata f ield of s tandard i nterrupt p acket if the exar vendor specific packet mapping is enabled then the data field also includes interrupt status for all of the uart / gpio pins as follows: t able 10: b it ( s ) f ield d escription 15 d15 reserved (0) 14 d14 bgpio5 (rts) 13 d13 bgpio4 (cts) 12 d12 bgpio3 (dtr) 11 d11 bgpio0 (ri) 10 d10 reserved (0) 9 d9 bgpio2 (dsr) 8 d8 bgpio1 (cd) 7 d7 reserved (0) 6 d6 boverrun 5 d5 bparity 4 d4 bframing 3 d3 bringsignal (ri) 2 d2 bbreak 1 d1 btxcarrier (dsr) 0 d0 brxcarrier (cd) d ata f ield of c ustomized i nterrupt p acket - e xar v endor s pecific
xr21b1411 21 rev. 1.2.0 enhanced 1-ch full-speed usb uart 3.1.1.20 pin_pullup_en register description (read / write) pin_pullup_en[5:0 ]: gpi0[5:0] enables internal pullup feature on the selected gpio pins ? logic 0 = disable pullup on the corresponding pin. ? logic 1 = enable pullup on the corresponding pin - caution: do not enable pulldown simultaneously pin_pullup_en[6]: uart rx enables internal pullup feature on the uart rx pin ? logic 0 = disable pullup on the corresponding pin. ? logic 1 = enable pullup on the corresponding pin - caution: do not enable pulldown simultaneously pin_pullup_en[7]: uart tx enables internal pullup feature on the uart tx pin ? logic 0 = disable pullup on the corresponding pin. ? logic 1 = enable pullup on the corresponding pin - caution: do not enable pulldown simultaneously pin_pullup_en[11:8]: reserved ? these bits are reserved and should remain ?0?. 3.1.1.21 pin_pulldown_en regist er description (read / write) pin_pulldown_en[5:0]: gpi0[5:0] enables internal pulldown feature on the selected gpio pins ? logic 0 = disable pulldown on the corresponding pin. ? logic 1 = enable pulldown on the corresponding pin - caution: do not enable pullup simultaneously pin_pulldown_en[6]: uart rx enables internal pulldown feature on the uart rx pin ? logic 0 = disable pulldown on the corresponding pin. ? logic 1 = enable pulldown on the corresponding pin - caution: do not enable pullup simultaneously pin_pulldown_en[7]: uart tx enables internal pulldown feature on the uart tx pin ? logic 0 = disable pulldown on the corresponding pin. ? logic 1 = enable pulldown on the corresponding pin - caution: do not enable pullup simultaneously pin_pulldown_en[11:8]: reserved ? these bits are reserved and should remain ?0?. 3.1.1.22 loopback register description (read / write) loopback[0]: tx_rx when this bit is set all tran smitted uart data is looped back to the uart receiver. note that when the internal loopback is enabled, the tx data will be disabled and rx data will be ignored. ? logic 0 = disable loopback. ? logic 1 = enable loopback.
xr21b1411 22 enhanced 1-ch full-speed usb uart rev. 1.2.0 loopback[1]: rts_cts when this bit is set rts is looped back to cts. ? logic 0 = disable loopback. ? logic 1 = enable loopback. loopback[2]: dtr_dsr when this bit is set dtr is looped back to dsr. ? logic 0 = disable loopback. ? logic 1 = enable loopback. loopback[11:3]: reserved these bits are reserved and should remain ?0?. 3.1.1.23 tx_fifo_reset (write only) tx_fifo_reset[0]: reset ? write a ?1? to reset the tx fifo, self-clearing. tx_fifo_reset[1 1:1]: reserved these bits are reserved and should remain ?0?. 3.1.1.24 tx_fifo_co unt (read only) tx_fifo_count[7:0]: character count ? reports the number of characte rs currently in the tx fifo. tx_fifo_count[11:8]: reserved these bits are reserved and should remain ?0?. 3.1.1.25 rx_fifo_reset (write only) rx_fifo_reset[0]: reset ? write a ?1? to reset the rx fifo, self-clearing. rx_fifo_reset[11:1]: reserved these bits are reserved and should remain ?0?. 3.1.1.26 rx_fifo_count (read only) rx_fifo_count[8:0]: character count ? reports the number of characte rs currently in the rx fifo. rx_fifo_reset[11:9]: reserved these bits are reserved and should remain ?0?. 3.1.1.27 rx_fifo_low_latency (read / write) rx_fifo_low_latency[0]: low latency enable this register is automatically set to logic ?1? for baud rates below 40961 bps. ? logic 0 = receive data is not from rx fifo until bmaxpacketsize (normally 64 bytes) or timeout (3 characters) has been reached. (note: when the cd c-acm driver is used, th e bmaxpacketsize becomes 63 bytes.) ? logic 1 = receive data is forwarded fr om rx fifo immediately upon receipt.
xr21b1411 23 rev. 1.2.0 enhanced 1-ch full-speed usb uart rx_fifo_low_latency[11:1]: reserved these bits are reserved and should remain ?0?. 3.1.1.28 wide_mode (read / write) wide_mode[0]: en x logic 0 = normal (7, 8 or 9 bit data) mode x logic 1 = wide mode - see ?section 1.3.1.1, wide mode transmit? on page 6 , ?section 1.3.2.3, wide mode operation with 7 or 8-bit data? on page 6 and ?section 1.3.2.4, wide m ode op eration with 9-bit data? on page 6 . wide_mode[11:1]: reserved these bits are reserved and should remain ?0?. 3.2 otp memory the otp on-chip memory contents are accessible via the usb interface. for details on programming the otp contact uarttechsupport@exar.com. note that certain memory locations are pre-programmed at the factory. programming any of these locations or locations not documented in the data sheet may cause permanent functional damage to the b1411 device. t able 11: otp m emory a ddr ess r egister n ame b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 0x00 otp_config0 factory programmed - do not overwrite lowpow - er_pol reserve d 0x01 otp_config1 factory programmed - do not overwrite 0x02 otp_config2 factory programmed - do not overwrite 0x03 otp_config3 0 0 0 0 ena_vbu s_sense core_clock_div 0x04 otp_valid 0 0 0 0 0 line_ coding string s usb 0x05 - 0x0 b line_coding_0 - line_cod - ing_6 value 0x0c usb_vendor_id_lsb value 0xd usb_vendor_id_msb value 0xe usb_product_id_lsb value 0xf usb_product_id_msb value 0x10 usb_attributes 0 self - _pow - ered remote_ w akeup reserved 0x11 usb_maxpower value 0x12 - 0x21 manufacturer_string_0 - manuf acturer_string_15 value 0x22 - 0x31 product_string_0 - pro - duct_string_15 value 0x32 - 0x41 serial_number_string_0 - serial_num ber_string_15 value 0x42 - 0x1f f address_value value
xr21b1411 24 enhanced 1-ch full-speed usb uart rev. 1.2.0 3.2.1 otp memory descriptions some otp memory locations are pre-programmed at the factory before shipments to customers. programming any memory location other than those specified below may result in permanent damage to the device. 3.2.1.1 otp config0 (read / write otp) otp_config0[ 0] : reserved x factory programmed - overwriting this bit may cause functional damage to the b1411 device otp_config0[1] : lo wpower_pol x sets the polarity of the lowpower output pin ?logic 0 = lowpower output pin will be active low ?logic 1 = lowpower output pin will be active high otp_config0[7: 2 ]: reserved x factory programmed - overwriting these bits ma y cause functional damage to the b1411 device 3.2.1.2 otp config1 (read / write otp) otp_config1[7: 0 ]: reserved x factory programmed - overwriting these bits ma y cause functional damage to the b1411 device 3.2.1.3 otp config2 (read / write otp) otp_config2[7: 0 ]: reserved x factory programmed - overwriting these bits ma y cause functional damage to the b1411 device 3.2.1.4 otp config3 (read / write otp) otp_config3[2:0]: core_clock_select the b1411 core can run at a fraction of the 48 mhz bu s clock to minimize power consumption in the core. refer to table 12 for core clock divider settings. note that the sele cted core clock rate must be a minimum of 4x the maximum baud rate setting desired in a customer ap plication . for example, if a core clock of 6 mhz is selected, the maximum baud rate of the b1411 is 1.5 mbps. t able 12: c ore c lock d ivider v alue n ame d escription 3'b000 div_by_1 core clock = clock / 1 (48 mhz) 3'b001 div_by_2 core clock = clock / 2 (24 mhz) 3'b010 div_by_4 core clock = clock / 4 (12 mhz) 3'b011 div_by_8 core clock = clock / 8 (6 mhz) 3'b100 - 3'b111 not used reserved - using these settings may cause functional damage to the b1411 device otp_config3[3]: ena_vbus_sense x controls whether vbus is sensed. ? logic 0 = vbus sense is not enabled (typically used in bus-powered mode) ?logic 1 = vbus sense is enabled (typ ically used in self-p owered mode)
xr21b1411 25 rev. 1.2.0 enhanced 1-ch full-speed usb uart otp_config3[7: 4]: reserved these bits are reserved and should remain ?0?.otp valid (read / write otp) 3.2.1.5 otp _valid (read / write otp) this register holds the valid flag for the otp override values. these include the usb device and configuration descriptor overrides and default line coding overrides. otp_valid[0]: usb ? set this bit to indicate that the usb device and conf iguration descriptors have sele cted fields overwritten by otp data. otp_valid[1]: strings ? set this bit to indicate that the contents of the usb string descriptors are overwritten by otp data. otp_valid[2]: line_coding ? set this bit to indicate that the power up line coding (baud rate, stop bits, parity) are overwritten by otp data. otp_valid[7:3]: reserved ? these bits are reserved and should remain ?0? 3.2.1.6 line coding0-6 (read / write otp) line_coding0-6[7:0]: value the contents of this field have the same format as th at used in the cdc-acm set _line_coding request. it allows the default baud rate and character format to be overridden. 3.2.1.7 usb_vendor_id_lsb (read / write otp) usb_vendor_id_lsb[7:0]: value bits [7:0] of the usb vendor id reported with the desc riptors. if otp_valid.usb is set to 0, then the exar vendor id is reported instead. 3.2.1.8 usb_vendor_id_msb (read / write otp) usb_vendor_id_msb[7:0]: value bits [15:8] of the usb vendor id re ported with the descriptors. if otp_va lid.usb is set to 0, then the exar vendor id is reported instead. 3.2.1.9 usb_product_id_lsb (read / write otp) usb_product_id_lsb[7:0]: value bits [7:0] of the usb product id reported with the desc riptors. if otp_valid.usb is set to 0, then the exar product id is reported instead. 3.2.1.10 usb_product_id_msb (read / write otp) usb_product_id_msb[7:0]: value bits [15:8] of the usb product id reported with the de scriptors. if otp_valid.usb is set to 0, then the exar product id is reported instead. 3.2.1.11 usb_attributes (read / write otp) usb_attributes[4:0]: reserved ? these bits are reserved and should remain ?0?
xr21b1411 26 enhanced 1-ch full-speed usb uart rev. 1.2.0 usb_attributes[5]: remote_wakeup ? bit[5] of the bmattributes field of t he device descriptor. if otp_valid.usb is set to 1, then this bit is set to indicate that the device supports remote wakeup. usb_attributes[6]: self_powered bit[6] of the bmattributes field of the device descriptor. if otp_valid.usb is set to 1, then this bit is set to indicate that the device is self powered. if the device also requires bus power to be reserved, then that power requirement is given by the usb_maxpower field. usb_attributes[7]: reserved this bit is reserved and should remain ?0? 3.2.1.12 usb_maxpower (read / write otp) usb_maxpower[7:0]: value the bmaxpower field of the device descriptor. it is expr essed in units of 2 ma. if otp_valid.usb is set to 1, then this indicates the power requirement of the device. 3.2.1.13 manufacturer string 0-15 (read / write otp) manufacturer_string _0-15[7:0]: value the default manufacturer string. null-terminated ascii. 3.2.1.14 product string 0-15 (read / write otp) product_string_0-15[7:0]: value the default product string. null-terminated ascii. 3.2.1.15 serial number string 0-15 (read / write otp) serial_number_string_0-15[7:0]: value the default serial number string. null-terminated ascii. 3.2.1.16 address value (read / write otp) address_value[7:0]: value the address value feature can be used to further cust omize the power-up defaults for the xr21b1411 before a software driver begins to initia lize the device. for exam ple, the manufacturer, product and serial number strings can be customized using the address value featur e. however, if improper ly used, this feature may cause permanent functional damage in the device. send an e-mail to uarttechsupport@exar.com for informati on regarding customizing register default values that can not be initialized in the exar i/o lab web configuration tool.
xr21b1411 27 rev. 1.2.0 enhanced 1-ch full-speed usb uart 4.0 electrical characteristics t able 13: a bsolute m aximum r atings p arameter r ating u nit vcc supply voltage + 5.75 v input voltage (all pins except usbd+ and usbd-) - 0.3 to + 5.5 v input voltage (usbd+ and usbd-) - 0.3 to + 5.75 v junction termperature 125 deg. c dc electrical characteristics - power consumption u nless otherwise noted : ta = -40 o to +85 o c, v cc is 4.4v - 5.25v s ymbol p arameter l imits m in typ m ax u nits c onditions i cc power supply current 6.75 7.25 ma 6 mhz internal clock i cc power supply current 7.5 8 ma 12 mhz internal clock i cc power supply current 8.5 9 ma 24 mhz internal clock i cc power supply current 10.5 12 ma 48 mhz internal clock i susp suspend mode current 1 1.25 ma dc electrical characteristics - uart, lowpower & gpio pins u nless otherwise noted : ta = -40 o to +85 o c, v cc is 4.4v - 5.25v, vio_ref = 1.6v - 3.6v s ymbol p arameter l imits m in m ax u nits c onditions v il input low voltage -0.3 0.25 * vio_ref v v ih input high voltage 0.70 * vio_ref vio_ref v v ol output low voltage 0.3 0.5 v v i ol = 1 ma, vio_ref = 1.6v i ol = 4 ma, vio_ref = 3.6v v oh output high voltage 1.3 2.8 vio_ref vio_ref v v i oh = -400 ua, vio_ref = 1.6v i oh = -1.5 ma, vio_ref = 3.6v i il input low leakage current 10 ua i ih input high leakage current 10 ua c in input pin capacitance 5 pf 5v
dc electrical characteristics - usb i/o pins u nless otherwise noted : ta = -40 o to +85 o c, v cc is 4.4v - 5.25v s ymbol p arameter l imits m in m ax u nits c onditions v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 5.25 v v ol output low voltage 0 0.3 v external 1.5 k ohm to 3. 6v on usbd- pin v oh output high voltage 2.8 3.6 v external 15 k ohm to gnd on usbd- pin v drvz driver output impedance 28 44 ohms i osc open short current current 38.5 ma 1.5 v on usbd+ and us bd- xr21b1411 28 enhanced 1-ch full-speed usb uart rev. 1.2.0
xr21b1411 29 rev. 1.2.0 enhanced 1-ch full-speed usb uart package dimensions (16 pin qfn - 3 x 3 x 0.9 mm )
n ote : qfn16 theta ja = 36.4 deg. c/w, theta jc = 17.8 deg. c / w. all values are typical.
revision history d ate r evision d escription september 2010 1.0.0 initial datasheet. october 2010 1.0.1 released datasheet. november 2010 1.0.2 corrected definition of self powered bit in otp. updated modem io 5v tolerance. january 2011 1.1.0 added unique preprogrammed serial number description july 2016 1.2.0 added windows driver versions, minor clarifications including requirement for odd produ ct id in windows os. reduced absolute maximum vcc rating and reduced vih in dc electrical characteristics. added tape and reel part number in ordering infor - mation section. clarified vbus_sense pin definition in bus powered mode. 30 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent in fringement. charts and sc hedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assurances to its satisfaction that: (a) the ri sk of injury or damage has been minimized; (b) the us er assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2016 exar corporation datasheet july 2016. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. xr21b1411 rev. 1.2.0 enhanced 1-ch full-speed usb uart

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