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fn8084 rev 2.00 page 1 of 12 august 13, 2015 fn8084 rev 2.00 august 13, 2015 ISL95311 digitally controlled potentiometer (xdcp?), terminal voltage 0v to 13.2v, 128 taps i 2 c interface datasheet the intersil ISL95311 is a dig itally controlled potentiometer (xdcp). the device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. the wiper position is c ontrolled by an i 2 c interface. the potentiometer is impleme nted by a resistor array composed of 127 resistive el ements and a wiper switching network. between each element and at either end are tap points accessible to the wiper terminal. the wiper of the potentiometer has an associat ed volatile wiper counter register (wr) and a non-volatile initial value register (ivr) that can be directly written to and read by the user. the contents of the wr con trols the position o f the wiper on the resistor array through the swit ches. at power-up, the device recalls the contents of the ivr to the corresponding wr. the device can be used as a three-terminal potentiometer or as a two-terminal va riable resistor in a wide variety of applications, including: ? lcd contrast control ? parameter and bias adjustments ? industrial and aut omotive control ? mechanical pot replacement features ? non-volatile solid-s tate potentiometer ?i 2 c serial interface ? dcp terminal voltage, 0v to +13.2v ? 128 wiper tap points - 0.8% resolution - wiper position stored i n nonvolatile memory and recalled on power-up ? 127 resistive elements - temperature compensated - low wiper resistance 70 ? typical @ 3.3v ? low power cmos - standby current, 2a @ v cc = +3.6v ? high reliability - endurance, 200,000 data changes per bit - register data retention 50 years @ t ? +75c ?r total values = 10k ??? 50k ? ? 10 ld msop package ? pb-free (rohs compliant) pinout ISL95311 (10-ld msop) top view v cc scl sda gnd 1 2 3 4 10 9 8 7 r h r w a0 v+ 5 r l 6 a1 ordering information part number (note) part marking resistance option ( ? ) temp range (c) package (pb-free) pkg. dwg. # ISL95311wiu10z aje 10k -40 to +85 10-ld msop m10.118 add -tk suffix for tape and reel. please refer to tb347 for d etails on reel specifications. note: these intersil pb-free pl astic packaged products employ sp ecial pb-free material sets; molding compounds/die attach mater ials and 100% matte tin plate plus anneal - e3 termination finish, which is r ohs compliant and compatible with both snpb and pb-free solderi ng operations. intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020.
ISL95311 fn8084 rev 2.00 page 2 of 12 august 13, 2015 block diagram 7-bit wiper register 7-bit nonvolatile memory store and recall control circuitry one of 128 decoder resistor array r h sda scl transfer gates r l r w control and memory vcc gnd r h r w r l simple block diagram detailed block diagram 0 1 2 124 125 126 127 v+ (volatile) slave address decode a1 a0 sda scl a1 a0 pin number symbol description 1 sda data i/o for i 2 c serial interface; it has an open drain output and may be wire -ord with other open drain active low outputs 2 gnd ground 3 vcc positive logic supply voltage 4 a1 address select pin used to s et the slave address for the i 2 c serial interface 5 a0 address select pin used to s et the slave address for the i 2 c serial interface 6r h a fixed terminal for one end of the potentiometer resistor 7r w the wiper terminal, which is equi valent to the movable terminal of a potentiometer 8r l a fixed terminal for one end of the potentiometer resistor 9 v+ positive bias voltage for t he potentiometer wiper control 10 scl clock input for the i 2 c serial interface
ISL95311 fn8084 rev 2.00 page 3 of 12 august 13, 2015 absolute maximum ratings reco mmended operating conditions storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on sda, scl, a0, a1 with respect to gnd . . . . . . . . . . . . . . . . . . . . -0.3v to v cc + 0.3v voltage on v+ (referenced to gnd) . . . . . . . . . . . . . . . . . . . . +13.2v ? v = |v (rh) - v (rl) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v+ r h , r l , r w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v+ i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v power rating of dcp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mw temperature range (industrial) . . . . . . . . . . . . . . . . . -40c to +85c v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v v+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0v to 13.2v wiper current of dcp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0ma pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. analog specifications over recommended operating condi tions, unless otherwise stated. symbol parameter test conditions min (note 15) typ (note 1) max (note 15) unit r total r h to r l resistance w option 10 k ? u option 50 k ? r h to r l resistance tolerance -20 +20 % v rh r h terminal voltage v rl = 0v 0 v+ v r w wiper resistance v+ = 12.0v, wiper current = v+/r total 70 200 ? c h /c l /c w potentiometer capacitance 10/10/25 pf i lkgdcp leakage on dcp pins voltage at pin from gnd to v+ 0.1 1 a voltage divider mode (0v @ r l ; v+ @ r h ; measured at r w , unloaded) inl (note 6) integral non-linearity w and u option -1 1 lsb (note 2) dnl (note 5) differential non-linearity w and u option -0.5 0.5 lsb (note 2) zserror (note 3) zero-scale error w option 0 1 7 lsb (note 2) u option 0 0.5 2 fserror (note 4) full-scale error w option -7 -1 0 lsb (note 2) u option -2 -0.5 0 tc v (note 7) ratiometric temperature coeffi cient dcp register set to 40 hex 4 ppm/c resistor mode (measurements between r w and r l with r h not connected, or between r w and r h with r l not connected) rinl (note 11) integral non-linearity dcp register set between 20 hex and 7f he x; monotonic over all tap positions -1.0 1.0 mi (note 8) rdnl (note 10) differential non-linearity w and u option -0.5 0.5 mi (note 8) roffset (note 9) offset dcp register set to 00 hex, w option 0 1 7 mi (note 8) dcp register set to 00 hex, u option 0 0.5 2 tc r (note 12) resistance temperature coeffici ent dcp register set between 20 h ex and 7f hex 45 ppm/c
ISL95311 fn8084 rev 2.00 page 4 of 12 august 13, 2015 operating specifications over the recommended operating c onditions unless otherwise spec ified. symbol parameter test conditions min (note 15) typ (note 1) max (note 15) unit i cc1 v cc supply current, volatile write/read f scl = 400khz; sda = open; (for i 2 c, active, read, and volatile write states only) 1ma i cc2 v cc supply current, nonvolatile write f scl = 400khz; sda = open; (for i 2 c, active, nonvolatile write states only) 3ma i sb v cc current, standby v cc = +5.5v, i 2 c interface in standby state 5 a v cc = +3.6v, i 2 c interface in standby state 2 a i v+ v+ bias current v+ = 13.2v, v cc = +5.5v 1 a i lkgdig leakage current, at pins sda, scl, a0, and a1 pins voltage at pin from gnd to v cc -10 10 a t dcp dcp wiper response time scl falling edge of last bit of dcp dat a byte to wiper change 1s vpor power-on recall voltage v cc range at which memory recall occurs 1.5 1.8 2.6 v v cc ramp v cc ramp rate 0.2 v/ms t d power-up delay v cc above vpor, to dcp ini tial value register recall completed, and i 2 c interface in standby state 3ms eeprom specs eeprom endurance 200,000 cycles eeprom retention temperature ? +75c 50 years serial interface specs v il a0, a1, sda, and scl input buffer low voltage -0.3 0.3* v cc v v ih a0, a1, sda, and scl input buffer high voltage 0.7* v cc v cc + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05* v cc v v ol sda output buffer low voltage, sinking 4ma 00.4v cpin a0, a1, sda, and scl pin capacitance 10 pf f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v cc , until sda exits the 30% to 70% of v cc window 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v cc during the following start condition 1300 ns t low clock low time measured at the 30% of v cc crossing 1300 ns t high clock high time measured at the 70% of v cc crossing 600 ns t su:sta start condition set-up time scl rising edge to sda falling edge; both crossing 70% of v cc 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v cc to scl falling edge crossing 70% of v cc 600 ns t su:dat input data set-up time from sda exiting the 30% to 70% of v cc window, to scl rising edge crossing 30% of v cc 100 ns
ISL95311 fn8084 rev 2.00 page 5 of 12 august 13, 2015 t hd:dat input data hold time from scl rising edge crossing 30% of v cc to sda entering the 30% to 70% of v cc window 0ns t su:sto stop condition set-up time from s cl rising edge crossing 70% of v cc , to sda rising edge crossing 30% of v cc 600 ns t hd:sto stop condition hold time from sda rising edge to scl falling edg e. both crossing 70% of v cc 600 ns t dh output data hold time from scl falling edge crossing 30% of v cc , until sda enters the 30% to 70% of v cc window 0ns t r (note 14) sda and scl rise time from 30% to 70% of v cc 20 + 0.1 * cb 250 ns t f (note 14) sda and scl fall time from 70% to 30% of v cc 20 + 0.1 * cb 250 ns cb (note 14) capacitive loading of sda or scl total on-chip and off-chip 10 400 pf rpu (note 14) sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f , for cb = 400pf, max is about 2k ? ~2.5k ? . for cb = 40pf, max is about 15k ? ~20k ? . 1k ? t wp (notes 13) non-volatile write cycle time 12 20 ms t su:a a0, a1 set-up time before start condition 600 ns t hd:a a0, a1 hold time after stop condition 600 ns notes: 1. typical values are for t a = +25c and 3.3v supply voltage. 2. lsb: [v(r w ) 127 C v(r w ) 0 ] / 127. v(r w ) 127 and v(r w ) 0 are v(r w ) for the dcp register set to 7f hex and 00 hex respectively. l sb is the incremental voltage when changing from one tap to an adjacent t ap. 3. zs error = v(r w ) 0 / lsb. 4. fs error = [v(r w ) 127 C v+] / lsb. 5. dnl = [v(r w ) i C v(r w ) i-1 ] / lsb-1, for i = 1 to 127. i is the dcp register setting. 6. inl = v(r w ) i C (i ? lsb C v(r w ) 0 ) for i = 1 to 127. 7. for i = 16 to 120 decimal, t = - 40c to 85c. max( ) is the max imum value of the wiper voltage and min ( ) is the minimum valu e of the wiper voltage over the temperature range. 8. mi = | r 127 C r 0 | / 127. r 127 and r 0 are the measured resistances for the dcp register set to 7f he x and 00 hex respectively. 9. roffset = r 0 / mi, when measuring between r w and r l . roffset = r 127 / mi, when measuring between r w and r h . 10. rdnl = (r i C r i-1 ) / mi, for i = 16 to 127. 11. rinl = [r i C (mi ? i) C r 0 ] / mi, for i = 16 to 127. 12. for i = 16 to 127, t = -40c to +85c. max( ) is the maximum va lue of the resistance and min ( ) is the minimum value of the r esistance over the temperature range. 13. t wp is the minimum cycle time to be allowed for any non-volatile w rite by the user, unless acknowle dge polling is used. it is the time from a valid stop condition at the end of a write sequence of a i 2 c serial interface write operation, to the end of the self-time d internal non-volatile write cycle. 14. recommended operating limits and are not production tested. 15. parts are 100% tested at +85c. over temperature limits esta blished by characterization and are not production tested. operating specifications over the recommended operating c onditions unless otherwise spec ified. (continued) symbol parameter test conditions min (note 15) typ (note 1) max (note 15) unit tc v max v rw ?? i ?? min v rw ?? i ?? C max v rw ?? i ?? min v rw ?? i ?? + ?? 2 ? --------------------------------------------------------------- ------------------------------ - 10 6 125c ---------------- - ? = tc r max ri ?? min ri ?? C ?? max ri ?? min ri ?? + ?? 2 ? --------------------------------------------------------------- - 10 6 125c ---------------- - ? =
ISL95311 fn8084 rev 2.00 page 6 of 12 august 13, 2015 sda vs scl timing a0, a1 pin timing pin descriptions potentiometer pins r h and r l r l and r h are referenced to the r elative posit ion of the wiper and not the voltage pote ntial on the terminals. with wr set to 127, the wiper will be closest to r h , and with the wr set to 00, the wip er is closest to r l . r w r w is the wiper terminal and is equivalent to the movable terminal of a mechanical potenti ometer. the position of the wiper within the array is determined by the wr. bus interface pins serial data input/output (sda) the sda is a bidirectional serial data input/output pin for the i 2 c interface. it receives device address, operation code, wiper register address and data from a i 2 c external master device at the rising edge of the serial clock scl, and it shift s out data after each falling e dge of the serial clock scl. sda requires an external pull-up resistor, since its an open drain input/output. serial clock (scl) this input is the serial clock of the i 2 c serial interface. scl requires an external pull- up resistor, since its an open drain input. device address (a1Ca0) the address inputs are used to set the least significant 2 bits of the 8-bit i 2 c interface slave addre ss. a match in the slave address serial data stream m ust be made with the address input pins in order to initia te communication with the ISL95311. a maximum of four ISL95311 devices may occupy the i 2 c serial bus. principles of operation the ISL95311 is an integrated circuit incorporating one dcp with their associated register, non-volatile memory, and a i 2 c serial interface providing direct communication between a host and the potentiometers and memory. t he resistor array is comprised of 127 indiv idual resistors connected in series. at either end of the arra y and between e ach resistor is an electronic swit ch between that poi nt and the wiper. the wiper, when at either fixe d terminal, act s like its mechanical equivalent and does not move bey ond the last position. that is, the counte r does not wrap around when clocked to either extreme. the electronic switches on the device operat e in a make before break mode when the w iper changes tap positions. when the device is powered-dow n, the last wiper position stored will be maintained in t he nonvolatile memory. when power is restored, the contents of the memory are recalled and the wiper is set to the value last stored. t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t hd:a scl sda in a0, a1 t su:a clk 1 start stop
ISL95311 fn8084 rev 2.00 page 7 of 12 august 13, 2015 on applying power to the ISL95311, the v cc supply should have a monotonic ramp to the sp ecified operating voltage. it is important that once v cc reaches 1v that it increases to at least 2.5v in less than 7.5ms (0.2v/ms ). the ramp rate before and after these thresholds is not important. v cc must be applied prior to, or simultaneously, with v+. under no condition should v+ be applied without v cc . while the sequence of applying v+ and v cc to the ISL95311 does not affect the proper recall of the wiper position, applying v+ before v cc powers the electronic switches of the dcp before the electronic switch control signals are applied. this can result in multiple electr onic switches being turned on, which could load the power supply and cause brief, unexpected potentiomet er wiper settings. to prevent unknown wiper pos itions on the ISL95311 on power-down, it is recommended that v+ turn off before or simultaneously with v cc . if v+ remains on after v cc turns off, the wiper position can remain unchanged from its previous setting or it can go to an undefined state. dcp description the dcp is implemented with a combination of resistor elements and cmos switches. the physical ends of the dcp are equivalent to the fix ed terminals of a mechanical potentiometer (r h and r l pins). the r w pin is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiomete r. the position of the wiper terminal within the dcp is controlled by a 7-bit volatile wiper register (wr). when the wr c ontains all zeroes (00h), the wiper terminal (r w ) is closest to its low terminal (r l ). when the wr contains all ones (7fh), the wiper terminal (r w ) is closest to its high terminal (r h ). as the value of the wr increases from all zeroes ( 00h) to all ones (7fh), the wiper moves monotonically from the position closest to r l to the position closest to r h . at the same time, the resistance between r w and r l increases monotonically, while the resistance between r h and r w decreases monotonically. while the ISL95311 is being powered up, the wr is reset to 20h (64 decimal), which locates the r w at the center between r l and r h . soon after the power supply voltage becomes large enough for reliable non- volatile memory reading, the ISL95311 reads the value stored on a non-volatile initial value register (ivr) and l oads it into the wr. the wr and ivr can be read from or written to directly using the i 2 c serial interface as described in the following sections. memory description the ISL95311 contains 1 non-volatile byte know as the initial value register (ivr). it is accessed by the i 2 c interface operations with addr ess 00h. the ivr contains the value which is loaded into the volatile wiper register (wr) at power-up. the volatile wr, and the non -volatile ivr of a dcp are accessed with the same address. the access control r egister (acr) dete rmines which word at address 00h is a ccessed (ivr or wr ). the volatile acr must be set as follows: when the acr is all zeroes, wh ich is the default at power-up: ? a read operation to address 0 outputs the value of the non-volatile ivr. ? a write operation to address 0 writes the id entical values to the wr and ivr of the dcp. ? when the acr is 80h: ? a read operation to address 0 outputs the value of the volatile wr. ? a write operation to add ress 0 only writes to the volatile wr. it is not possible to write to an ivr without writing the same value to its wr. 00h and 80h are the only value s that should be written to address 2. all other values a re reserved an d must not be written to address 2. the ISL95311 is pre-progr ammed with 40h in the ivr. i 2 c serial interface the ISL95311 supports a bidirec tional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the tr ansfer is a master and the device being controlled is t he slave. the master always initiates data transfers and p rovides the clock for both transmit and receive operatio ns. therefore, the ISL95311 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of eac h byte of data first. protocol conventions data states on the sda lin e can change onl y during scl low periods. sda state cha nges during scl high are reserved for indicating star t and stop conditions (see figure 1). on power-up of the i sl95311, the sda pin is in the input mode. all i 2 c interface operations m ust begin with a start condition, which is a high to l ow transition of sda while table 1. memory map address non-volatile volatile 2-acr 1 reserved 0ivrwr wr: wiper register, ivr: initial value register.
ISL95311 fn8084 rev 2.00 page 8 of 12 august 13, 2015 scl is high. the ISL95311 cont inuously monitors the sda and scl lines for the start condition and does not respond to any command unt il this condition is met (see figure 1). a start condition is ignored during the power-up sequence and during internal n on-volatile write cycles. all i 2 c interface operations mus t be terminated by a stop condition, which is a low to h igh transition of sda while scl is high (see figure 1). a stop condition at the end of a read operation, or at the end of a write operation to volatil e bytes only places th e device in its standby mode. a stop condition during a wr ite operation to a n on-volatile byte, initiates an internal non-volatile write cycle. the device enters its standby state when t he internal non-volatile write cycle is completed. an ack, acknowledge, is a s oftware convention used to indicate a succe ssful data transfer. the transmitting device, either master or slave, re leases the sda bus after transmitting eight b its. during the nint h clock cycl e, the receiver pulls the sda l ine low to acknowledge the reception of the eight bits of data (see figure 2). the ISL95311 responds with an ack after recognition of a start condition followed by a va lid identification byte, and once again after successful receipt of an address byte. the ISL95311 also responds with an ack after receiving a data byte of a write operation. t he master must r espond with an ack after receiving a data byte of a read operation a valid identification byte cont ains 01010 as the five msbs, and the following two bits match ing the logic values present at pins a1, and a0. the lsb is in the read/write bit. its value is 1 for a read oper ation, and 0 for a write operation (see table 2.) write operation a write operation requires a sta rt condition, followed by a valid identification byte, a vali d address byte, a data byte, a nd a stop condition (see figure 3). after each of t he three bytes, the ISL95311 responds with an ack. at this time, if the data byte is to be written only to v olatile registers, then the devi ce enters its standby stat e. if the data byte is to be written als o to non-volatile memory, t he ISL95311 begins its internal write cycle to non-volatile memory. dur ing the internal non-volatile write cycle, the device ignores transitions at the sda and scl pins, and the sda out put is at a high im pedance state. when the internal non-volat ile write cycle is com pleted, t he isl9531 1 enters its standby state. the byte at address 02h determines if the data byte is to be written to volatile and/or non- volatile memory (see memory description on page 7). data protection a stop condition also acts as a protection o f non-volatile memory. a valid identification byte, address byte, and total number of scl pulses act as a protection of both volatile and non-volatile registers. d uring a write sequence, the data byte is loaded into an inte rnal shift register as it is received. if the address byte is 0 or 2, the data byte is transferred to the wiper reg ister (wr) or to the access control register respectively, a t the falling edge of the scl pulse that loads the last bit (lsb) of the data byte. if the address byte is 0, and the a ccess control re gister is all zeros (default), then the stop c ondition initiates the internal write cycle to non- volatile memory. read operation a read operation consists o f a three byte instruction followed by one or more data bytes (see figure 4). the master initiates the opera tion issuing the following sequence: a start, the identif ication byte with the r/w bit set to 0, an addre ss byte, a second sta rt, and a second identification by te with the r/w bit set to 1. after each of the three bytes, the ISL95311 responds with an ack; then the ISL95311 transmits the data byte. the master then terminates the read operation (issuing a stop condition) following the last b it of the data byte (see figure 4). the byte at address 02h determines if the data bytes being read are from volatile or non-volatile memory. (see memory description on page 7.) 01010a1a0r/w (msb) (lsb) table 2. dentification byte format logic values at pins a1, and a0 respectively
ISL95311 fn8084 rev 2.00 page 9 of 12 august 13, 2015 figure 1. valid data changes, start, and stop conditions figure 2. acknowledge response from receiver figure 3. byte write sequence figure 4. read sequence sda scl start data data stop stable change data stable sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance s t a r t s t o p identification byte address byte data byte a c k signals from the master signals from the ISL95311 a c k 00 11 a c k write signal at sda 0000 a 1 0 0 00 a 0 0 6,*1$/6 )5207+( 0$67(5 6,*1$/6)520 7+(6/$9( 6,*1$/$76'$ 6 7 $ 5 7 ,'(17,),&$7,21 %<7(:,7+ 5: $''5(66 %<7( $ & . $ & . 00 11 s t o p a c k 01 0 11 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 00 0 000 00 0a 1 a 0 0 a 1 a 0
ISL95311 fn8084 rev 2.00 page 10 of 12 august 13, 2015 communicating with the ISL95311 there are 3 register addresses in the ISL95311, of which two can be used. address 00h and address 02h are used to control the device. address 0 1h is reserved and should not be used. address 00h contains t he nonvolatile initial value register (ivr), and the vol atile wiper register (wr). address 02h contains only a vola tile word and is used as a pointer to either the iv r or wr. see table 1. register descriptions: access control the access control register ( acr) is volat ile and is at address 02h. it is 8-bits, and on ly the msb is significant, all other bits should be zero (0). the acr controls which word is accessed at register 00h as follows: 00h = nonvolatile ivr 80h = volatile wr all other bits of the acr should be writt en to as zeros. only the msb can be either 0 or 1 . power-up default for this address is 00h. register description: ivr and wr the ISL95311 has a single potent iometer. the wiper of the potentiometer is controlled directly by the wr. writes and reads can be made directly to t his register to control and monitor the wiper position wi thout any nonvol atile memory changes. this is done by setti ng address 02h to data 80h, then writing the data. the nonvolatile ivr s tores the power-up va lue of the wiper. on power-up, the contents of th e ivr are transferred to the wr. to write to the ivr, first addr ess 02h is set to data 00h, then the data is written. writing a new value to the ivr register will set a new power-up position for the wiper. also, writing t o this register will load the same value into the wr as the ivr. so, if a new value is loaded in to the ivr, not only will the non-volatile ivr change, but t he wr will also contain the same value after t he write, and the wiper position will change. reading from the ivr will not change the wr, if its contents are different. example 1 writing a new value (77h) to the ivr: (note that the wr will also refl ect this new value since both r egisters get written to at the same time) example 2 reading from the wr: notes: a = acknowledge, x = data bit read write to acr first 01010000a00000010a00000000a then, write to ivr 01010000a00000000a01110111a write to the acr first (to index the wr) 01010000a00000010a00000010a then, set the wr address 01010000a00000000a read from the wr 01010001axxxxxxx x
fn8084 rev 2.00 page 11 of 12 august 13, 2015 ISL95311 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2005-2015. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's produc ts address some of the largest marke ts within the industrial and i nfrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application no tes, related documentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggesti ons for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also a vailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change august 13, 2015 fn8084.2 updated ordering information table on page 1. added revision history and about intersil sections. updated pod m10.118 to latest rev. changes: updated to new pod template. added land pattern
ISL95311 fn8084 rev 2.00 page 12 of 12 august 13, 2015 package outline drawing m10.118 10 lead mini small outline plastic package rev 1, 4/12 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.18 - 0.27 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 10 0.85010 seating plane a 0.50 bsc 3.00.05 4.90.15 (0.29) (1.40) (0.50) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-ba plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m

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Price & Availability of ISL95311

Part #	Manufacturer	Description	Price	BuyNow Qty.
ISL95311WIU10Z 57K4486	Renesas Electronics Corporation	Ic, digital Potentiometer, cmos, tssop,10Pin, plastic Rohs Compliant: Yes \|Renesas ISL95311WIU10Z	250: USD2.11	0
ISL95311WIU10Z-TK 57K4487	Renesas Electronics Corporation	Nv Digital Potentiometer, Full Reel; End To End Resistance:10Kohm; No. Of Pots:Single; Control Interface:I2C; Track Taper:Linear; Resistance Tolerance:± 20%; Supply Voltage Min:2.7V; Supply Voltage Max:5.5V; No. Of Pins:10Pins; Msl:-Rohs Compliant: Yes \|Renesas ISL95311WIU10Z-TK		0
ISL95311WIU10Z-TK 65T7377	Renesas Electronics Corporation	Nv Digital Potentiometer; End To End Resistance:10Kohm; Control Interface:I2C; Track Taper:Linear; Resistance Tolerance:± 20%; Supply Voltage Min:2.7V; Supply Voltage Max:5.5V; Potentiometer Ic Case Style:Msop; No. Of Pins:10Pins Rohs Compliant: Yes \|Renesas ISL95311WIU10Z-TK		0

Part #	Manufacturer	Description	Price	BuyNow Qty.
ISL95311WIU10Z-TK	Renesas Electronics Corporation			570

Part #	Manufacturer	Description	Price	BuyNow Qty.
ISL95311WIU10ZTK	Intersil Corporation	Digitally Controlled Potentiometer (XDCP), Digital Potentiometer, 1 Func, 10000ohm, 128 Positions, CMOS, PDSO10		345

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