cystech electronics corp. spec. no. : c096n3 issued date : 2015.11.24 revised date : page no. : 1/9 mte1k8n15n3 cystek product specification 150v n-channel enhancement mode mosfet MTE1K8N15KN3 bv dss 150v i d @v gs =10v, t a =25 c 0.7a 1.07(typ.) r dson @v gs =10v, i d =0.5a features r dson @v gs =10v, i d =1a 1.15(typ.) ? low on-resistance ? excellent thermal and electrical capabilities ? compact and low profile sot-23 package ? pb-free lead plating and halogen-free package ? esd protected gate equivalent circuit outline ordering information device package shipping MTE1K8N15KN3-0-t1-g sot-23 (pb-free lead plating and halogen-free package) 3000 pcs / tape & reel MTE1K8N15KN3 sot-23 d g gate s g s source d drain environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t1 : 3000 pcs / tape & reel,7? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c096n3 issued date : 2015.11.24 revised date : page no. : 2/9 mte1k8n15n3 cystek product specification absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source voltage v ds 150 gate-source voltage v gs 20 v continuous drain current @ t a =25 c, v gs =10v (note 3) 0.7 continuous drain current @ t a =70 c, v gs =10v (note 3) i d 0.56 pulsed drain current (note 1, 2) i dm 4 a maximum power dissipation @ t a =25 w (note 3) 1.38 w linear derating factor p d 0.01 w/ c thermal resistance, junction-to-ambient (note 3) r th,ja 90 c/w operating junction and storage temperature range tj, tstg -55~+150 c note : 1. pulse width limited by maximum junction temperature. 2. pulse width 300 s, duty cycle 2%. 3. surface mounted on fr-4 board, t 10sec. electrical characteristics (ta=25 c) symbol min. typ. max. unit test conditions static bv dss 150 - - v gs =0v, i d =250 a v gs(th) 2.0 - 4.0 v v ds =v gs , i d =250 a i gss - - 2 10 v gs = 2 20v, v ds =0v - - 1 v ds =120v, v gs =0v i dss - - 25 a v ds =120v, v gs =0v, tj=70 c - 1.07 1.8 v gs =10v, i d =0.5a *r ds(on) - 1.15 1.8 v gs =10v, i d =1a *g fs - 1.13 - s v ds =15v, i d =1a dynamic ciss - 93 - coss - 17 - crss - 11 - pf v ds =25v, v gs =0v, f=1mhz t d(on) - 15.6 - t r - 34.8 - t d(off) - 79.4 - t f - 41.8 - ns v ds =75v, i d =1a, v gs =10v, r g =6 qg - 3.8 - qgs - 0.7 - qgd - 1.0 - nc v ds =120v, i d =1a, v gs =10v source-drain diode *v sd - 0.83 1.2 v v gs =0v, i s =1a trr - 26.3 - ns qrr - 23.3 - nc i f =1a, di f /dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c096n3 issued date : 2015.11.24 revised date : page no. : 3/9 mte1k8n15n3 cystek product specification typical characteristics typical output characteristics 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0 5 10 15 20 v ds , drain-source voltage(v) i d , drain current (a) 10v 9v 8v 7v v gs =4v 5v 4.5v 5.5v 6v brekdown voltage vs ambient temperature 0.4 0.6 0.8 1.0 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.01 0.1 1 10 i d , drain current(a) r ds(on) , static drain-source on-state resistance() v gs =10v v gs =4.5v v gs =6v v gs =5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1.0 1.2 0123 i dr , reverse drain current(a) v sd , source-drain voltage(v) 4 tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0.0 2.0 4.0 6.0 8.0 10.0 024681 0 v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance() i d =0.5a drain-source on-state resistance vs junction tempearture 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =0.5a r ds( on) @tj=25c : 1.07 typ.
cystech electronics corp. spec. no. : c096n3 issued date : 2015.11.24 revised date : page no. : 4/9 mte1k8n15n3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 1 10 100 1000 0 5 10 15 20 25 30 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1.0 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 i d , drain current(a) g fs , forward transfer admittance(s) ta=25c pulsed v ds =15v v ds =10v gate charge characteristics 0 2 4 6 8 10 012345 qg, total gate charge(nc) v gs , gate-source voltage(v) i d =1a v ds =120v v ds =75v maximum safe operating area 0.001 0.01 0.1 1 10 0.1 1 10 100 1000 v ds , drain-source voltage(v) i d , drain current(a) t a =25c, tj=150c v gs =10v, r ja =90c/w single pulse dc 100ms r dson limited 1s 100 s 1ms 10ms maximum drain current vs junction temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 25 50 75 100 125 150 175 tj, junction temperature(c) i d , maximum drain current(a) t a =25 c, v gs =10v, r ja =90c/w
cystech electronics corp. spec. no. : c096n3 issued date : 2015.11.24 revised date : page no. : 5/9 mte1k8n15n3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0246810 v gs , gate-source voltage(v) i d , drain current(a) v ds =10v single pulse power rating, junction to ambient 0 50 100 150 200 250 300 350 0.0001 0.001 0.01 0.1 1 10 100 pulse width(s) power (w) t j(max) =150c t a =25c r ja =90c/w transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =90 c/w
cystech electronics corp. spec. no. : c096n3 issued date : 2015.11.24 revised date : page no. : 6/9 mte1k8n15n3 cystek product specification recommended soldering footprint
cystech electronics corp. spec. no. : c096n3 issued date : 2015.11.24 revised date : page no. : 7/9 mte1k8n15n3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c096n3 issued date : 2015.11.24 revised date : page no. : 8/9 mte1k8n15n3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c096n3 issued date : 2015.11.24 revised date : page no. : 9/9 mte1k8n15n3 cystek product specification sot-23 dimension marking: te date code kn15 xx device code style: pin 1.gate 2.source 3.drain 3-lead sot-23 plastic surface mounted package cystek package code: n3 inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.1102 0.1204 2.80 3.04 j 0.0032 0.0079 0.08 0.20 b 0.0472 0.0669 1.20 1.70 k 0.0118 0.0266 0.30 0.67 c 0.0335 0.0512 0.89 1.30 l 0.0335 0.0453 0.85 1.15 d 0.0118 0.0197 0.30 0.50 s 0.0830 0.1161 2.10 2.95 g 0.0669 0.0910 1.70 2.30 v 0.0098 0.0256 0.25 0.65 h 0.0000 0.0040 0.00 0.10 l1 0.0118 0.0197 0.30 0.50 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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