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8- channel dac with pll and single - ended outputs, 192 khz, 24 bit s data sheet ad1934 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. te l: 781.329.4700 ? 2007 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features pll generated or direct master clock low emi design 108 db dac dynamic ran ge and snr ? 94 db thd + n single 3.3 v s upply tolerance for 5 v logic inputs supports 24 bits and 8 khz to 192 khz sample rates single - ended dac output log volume control w ith auto ramp function spi ? c ontrollable for flexibility software - controllable clickless mute software power - down right - justified, left - justified, i 2 s, and tdm m odes master and slave modes up to 16 - channel in/out 48- lead lqfp qualified for automotive applic ations applications automotive audio systems home theater sy stems set - top boxes digital audio effects processors g eneral description the ad 1934 is a high performance, single chip that provide s eight digital - to - analog converters ( dacs ) with single - ended o utput using the analog devices, inc. , patented mult ibit sigma - delta ( - ) architecture. an spi port is included, allowing a microcontroller to adjust volume and many other parameters. the ad 1934 operates from 3.3 v digital and analog supplies. the ad 1934 is available in a 48 - lead ( single- ended output) l q f p. other members of this family include a d ifferential dac output version. the a d 1934 is designed for low emi. this consideration is apparent in both the system and circuit design architectures. by using t he on - board pll to derive the master clock from the lr c lock or from an external crystal, the ad 1934 eliminate s the need for a separate high frequency master clock and can also be use d with a suppressed bit clock. the dac s are designed using the latest ana log devices continuous time architectures to further minimize emi. by using 3.3 v supplies, power consumption is minimized , further reducing emissions. functional block dia gram 06106-001 serial data port precision voltage reference timing management and control (clock and pll) control port spi control data input/output ad1934 digital audio input/output sdatain clocks analog audio outputs 6.144mhz dac dac dac dac dac dac dac dac digital filter and volume control figure 1.
ad1934 data sheet rev. d | page 2 of 29 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 4 test conditions ............................................................................. 4 analog performance specifications ........................................... 4 crystal oscillator specifications................................................. 5 digital input/output specifications........................................... 5 power supply specifications........................................................ 6 digital filters ................................................................................. 7 timing specifications .................................................................. 7 absolute maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 theory of operation ...................................................................... 13 digital-to-analog converters (dacs) .................................... 13 clock signals ............................................................................... 13 reset and power-down ............................................................. 13 serial control port ..................................................................... 14 power supply and voltage reference ....................................... 15 serial data portsdata format ............................................... 15 time-division multiplexed (tdm) modes ............................ 15 daisy-chain mode ..................................................................... 17 control registers ............................................................................ 21 definitions ................................................................................... 21 pll and clock control registers ............................................. 21 dac control registers .............................................................. 22 auxiliary tdm port control registers ................................... 24 additional modes ....................................................................... 24 application circuits ....................................................................... 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 automotive products ................................................................. 27 revision history 2/13rev. c to rev. d changes to t clh comments, table 7 ............................................... 6 changes to serial control port section ....................................... 13 7/11rev. b to rev. c deleted references to i 2 c ............................................. throughout changes to figure 2 and table 10, dsdatax/auxdata1 pin descriptions ...................................................................................... 9 1/11rev. a to rev. b added automotive information .................................. throughout change to table 2, introductory text ............................................ 4 change to table 4, introductory text ............................................ 4 change to table 7, introductory text ............................................ 6 changes to ordering guide .......................................................... 26 9/09rev. 0 to rev. a change to title ................................................................................... 1 change to table 11 ......................................................................... 13 change to power supply and voltage reference section .......... 14 updated outline dimensions ....................................................... 26 changes to ordering guide .......................................................... 26 8/07revision 0: initial version
data sheet ad1934 rev. d | page 3 of 28 specifications test conditions performance of all channels is identical , exclusive of the int er channel gain mism atch and inter channel phase deviatio n specifications. supply voltages (avdd, dvdd) 3.3 v t emperature r ange 1 as specified in table 1 and table 2 master c lock 12.288 mhz (48 khz f s , 256 f s m ode) input sample ra te 48 khz measurement b andwidth 20 hz to 20 khz word w idth 24 b its load capacitance (digital ou tput) 20 pf load current (digital ou tput ) 1 ma or 1.5 k? to ? dvdd supply input v oltage hi 2.0 v input v oltage lo 0.8 v 1 functionally guaranteed at ?40c to +125c case temperature. analog performance specifications specifications guaranteed at 25 c (ambient) . table 1 . parameter test conditions /comments min typ max unit digital - to - analog converters dynamic range 20 hz to 20 khz, ? 60 db i nput no filter (rms) 98 10 4 db with a - weighted filter (rms) 100 106 db with a - weighted filter (av erage ) 108 db total harmonic distortion + noise 0 dbfs single - ended ver sion two channels running ? 92 db eight channels runnin g ?86 ?75 db full - scale output voltage 0.88 (2.48) v rms (v p -p) gain error ?10 +10 % interchannel gain mismatch ?0.2 +0.2 db offset error ? 16 ?4 + 16 mv gain drift ?30 + 30 ppm/c interchannel isolation 100 db interchannel phase deviati on 0 degrees volume control step 0.375 db volume control range 95 db de -e mphasis gain error 0.6 db output resistance at each pin 100 ? reference internal reference voltage filtr pin 1.50 v external reference voltage filtr pin 1.32 1.50 1.68 v common - mode ref erence output cm pin 1.50 v
ad1934 data sheet rev. d | page 4 of 28 specifications measured at 125c (case). table 2. parameter test conditions/comments min typ max unit digital-to-analog converters dynamic range 20 hz to 20 khz, ?60 db input no filter (rms) 98 104 db with a-weighted filter (rms) 100 106 db with a-weighted filter (average) 108 db total harmonic distortion + noise 0 dbfs single-ended version two channels running ?92 db eight channels running ?86 ?70 db full-scale output voltage 0.8775 (2.482) v rms (v p-p) gain error ?10 +10 % interchannel gain mismatch ?0.2 +0.2 db offset error ?16 ?4 +16 mv gain drift ?30 +30 ppm/c reference internal reference voltage filtr pin 1.50 v external reference voltage filtr pin 1.32 1.50 1.68 v common-mode reference output cm pin 1.50 v crystal oscillator specifications table 3. parameter min typ max unit transconductance 3.5 mmhos digital input/output specifications ?40c < t c < 125c, dvdd = 3.3 v 10%. table 4. parameter test conditions/comments min typ max unit input voltage hi (v ih ) 2.0 v input voltage hi (v ih ) mclki pin 2.2 v input voltage lo (v il ) 0.8 v input leakage i ih @ v ih = 2.4 v 10 a i il @ v il = 0.8 v 10 a high level output voltage (v oh ) i oh = 1 ma dvdd ? 0.60 v low level output voltage (v ol ) i ol = 1 ma 0.4 v input capacitance 5 pf
data sheet ad1934 rev. d | page 5 of 28 power suppl y specifications table 5. para meter test conditions/comments min typ max unit supplies voltage dvdd 3.0 3.3 3.6 v avdd 3.0 3.3 3.6 v digital current mclk = 256 f s normal operation f s = 48 khz 56 ma f s = 96 khz 65 ma f s = 192 khz 95 ma power - down f s = 4 8 khz to 192 khz 2.0 ma analog current normal operation 74 ma power - down 23 ma dissipation operation mclk = 256 f s , 48 khz all supplies 429 mw digital supply 185 mw analog supply 244 mw power - down , all supplies 83 mw power supply rejection ratio signal at analog supply pins 1 khz , 200 mv p -p 50 db 20 khz , 200 mv p -p 50 db
ad1934 data sheet rev. d | page 6 of 28 digital filters table 6 . parameter mode factor min typ max unit dac interpolation filter pass b and 48 khz m ode, t yp @ 48 khz 0.4535 f s 22 khz 96 khz m ode, t yp @ 96 khz 0.3646 f s 35 khz 192 khz m ode, t yp @ 192 khz 0.3646 f s 70 khz pass - band ripple 48 khz mode, t yp @ 48 khz 0.01 db 96 khz mode, t yp @ 96 khz 0.05 db 192 khz mode, ty p @ 192 khz 0.1 db transition band 48 khz mode, ty p @ 48 khz 0.5 f s 24 khz 96 khz mode, ty p @ 96 khz 0.5 f s 48 khz 192 khz mode, t yp @ 192 khz 0.5 f s 96 khz stop band 48 khz mode, ty p @ 48 khz 0.5465 f s 26 khz 96 khz mode, ty p @ 96 k hz 0.6354 f s 61 khz 192 khz mode, ty p @ 192 khz 0.6354 f s 122 khz stop - band attenuation 48 khz mode, t yp @ 48 khz 70 db 96 khz mode, ty p @ 96 khz 70 db 192 khz mode, t yp @ 192 khz 70 db group delay 48 khz mode, ty p @ 48 khz 25/ f s 521 s 96 khz mode, ty p @ 96 khz 11/ f s 115 s 192 khz mode, ty p @ 192 khz 8/ f s 42 s timing specification s ?40c < t c < 1 25 c, dvdd = 3.3 v 10%. table 7. parameter condition comments min max unit i nput master clock (mclk) and reset t mh mclk duty cycle dac clock source = pll clock @ 256 f s , 384 f s , 512 f s , 768 f s 40 60 % t mh dac clock source = d irect mclk @ 512 f s (b ypass on - chip pll) 40 60 % f mclk mclk f requency pll mode, 256 f s reference 6.9 13.8 mhz f mclk dir ect 512 f s mode 27.6 mhz t pdr rst l ow 15 ns t pdrr rst r ecovery reset to active output 4096 t mclk pll lock t ime mclk and lrclk input 10 ms 256 f s vco clock , output duty cycle mclko pin 40 60 % spi por t see figure 9 t cch cclk high 35 ns t ccl cclk low 35 ns f cclk cclk frequency f cclk = 1/t ccp , only t ccp shown in figure 9 10 mhz t cds cdata setup to cclk risin g 10 ns t cdh cdata hold from cclk rising 10 ns t cls clatch setup to cclk rising 10 ns t clh clatch hold from cclk rising 10 ns t clh igh clatch high not shown in figure 9 10 ns t coe cout enable from cclk falling 30 ns t cod cout delay from cclk falling 30 ns t coh cout hold from cclk falling, not shown in figure 9 30 ns t cots cout tri - state from cclk falling 30 ns
data sheet ad1934 rev. d | page 7 of 28 parameter condition comments min max unit dac serial port see figure 16 t dbh dbclk high slave mode 10 ns t dbl dbclk l ow slave mode 10 ns t dls dlrclk setup to dbclk rising, slave mode 10 ns t dlh dlrclk hold from dbclk rising, slave mode 5 ns t dls dlrclk skew from dbclk falling, master mode ?8 +8 ns t dds dsdata setup to dbclk rising 10 ns t ddh dsdata hold from dbclk rising 5 ns auxtdm serial port see figure 17 t abh auxtdmbclk high slave mo de 10 ns t abl auxtdmbclk low slave mode 10 ns t als auxtdmlrclk setup to auxtdmbclk rising, slave mode 10 ns t alh auxtdmlrclk hold from auxtdmbclk rising, slave mode 5 ns t als auxtdmlrclk skew from auxtdmbclk falling, master mode ? 8 +8 ns t dds dsda ta setup to auxtdmbclk, not shown in figure 17 10 ns t ddh dsdata hold from auxtdmbclk rising, not shown in figure 17 5 ns auxiliary interface t dxdd auxdata delay from auxbclk falling 18 ns t xbh auxbclk high 10 ns t xbl auxbclk low 10 ns t dls auxlrclk setup to auxbclk rising 10 ns t dlh auxlrclk hold from auxbclk rising 5 ns
ad1934 data sheet rev. d | page 8 of 28 absolute maximum ratings table 8. parameter rating analog (avdd) ?0.3 v to +3.6 v digital (dvdd) ?0.3 v to +3.6 v input current (except supply pins) 20 ma analog input voltage (signal pins) ?0.3 v to avdd + 0.3 v digital input voltage (signal pins) ?0.3 v to dvdd + 0.3 v operating temperature range (case) ?40c to +125c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja represents thermal resistance, junction-to-ambient; jc represents the thermal resistance, junction-to-case. all characteristics are for a 4-layer board. table 9. thermal resistance package type ja jc unit 48-lead lqfp 50.1 17 c/w esd caution
data sheet ad1934 rev. d | page 9 of 28 pin configuration and function descriptions 06106-020 avdd 48 lf 47 nc 46 nc 45 nc 44 nc 43 nc 42 nc 41 nc 40 nc 39 cm 38 avdd 37 dvdd 13 dsdata3 14 dsdata2 15 dsdata1 16 dbclk 17 dlrclk 18 auxdata1 19 nc 20 auxtdmbclk 21 auxtdmlrclk 22 cin 23 cout 24 agnd 1 mclki/xi 2 mclko/xo 3 agnd 4 avdd 5 ol3 6 or3 7 ol4 8 or4 9 pd/rst 10 dsdata4 11 dgnd 12 agnd 36 filtr 35 agnd 34 avdd 33 agnd 32 or2 31 ol2 30 or1 29 ol1 28 clatch 27 cclk 26 dgnd 25 ad1934 top view (not to scale) single-ended output nc = no connect figure 2. pin configuration table 10. pin function description pin o. in put/ut put mnemonic description 1 i agnd analog ground. 2 i mclki/xi master clock input/ cryst al oscillator input. 3 o mclk o /xo master clock output/ crystal oscillator output. 4 i agnd analog ground. 5 i avdd analog power supply. connect to analog 3.3 v supply. 6 o ol3 dac 3 left output. 7 o or3 dac 3 right output. 8 o ol4 dac 4 left output. 9 o or4 dac 4 right output. 10 i pd / rst power - down reset (active low). 11 i/o dsdata4 dac serial data input 4. data input to dac4 data in/tdm dac2 data out (dual - line mode)/aux dac2 data out (to external dac2). 12 i d gnd digital ground. 13 i dvdd digital power supply. connect to digital 3.3 v supply. 14 i/o dsdata3 dac serial data input 3. data input to dac3 data in/tdm dac2 data in (dual - line mode)/aux not used. 15 i/o dsdata2 dac serial data input 2. data input to dac2 data in/tdm dac2 data out/aux not used. 16 i dsdata1 dac serial data input 1. data input to dac1 data in/tdm dac data in/aux tdm data in. 17 i/o dbclk bit clock for dacs (regular stereo, tdm , or daisy - chain tdm mode). 18 i/o dlrclk lr clock for da cs (regular stereo, tdm , or daisy - chain tdm mode). 19 o auxdata1 aux dac1 data out (to external dac1). 20 nc no connect. 21 i/o auxtdmbclk auxiliary mode only dac tdm bit clock. 22 i/o auxtdmlrclk auxiliary mode only dac lr tdm clock. 23 i cin/adr0 control data input (spi) . 24 i/ o cout/sda control data output (spi) . 25 i dgnd digital ground.
ad1934 data sheet rev. d | page 10 of 28 pin no. in put/out put mnemonic description 26 i cclk/scl control clock input (spi) . 27 i clatch /adr1 latch input for control data (spi ). 28 o ol1 dac 1 left output. 29 o or1 dac 1 right output. 30 o ol2 dac 2 left output. 31 o or2 dac 2 right output. 32 i agnd analog ground. 33 i avdd analog power supply. connect to analog 3.3 v supply. 34 i agnd analog ground. 35 o f i ltr voltage reference filter capacitor connection. bypass w ith 10 f||100 nf to agnd. 36 i agnd analog ground. 37 i avdd analog power supply. connect to analog 3.3 v supply. 38 o cm common - mode reference filter capacitor connection. bypass with 47 f||100 nf to agnd. 39 to 46 nc must be tied to common mode, p in 38 . alternately, ac - couple d to g round . 47 o lf pll loop filter . return to avdd. 48 i avdd analog power supply. connect to analog 3.3 v supply.
data sheet ad1934 rev. d | page 11 of 28 typical performance characteristics 0.06 0.04 0.02 ?0.06 ?0.04 ?0.02 0 0 24 16 8 magnitude (db) frequency (khz) 06106-004 figure 3 . dac pass -b and filter response , 48 khz 0 ?150 ?100 ?50 0 48 12 24 36 magnitude (db) frequency (khz) 06106-005 figure 4 . dac stop -b and filter response, 48 khz 0.10 ?0.10 ?0.05 0 0.05 0 96 72 48 24 magnitude (db) frequency (khz) 06106-006 figure 5 . dac pass -b and filter response, 96 khz 0 ?150 ?100 ?50 0 96 24 48 72 magnitude (db) frequency (khz) 06106-007 figure 6 . dac stop -b and filter response, 96 khz 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 64 8 16 32 magnitude (db) frequency (khz) 06106-008 figure 7 . dac pass -b and filter response, 192 khz ?10 ?8 ?6 ?4 ?2 0 48 96 64 80 magnitude (db) frequency (khz) 06106-009 figure 8 . dac stop -b and filter response, 192 khz
ad1934 data sheet rev. d | page 12 of 28 theory of operation digital - to - analog converters ( dac s) the ad 1934 dac channels are arranged as single- ended, fo ur stereo pa irs giving eight analog outputs for minimum external components. the dacs include on - board digital reconstruction filters with 70 db stop - band attenuation and linear phase response, operating at an oversampling ratio of 4 (48 khz or 96 khz mode s) or 2 (192 khz mode). each channel has its own independently programmable attenuator, adjustable in 255 steps in increments of 0.375 db. digital inputs are supplied through four serial data input pins (one for each stereo pair) and a common frame (dlrclk ) and bit (dbclk) clock. alternatively, one of the tdm modes can be used to access up to 16 channels on a si ngle tdm data line. each output pin has a nominal common - mode dc level of 1.5 v and swings 1.27 v for a 0 dbfs digital input signal. a single op am p, third - order , external , low - pass filter is recommended to remove high frequency noise present on the output pins . t he use of op amps with low slew rate or low bandwidth can cause high frequency noise and tones to fold down into the audio band; therefore, exercise care in selecting these components. the voltage at cm, the common - mode reference pin, can be used to bias the external op amps that buffer the output signals (see the power supply and voltage reference se ction). clock signals the on - chip phase locked lo op (pll) can be selected to reference the input sample rate from either of the lrclk pins or 256, 384, 512, or 768 times the sample rate, referenced to the 48 khz mode from the mclki pin. the default at pow er - up is 256 f s from mclki pin . in 96 khz mode, the master clock frequency stay s at the same absolute frequency ; therefore, the actual multiplication rate is divided by 2. in 192 khz mode, the actual multiplication rate is divided by 4. for example, if a device in the ad 1934 family is programmed in 256 f s mode, the frequency of the master clock input is 256 48 khz = 12.288 mhz. if the ad 1934 is then switched to 96 khz operation (by writing to the spi port), the frequency of the master clock should re main at 12.288 mhz, which is now 128 f s . in 192 khz mode, this be comes 64 f s . the internal clock for the dacs varies by mode: 512 f s (48 khz mode), 256 f s (96 khz mode), or 128 f s (192 khz mode). by default, the on - board pll generate s this intern al master clock from an external clock. a direct 512 f s ( referenced to 48 khz mode) master clock can be used for dacs if selected in pll and clock control 1 register. the pll can be powered down in pll and clock control 0 register . to ensure reliable lo cking when changing pll modes , or if the reference clock is unstable at power - on, power down the pll and then power it back up when the reference clock has stabilized. the internal mclk can be disabled in pll and clock control 0 register to reduce power d issip ation when the ad 1934 is idle. the clock should be stable before it is enabled. unless a stand - alone mode is selected (see the serial control port section ), the clock is disabled by reset and must be enabled b y writing to the spi port for normal operation. to maintain the highest performance possible, it is recommended that the clock jitter of the internal master clock signal be limited to less than 300 ps rms time interval error (tie ). even at these levels, ex tra noise or tones can appear in the dac outputs if the jitter spectrum contains large spectral peaks. if the internal pll is not being used, it is highly recommended that an independent crystal oscillator generate the master clock. in addition, it is espe cially important that the clock signal not be passed through an fpga, cpld, or other large digital chip (such as a dsp) before being applied to the ad 1934 . in most cases, this induce s clock jitter due to the sharing of common power and ground connections w ith other unr elated digital output signals. when the pll is used, jitter in the reference clock is attenuated above a certain frequency depending on the loop filter. reset and power - down reset set s all the control registers to their default settings. to a void pops, reset does not power down the analog outputs. after reset is de asserted, and th e pll acquires lock condition , an initialization routine run s inside the ad 1934 . this initialization lasts for approximately 256 mclks. the power - d o wn bits in the pll and clock control 0 and dac control 1 registers power down the respective sections. all other register settings are retained. to guarantee proper startup, t he reset pin should be pulled low by an external res istor .
data sheet ad1934 rev. d | page 13 of 28 serial control port the ad1934 has an spi control port that permits programming and reading back of the internal control registers for the adcs, dacs, and clock system. a standalone mode is also available for operation without serial control; standalone is configured at reset by connecting cin, cclk, and clatch to ground. in standalone mode, all registers are set to default, except the internal mclk enable, which is set to 1. the adc abclk and alrclk clock ports are set to master/slave by the connecting the cout pin to either dvdd or ground. standalone mode only supports stereo mode with an i 2 s data format and 256 f s mclk rate. refer to table 11 for details. if cin, cclk, and clatch are not grounded, the ad1934 spi port is active. it is recommended to use a weak pull-up resistor on clatch in applications that have a microcontroller. this pull-up resistor ensures that the ad1934 recognizes the presence of a micro- controller. the spi control port of the ad1934 is a 4-wire serial control port. the format is similar to the motorola spi format except the input data-word is 24 bits wide. the serial bit clock and latch can be completely asynchronous to the sample rate of the dacs. figure 9 shows the format of the spi signal. the first byte is a global address with a read/write bit. for the ad1934, the address is 0x04, shifted left 1 bit due to the r/ w bit. the second byte is the ad1934 register address and the third byte is the data. table 11. spi vs. standalone mode configuration dac control cout cin clatch cclk spi out in 1 (pull-up) in standalone 0 0 0 0 d0 d0 d8 d8 d22 d23 d9 d9 c latch cclk cin cout t cch t ccl t cds t cdh t cls t ccp t clh t cots t cod t coe 06106-010 figure 9. format of spi signal
ad1934 data sheet rev. d | page 14 of 28 power supply and voltage reference the ad1934 is designed for 3.3 v supplies. separate power supply pins are provided for the analog and digital sections. these pins should be bypassed with 100 nf ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. a bulk aluminum electrolytic capacitor of at least 22 f should also be provided on the same pc board as the dac. for critical applications, improved performance is obtained with separate supplies for the analog and digital sections. if this is not possible, it is recommended that the analog and digital supplies be isolated by means of a ferrite bead in series with each supply. it is important that the analog supply be as clean as possible. all digital inputs are compatible with ttl and cmos levels. all outputs are driven from the 3.3 v dvdd supply and are compatible with ttl and 3.3 v cmos levels. the dac internal voltage reference (vref) is brought out on filtr and should be bypassed as close as possible to the chip, with a parallel combination of 10 f and 100 nf. any external current drawn should be limited to less than 50 a. the internal reference can be disabled in pll and clock control 1 register and filtr can be driven from an external source. this can be used to scale the dac output to the clipping level of a power amplifier based on its power supply voltage. the cm pin is the internal common-mode reference. it should be bypassed as close as possible to the chip, with a parallel combination of 47 f and 100 nf. this voltage can be used to bias external op amps to the common-mode voltage of the input and output signal pins. the output current should be limited to less than 0.5 ma source and 2 ma sink. serial data portsdata format the eight dac channels use a common serial bit clock (dbclk) and a common left-right framing clock (dlrclk) in the serial data port. the clock signals are all synchronous with the sample rate. the normal stereo serial modes are shown in figure 15. the dac serial data modes default to i 2 s. the ports can also be programmed for left-justified, right-justified, and tdm modes. the word width is 24 bits by default and can be programmed for 16 or 20 bits. the dac serial formats are programmable according to dac control 0 register. the polarity of the dbclk and dlrclk is programmable according to dac control 1 register. the auxiliary tdm port is also provided for applications requiring more than eight dac channels. in this mode, the auxtdmlrclk and auxtdmbclk pins are configured as tdm port clocks. in regular tdm mode, the dlrclk and dbclk pins are used as the tdm port clocks. the auxiliary tdm serial ports format and its serial clock polarity is programmable according to the auxiliary tdm port control 0 register and control 1 register. both dac and auxiliary tdm serial ports are programmable to become the bus masters according to dac control 1 register and auxiliary tdm control 1 register. by default, both auxiliary tdm and dac serial ports are in the slave mode. time-division multiplexed (tdm) modes the ad1934 serial ports also have several different tdm serial data modes. the most commonly used configuration is shown in figure 10. in figure 10, the eight on-chip dac data slots are packed into one tdm stream. in this mode, dbclk is 256 f s . the i/o pins of the serial ports are defined according to the serial mode selected. for a detailed description of the function of each pin in tdm and aux modes, see table 12. the ad1934 allows systems with more than eight dac channels to be easily configured by the use of an auxiliary serial data port. the dac tdm-aux mode is shown in figure 11. in this mode, the aux channels are the last four slots of the 16-channel tdm data stream. these slots are extracted and output to the aux serial port. one major difference between the tdm mode and an auxiliary tdm mode is the assignment of the tdm port pins, as shown in table 12. in auxiliary tdm mode, dbclk and dlrclk are assigned as the auxiliary port clocks, and auxtdmbclk and auxtdmlrclk are assigned as the tdm port clocks. in regular tdm or 16-channel, daisy-chain tdm mode, the dlrclk and dbclk pins are set as the tdm port clocks. it should be noted that due to the high auxtdmbclk frequency, 16-channel auxiliary tdm mode is available only in the 48 khz/44.1 khz/32 khz sample rate. slot 1 left 1 slot 2 right 1 slot 3 left 2 slot 4 right 2 msb msb?1 msb?2 data bclk lrclk slot 5 left 3 slot 6 right 3 slot 7 left 4 slot 8 right 4 lrclk bclk data 256 bclks 32 bclk 06106-017 figure 10. dac tdm (8-channel i 2 s mode)
data sheet ad1934 rev. d | page 15 of 28 table 12. pin function changes in tdm and aux modes pin name stereo modes tdm modes aux modes auxdata1 not used (float) not used (float) aux data out 1 (to external dac 1) dsdata1 dac1 data in dac tdm data in tdm data in dsdata2 dac2 data in dac tdm data out not used (ground) dsdata3 dac3 data in dac tdm data in 2 (dual-line mode) not used (ground) dsdata4 dac4 data in dac tdm data out 2 (dual-line mode) aux data out 2 (to external dac 2) auxtdmlrclk not used (ground) not used (ground) tdm frame sync in/out auxtdmbclk not used (ground) not used (ground) tdm bclk in/out dlrclk dac lrclk in/out dac tdm frame sync in/out aux lrclk in/out dbclk dac bclk in/out dac tdm bclk in/out aux bclk in/out left right msb msb msb msb auxtdmlrclk auxtdmbclk dsdata1 (tdm_in) dlrclk (aux port) dbclk (aux port) auxdata1 (aux1_out) dsdata4 (aux2_out) msb empty empty empty empty dac l1 dac r1 dac l2 dac r2 dac l3 dac r3 dac l4 dac r4 aux l1 aux r1 aux l2 aux r2 8-on-chip dac channels auxiliary dac channels will appear at aux dac ports unused slots 32 bits 0 6106-051 figure 11. 16-channe l dac tdm-aux mode
ad1934 data sheet rev. d | page 16 of 28 daisy-chain mode the ad1934 also allows a daisy-chain configuration to expand the system 16 dacs (see figure 12). in this mode, the dbclk frequency is 512 f s . the first eight slots of the dac tdm data stream belong to the first ad1934 in the chain and the last eight slots belong to the second ad1934. the second ad1934 is the device attached to the dsp tdm port. to accommodate 16 channels at a 96 khz sample rate, the ad1934 can be configured into a dual-line, dac tdm mode, as shown in figure 13. this mode allows a slower dbclk than normally required by the one-line tdm mode. again, the first four channels of each tdm input belong to the first ad1934 in the chain and the last four channels belong to the second ad1934. the dual-line, dac tdm mode can also be used to send data at a 192 khz sample rate into the ad1934, as shown in figure 14. the i/o pins of the serial ports are defined according to the serial mode selected. see table 13 for a detailed description of the function of each pin. see figure 18 for a typical ad1934 configuration with two external stereo dacs. figure 15 and figure 16 show the serial mode formats. for maximum flexibility, the polarity of lrclk and bclk are programmable. in these figures, all of the clocks are shown with their normal polarity. the default mode is i 2 s. dlrclk dbclk 8 dac channels of the first ic in the chain 8 unused slots 8 dac channels of the second ic in the chain msb dsdata1 (tdm_in) of the second ad1934 dsdata2 (tdm_out) of the second ad1934 this is the tdm to the first ad1934 dac l1 dac r1 dac l2 dac r2 dac l3 dac r3 dac l4 dac r4 dac l1 dac r1 dac l2 dac r2 dac l3 dac r3 dac l4 dac r4 dac l1 dac r1 dac l2 dac r2 dac l3 dac r3 dac l4 dac r4 32 bits dsp second ad1934 first ad1934 06106-054 figure 12. single-line dac tdm daisy-chain mode (applicable to 48 khz sample rate, 16-channel, two ad1934 daisy chain) dlrclk dbclk 8 dac channels of the second ic in the chain 8 dac channels of the first ic in the chain dsdata1 (in) dac l1 dac r1 dac l2 dac r2 dac l1 dac r1 dac l2 dac r2 dsdata3 (in) dac l3 dac r3 dac l4 dac r4 dac l3 dac r3 dac l4 dac r4 dsdata2 (out) dac l1 dac r1 dac l2 dac r2 dsdata4 (out) dac l3 dac r3 dac l4 dac r4 32 bits dsp second ad1934 first ad1934 msb 06106-055 figure 13. dual-line, dac tdm mode (applicable to 96 khz sample rate, 16-channel, two ad1934 daisy chain; dsdata3 and dsdata4 a re the daisy chain)
data sheet ad1934 rev. d | page 17 of 28 06106-058 dlrclk dbclk dsdata1 dac l1 dac r1 dac l2 dac r2 dsdata2 dac l3 dac r3 dac l4 dac r4 32 bits msb figure 14. dual-line, dac tdm mode (applicable to 192 khz sample rate, 8-channel mode) lrclk bclk sdat a lrclk bclk sdat a lrclk bclk sdat a lsb lsb lsb lsb lsb lsb left channel right channel right channel left channel left channel right channel msb msb msb msb msb msb right-justified mode?select number of bits per channel dsp mode?16 bits to 24 bits per channel i 2 s mode?16 bits to 24 bits per channel left-justified mode?16 bits to 24 bits per channel lrclk bclk sdat a lsb lsb notes 1. dsp mode does not identify channel. 2. lrclk normally operates at f s except for dsp mode, which is 2 f s . 3. bclk frequency is normally 64 lrclk but may be operated in burst mode. msb msb 1/ f s 06106-013 figure 15. stereo serial modes
ad1934 data sheet rev. d | page 18 of 28 dbclk dlrclk dsdata left-justified mode dsdata right-justified mode dsdata i 2 s-justified mode t dlh t dbh t dbl t dls t dds msb msb msb lsb msb?1 t ddh t dds t ddh t dds t ddh t ddh t dds 06106-014 figure 16. dac serial timing auxtdmbclk auxtdmlrclk dsdata1 left-justified mode dsdata1 right-justified mode dsdata1 i 2 s-justified mode t abh lsb msb msb msb msb?1 t abl t als t alh 06106-015 figure 17. auxtdm serial timing
data sheet ad1934 rev. d | page 19 of 28 table 13. pin function changes in tdm and aux modes (replication of table 12 ) pin name stereo modes tdm modes aux modes auxdata1 not used (flo at) not used (float) aux data out 1 (to external dac 1) dsdata1 dac1 data in dac tdm data in tdm data in dsdata2 dac2 data in dac tdm data out not used (ground) dsdata3 dac3 data in dac tdm data in 2 (dual - line mode) not used (ground) dsdata4 dac4 d ata in dac tdm data out 2 (dual - line mode) aux data out 2 (to external dac 2) auxtdmlrclk not used (ground) not used (ground) tdm frame sync in/out auxtdmbclk not used (ground) not used (ground) tdm bclk in/out dlrclk dac lrclk in/out dac tdm frame syn c in/out aux lrclk in/out dbclk dac bclk in/out dac tdm bclk in/out aux bclk in/out aux dac 1 aux dac 2 lrclk bclk data mclk lrclk bclk data mclk 30mhz 12.288mhz sharc is running in slave mode (interrupt-driven) sharc ad1934 tdm master aux master fsync-tdm (rfs) rxclk txclk txdata tfs (nc) auxdata1 dsdata4 dbclk dlrclk dsdata2 dsdata3 mclk auxtdmlrclk auxtdmbclk dsdata1 06106-019 figure 18 . example of aux mode connection to sharc ? (ad193 4 as tdm master/aux master s hown)
ad1934 data sheet rev. d | page 20 of 28 control registers d efinitions the global address for the ad 1934 is 0x04, shifted left 1 bit due to the r/ w bit. all registers are reset to 0, except for the dac volume registers that are set to full volume. note that t he first setting in each control register p a rameter is the default s etting. table 14. register f ormat global address r/ w register address data bit 23:17 16 15:8 7:0 table 15. register addresses and func tions address function 0 pll and clock control 0 1 pll and clock control 1 2 dac control 0 3 dac control 1 4 dac control 2 5 dac individual channel mutes 6 dac 1l volume control 7 dac 1r volume control 8 dac 2l volume control 9 dac 2r volume control 10 dac 3l volume control 11 dac 3r volume cont rol 12 dac 4l volume control 13 dac 4r volume control 14 reserved 15 auxiliary tdm port control 0 16 auxiliary tdm port control 1 pll and clock contro l registers table 16. pll and clock c ontrol 0 bit value function descripti on 0 0 normal operation pll power - down 1 power - down 2:1 00 input 256 ( 44.1 khz or 48 khz) mclk pin functionality (pll active) 01 input 384 ( 44.1 khz or 48 khz) 10 input 512 ( 44.1 khz or 48 khz) 11 input 768 ( 44.1 khz or 48 khz) 4:3 00 x tal oscillator enabled mclko pin 01 256 f s vco output 10 512 f s vco output 11 off 6:5 00 mclk pll input 01 dlrclk 10 a uxtdm lrclk 11 reserved 7 0 disable: dac idle internal mclk enable 1 enable: dac a ctive
data sheet ad1934 rev. d | page 21 of 28 table 17. pll and clock c ontrol 1 bit value function description 0 0 pll c lock dac clock source select 1 mclk 1 0 pll c lock c lock source s elect 1 mclk 2 0 enabled on - chip voltage refe rence 1 disabled 3 0 not l ocked pll lock indicator (rea d- only) 1 locked 7:4 0000 reserved dac control register s table 18. dac c ontrol 0 bit value function description 0 0 normal power -d own 1 power - down 2:1 00 32 khz /44.1 khz /48 khz sample r ate 01 64 khz /88.2 khz /96 khz 10 128 khz /176.4 khz /192 khz 11 reserved 5:3 000 1 sdata d elay (bclk periods) 001 0 010 8 011 12 100 16 101 reserved 110 reserved 111 reserved 7:6 00 stereo ( n ormal) serial f ormat 01 tdm (daisy chain) 10 dac a ux mode (da c- , tdm - coupled) 11 dual - line tdm table 19. dac c ontrol 1 bit value function description 0 0 latch in mid cycle (normal) bclk active ed ge (tdm i n) 1 latch in at end of cycle (pipeline) 2:1 00 64 (2 channels) bclks per fram e 01 128 (4 channels) 10 256 (8 channels) 11 512 (16 channels) 3 0 left low lrclk p olarity 1 left high 4 0 slave lrclk master/sl ave 1 master 5 0 slave bclk master/s lave 1 master 6 0 dbclk pin bclk s ource 1 internally generated 7 0 normal bclk p olarity 1 inverted
ad1934 data sheet rev. d | page 22 of 28 table 20. dac c ontrol 2 bit value function description 0 0 unmute master m ute 1 mute 2:1 00 flat de - emphasis (32 khz /44.1 khz /48 khz mode only) 01 48 khz c urve 10 44.1 khz cu rve 11 3 2 khz c urve 4:3 00 24 word width 01 20 10 reserved 11 16 5 0 non inverted dac output polarit y 1 inverted 7:6 00 reserved table 21. dac individual channel mutes bit value function description 0 0 unmut e dac 1 left mut e 1 mute 1 0 unmute dac 1 right m ute 1 mute 2 0 unmute dac 2 left mu te 1 mute 3 0 unmute dac 2 right mut e 1 mute 4 0 unmute dac 3 left mu te 1 mute 5 0 unmute dac 3 right mu te 1 mute 6 0 unmute dac 4 left mu te 1 mute 7 0 unmut e dac 4 right m ute 1 mute table 22. dac volume controls bit value function description 7:0 0 no attenuation dac volume co ntrol 1 to 254 ?3/8 db per step 255 full attenuation
data sheet ad1934 rev. d | page 23 of 28 auxiliary tdm port c ontrol registers tabl e 23. auxiliary tdm control 0 bit value function description 1:0 00 24 word width 01 20 10 reserved 11 16 4:2 000 1 sdata delay (bclk periods) 001 0 010 8 011 12 100 16 101 reserved 110 reserved 111 re served 6:5 00 reserved serial format 01 reserved 10 dac a ux mode 11 reserved 7 0 latch in mid cycle (normal) bclk active edge (tdm in) 1 latch in at end of cycle (pipeline) table 24. auxiliary tdm control 1 bit valu e function description 0 0 50/50 (allows 32/24/20/16 bclk/channel) lrclk format 1 pulse (32 bclk/channel) 1 0 drive out on falling edge (def) bclk polarity 1 drive out on rising edge 2 0 left low lrclk polarity 1 left high 3 0 slave lrclk mast er/slave 1 master 5:4 00 64 bclks per frame 01 128 10 256 11 512 6 0 slave bclk master/slave 1 master 7 0 auxtdmbclk pin bclk source 1 internally generated additional modes the ad 1934 offers several additional modes for board level design enhancements . to reduce the emi in board level design, serial data can be transmitted without an explicit bclk. see figure 19 for an example of a dac tdm data transmission mode that does not require high spe ed dbclk . this configuration is applicable when the ad 1934 master clock is generated by the pll with the dlrclk as the pll reference frequency. to relax the requirement for the setup time of the ad 1934 in cases of high speed tdm data transmission, the ad 1934 can latch in the data using the falling edge of dbclk. this effectively dedicate s the entire bclk period to the setup time. this mode is useful in case s where the source has a large delay time in the serial data driver. figure 20 shows this pipeline mode of data transmission. both the blck - less and pipeline mode s are available.
ad1934 data sheet rev. d | page 24 of 28 dlrclk internal dbclk dsdata dlrclk internal dbclk tdm-dsdata 32 bits 06106-059 figure 19. serial dac data transmission in tdm format without dbclk (applicable only if pll locks to dlrclk) dlrclk dbclk dsdata data must be valid at this bclk edge msb 06106-060 figure 20. i 2 s pipeline mode in dac serial data transmission (applicable in stereo and tdm useful for high frequency tdm transmission)
data sheet ad1934 rev. d | page 25 of 28 application circuits typical applications circuits are show n in figure 21, figure 22, and figure 23. recommended loop filters f or lr c lock and m aster c lock as the pll reference are shown in figure 21. output filters for the dac outputs are shown in figure 22 and figure 23 for the non inverting and inverting cases , respectively . 39nf + 2.2nf lf lrclk avdd2 3.32k? 5.6nf 390pf lf mclk avdd2 562? 06106-027 figure 21 . recommended loop filters for lrclk or mclk pll reference 3 1 2 op275 + ? 4.75k? 4.75k? 4.7f + dac out 240pf npo 270pf npo 3.3nf npo audio output 4.99k? 604? 4.99k? 49.9k? 06106-024 figure 22 . typical dac output filter circuit (single - ended, noninverting) 2 1 3 op275 ? + 3.01k? 11k? 4.7f + dac out cm 0.1f 270pf npo 68pf npo 2.2nf npo audio output 604? 49.9k? 11k? 06106-025 figure 23 . typical dac output filter circuit (singl e- ended, inverting)
ad1934 data sheet rev. d | page 26 of 28 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706-a figure 24. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters ordering guide model 1, 2 temperature range package description package option ad1934ystz ?40c to +105c 48-lead lqfp st-48 ad1934ystz-rl ?40c to +105c 48-lead lqfp, 13 tape and reel st-48 AD1934WBSTZ ?40c to +105c 48-lead lqfp st-48 AD1934WBSTZ-rl ?40c to +105c 48-lead lqfp, 13 tape and reel st-48 eval-ad1938az evaluation board 1 z = rohs compliant part. 2 w = qualified for auto motive applications. automotive products the AD1934WBSTZ and AD1934WBSTZ-rl models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commerc ial models; therefore, designers should review the specifications section of this data sheet carefully. only the automotive grade p roducts shown are available for use in automotive applications. contact your local analog devices account representative for specific p roduct ordering information and to obtain the specific automotive reliability reports for these models.
data sheet ad1934 rev. d | page 27 of 28 notes
ad1934 data sheet rev. d | page 28 of 28 notes ? 2007 C 2013 analog devices, inc. all rights reserved. trademark s and registered trademarks are the property of their respective owners. d06106 -0- 2/13(d)

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