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never stop thinking. iec-4-afe-x quad isdn echocancellation circuit analog front end for splitterless adsl over isdn peb 24902, version 3.2 pef 24902, version 3.2 data sheet, rev. 1, may 2004 wireline communications
abm ? , ace ? , aop ? , arcofi ? , asm ? , asp ? , digitape ? , duslic ? , epic ? , elic ? , falc ? , geminax ? , idec ? , inca ? , iom ? , ipat ? -2, isac ? , itac ? , iwe ? , iworx ? , musac ? , muslic ? , octat ? , optiport ? , potswire ? , quat ? , quadfalc ? , scout ? , sicat ? , sicofi ? , sidec ? , slicofi ? , smint ? , socrates ? , vinetic ? , 10basev ? , 10basevx ? are registered trademarks of infineon technologies ag. 10bases?, easyport?, vdslite? are trademarks of infineon technologies ag. microsoft ? is a registered trademark of microsoft corporation, linux ? of linus torvalds, visio ? of visio corporation, and framemaker ? of adobe systems incorporated. the information in this document is subject to change without notice. edition 2004-05-28 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
wg_template_fm5_a5_2003-09-01.fm / ds4 iec-4-afe-x revision history: 2004-05-28 rev. 1 previous version: afe v3.2 preliminary data sheet ds1 page subjects (major changes since last revision) page 9 aplication: added reference to system description geminax max page 10 references: updated page 13 added n.c.: not connected. page 28 removed figure 7 (psd mask for 4b3t adsl-friendly) and figure 8 (psd mask 2b1q adsl-friendly) (described in system description geminax max) page 29 absolute peak voltage: removed values (there is no pulse mask specified) added common dc level page 38 reset & por reset also the digital low pass filter page 40 added power consumption values for 2b1q page 40 initialization and operation: added reference to system description geminax max page 42 starpoint hybrid: added values for main inductance of blocking coils, removed reference to ftz 1 tr 216 page 43 added trafo type page 44 added external circuitry for 2b1q adsl-friendly page 48 removed pull-up specification
peb 24902 pef 24902 table of contents page data sheet rev. 1, 2004-05-28 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 features of the iec-4-afe-x version 3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 infineons ic family for splitterless fdd adsl over isdn . . . . . . . . . . . . . 9 1.4 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 not supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.1 general aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.2 pin description: changes to afe v2.1 . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.3 pin description: complete list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.1 specification of the pll and the 15.36 mhz master clock (pin cl15) . 21 3.2.2 specification of the crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 analog line port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.1 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.2 range function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.3 digital low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.4 digital-to-analog converter and linedriver . . . . . . . . . . . . . . . . . . . . . . 28 3.3.5 analog loop-back function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.6 level detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.1 frame structure on the digital interface in the 2b1q mode . . . . . . . . . 32 3.4.2 frame structure on the digital interface in the 4b3t mode . . . . . . . . . 32 3.4.3 propagation delay in transmit direction . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5 serial control interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5.2 sci system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5.3 sci physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.4 iec-4-afe-x version 3.2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6 boundary scan test controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.2 power-on-reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.4 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5 initialization and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
peb 24902 pef 24902 table of contents page data sheet rev. 1, 2004-05-28 5 external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1 terminating impedance of the line port (informative) . . . . . . . . . . . . . . . 41 5.2 terminating impedance of the adsl port (informative) . . . . . . . . . . . . . . 41 5.3 starpoint hybrid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.4 external circuitry 4b3t adsl-friendly . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.5 external circuitry 2b1q adsl-friendly . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2 operating ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3 supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.5.1 digital interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.5.2 boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
peb 24902 pef 24902 list of figures page data sheet rev. 1, 2004-05-28 figure 1 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2 logic symbol iec-4-afe-x version 3.2 . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3 pin diagram iec-4-afe-x version 3.2 . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 5 jitter transfer gain in db . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 6 maximum phase difference due to sinusoidal input jitter . . . . . . . . . 22 figure 7 block diagram of special functions in the iec-4-afe-x version 3.2 . 30 figure 8 frame structure on sdx and sdr in 2b1q mode . . . . . . . . . . . . . . . 32 figure 9 frame structure on sdx and sdr in 4b3t mode. . . . . . . . . . . . . . . . 33 figure 10 sci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 11 power-on-reset behavior of the iec-4-afe-x after vdd collapse . . 39 figure 12 terminating impedance of the adsl port z_adsl-i . . . . . . . . . . . . . 41 figure 13 starpoint hybrid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 14 external circuitry - 4b3t adsl-friendly. . . . . . . . . . . . . . . . . . . . . . . . 43 figure 15 isdn external circuitry - 2b1q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 16 maximum line input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 17 power supply blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 18 boundary scan timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 19 p-mqfp-64-9 hs (plastic metric quad flat package) . . . . . . . . . . . . 51
peb 24902 pef 24902 list of tables page data sheet rev. 1, 2004-05-28 table 1 serial control interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2 address pins and test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5 pll input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 6 specification of the crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7 specified data of the analog-to-digital converter . . . . . . . . . . . . . . . . 26 table 8 average transmit power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 9 characteristics of the tx-path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 10 specified data of the level detection circuit. . . . . . . . . . . . . . . . . . . . 31 table 11 coding of the 2b1q data pulse (aoutx/boutx) . . . . . . . . . . . . . . . . 32 table 12 coding of the 4b3t data pulse (aoutx/boutx) . . . . . . . . . . . . . . . . 33 table 13 pin types and boundary scan cells . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 14 sequence of pins in the boundary scan . . . . . . . . . . . . . . . . . . . . . . . 35 table 15 tap controller instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 16 parameters for por activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 17 power consumption (4b3t adsl-friendly) . . . . . . . . . . . . . . . . . . . . . 40 table 18 power consumption (2b1q adsl-friendly) . . . . . . . . . . . . . . . . . . . . . 40 table 19 terminating impedance of the isdn port z_isdn . . . . . . . . . . . . . . . 41 table 20 parameters of the starpoint hybrid . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 21 external circuitry parameters - 4b3t adsl-friendly . . . . . . . . . . . . . . 43 table 22 external circuitry parameters -2b1q adsl-friendly . . . . . . . . . . . . . . 45 table 23 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 24 operating ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 25 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 26 interface signals of iec-4-afe-x and dfe-q/dfe-t . . . . . . . . . . . . . 49 table 27 boundary scan timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
data sheet 8 2004-05-28 type package peb 24902 p-mqfp-64-9 hs pef 24902 p-mqfp-64-9 hs iec-4-afe-x quad isdn echocancellation circuit analog front end for splitterless adsl over isdn iec-4-afe-x peb 24902 pef 24902 version 3.2 features p-mqfp-64-1, -2, -3, -8 1overview the iec-4-afe-x version 3.2 is part of infineons chip set for a splitterless, fdd (non-overlapped) adsl over isdn linecard based on geminax max according to ref [3.] , chapter 4.2.2 of ref [5.] , annex b of ref [6.] / ref [7.] , and ref [8.] . figure 1 shows the basic architecture of an integrated isdn and adsl linecard based on geminax max chip set. the iec-4-afe-x version 3.2 is designed for use in central office, dlcs and dslams. 1.1 features of the iec-4-afe-x version 3.2 four port isdn echo cancellation circuit analog frontend offers all features of afe v2.1 ( ref [1.] ) 1) integrated digital transmit low-pass filter, which obsoletes the need for an discrete, passive splitter device conforms in connection with geminax max chip set to ref [3.] , especially to the following isdn psd masks: - ?psd mask for a 4b3t isdn system with integrated splitter? acc. to ref [3.] (4b3t adsl friendly, compatible to adsl us spectrum down to 138 khz) - ?psd mask for a 2b1q isdn system with integrated splitter? acc. to ref [3.] (2b1q adsl friendly, compatible to adsl us spectrum down to 120 khz) footprint compatible to afe v2.1 ( ref [1.] ) serial control interface for communication with geminax max chip set 1) with the exception of features for isdn only, which are overruled by ref [3.] p-mqfp-64-9 hs
peb 24902 pef 24902 overview data sheet 9 rev. 1, 2004-05-28 1.2 application diagram figure 1 shows a typical application of iec-4-afe-x version 3.2 together with infineons ic family for splitterless fdd adsl over isdn and dfe-t/q version v2.2 ( chapter 1.3 ) for an integrated voice and data solution (ivd). figure 1 application diagram note: iec-4-afe-x version 3.2 is designed for operation with geminax max chip set. the system properties of an ivd isdn consisting of geminax max chipset, iec- 4-afe-x version 3.2 and dfe-q/t v2.2 are described in ref [9.] . attention: any warranty, whether express or implied shall be subject to the use of the chips within the procedure as outlined in the respective data sheet. in case the chips are used incorrectly or not used within the logic or electrical specifications, any and all warranty or other claim based on any defect or malfunction whatsoever shall be excluded. 1.3 infineons ic family for splitterless fdd adsl over isdn isdn peb 24902 / pef 24902 iec-4-afe-x version 3.2 pef 24911 dfe-q version 2.2 pef 24901 dfe-t version 2.2 applicat ion_v1 ge mi na x -l2 max geminax-d max utopia l2 afe-x iom-2 geminax-a0 max external adsl ci rcui try external isdn ci rcui try line starpoint hybri d uplink dfe-t/q sci
peb 24902 pef 24902 overview data sheet 10 rev. 1, 2004-05-28 adsl pef 55008 geminax-d max pef 55204 geminax-a0 max pef 55208 geminax-a8 max peb 22716 geminax-l2 max 1.4 related documentation 1. afe v2.1, quad isdn echocancellation circuit analog front end, pef / peb 24902 version 2.1, data sheet ds2, infineon technologies ag, january 2001 2. ts 102080 v1.3.2, transmission and multiplexing; isdn basic rate access, digital transmission system on metallic local lines, etsi, may 2000 3. ts 102080 v1.4.1, transmission and multiplexing; isdn basic rate access, digital transmission system on metallic local lines, annex-d: isdn systems requirements when coexisting with adsl or vdsl, etsi, july 2003 4. ts 101952-1-3 v1.1.1, access network xdsl transmission filters; part 1: adsl splitters for european deployment; sub-part 3: specification of adsl/isdn splitters, etsi, may 2002 5. ts 101388 v1.3.1, transmission and multiplexing (tm); access transmission systems on metallic access cables; asymmetric digital subscriber line (adsl)- european specific requirements, etsi, may 2002 6. g.992.1, asymmetrical digital subscriber line (adsl) transceivers, itu-t, june 1999 7. g.992.3, asymmetrical digital subscrib er line transceivers 2 (adsl2), itu-t, july 2002 8. 1 tr 112, description of the u-r2 interface of adsl systems, u-r2 interface, v5.1, dtag, dezember 2003 9. geminax max, preliminary users manual, rev. 1.0, adsl2+ data only and integrated voice and data linecard, system description, infineon, apr. 2004 1.5 not supported iec-4-afe-x version 3.2 does not support isdn-only operation according to ref [2.] . iec-4-afe-x version 3.2 in connection with geminax max chip set supports adsl- friendly operation according to ref [3.] , which overrules several requirements of ref [2.] .
peb 24902 pef 24902 external signals data sheet 11 rev. 1, 2004-05-28 2 external signals attention: any warranty, whether express or implied shall be subject to the use of the chips within the procedure as outlined in the respective data sheet. in case the chips are used incorrectly or not used within the logic or electrical specifications, any and all warranty or other claim based on any defect or malfunction whatsoever shall be excluded. 2.1 logic symbol figure 2 logic symbol iec-4-afe-x version 3.2 aout 0 bout 0 ain 0 bin 0 aout 1 bout 1 ain 1 bin 1 aout 2 bout 2 ain 2 bin 2 aout 3 bout 3 ain 3 bin 3 sdx sdr pdm 0 pdm 1 pdm 2 pdm 3 tdiss tdo tdi tck tms clock cl 15 xin xout v ref3 v ref2 v ref1 v ref0 res pllf code gnd d1...2, a0...3 vdd d1...2, a0...3 +5v 0v mode s ettings boundary scan pins adc outputs serial interfac e to dfe analog line ports iec-4-afe-x afe-x_logic_symbol.vsd serial control interface di n dout sclk scs address addr0 addr1 addr2 test
peb 24902 pef 24902 external signals data sheet 12 rev. 1, 2004-05-28 2.2 pin diagram figure 3 pin diagram iec-4-afe-x version 3.2 2.3 pin description gnd a2 xdn2 v ref2 ain2 bin2 dout tdi tdo tck tms tdiss bin3 v ref3 xdn3 gnd a3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 ain3 49 48 res. 47 aout2 46 vdd a2 45 addr2 44 bout2 43 gnd d0 sdr sclk 42 41 pdm2 40 pdm1 39 pdm0 38 vdd d0 37 bout0 36 addr0 35 vdd a0 34 aout0 33 gnd a0 32 xdn0 31 v ref0 30 ain0 29 bin0 28 din 27 clock 26 res 25 sdx 24 code 23 pllf 22 bin1 21 ain1 20 v ref1 19 xdn1 18 gnd a1 17 1 res. 2 aout3 3 vdd a3 4 test 5 bout3 6 cl15 pdm3 gnd d1 78 xout 9 xin 10 vdd d1 11 scs 12 bout1 13 addr1 14 vdd a1 15 aout1 16 iec-4- afe-x afe-x_pinning
peb 24902 pef 24902 external signals data sheet 13 rev. 1, 2004-05-28 2.3.1 general aspects the following abbreviations are used: 2.3.2 pin description: changes to afe v2.1 some unused pins of afe v2.1 are used for afe-x for additional functionality. table 1 to table 2 list all pins with changed functionality as compared to afe v2.1. i input. digital lvttl levels o output. digital lvttl levels od open drain pu pull up pd pull down n.c. not connected table 1 serial control interface (sci) pin no. old new i/o function 12 n.c. scs i (pd) tie to ?1? 43 n.c. sclk i (pd) serial clock clock signal of the sci 27 addr din i (pd) serial data receive receive data line of the sci 54 n.c. dout od serial data transmit transmit data line of the sci table 2 address pins and test mode pin no. old new i/o function 35 n.c. addr0 i (pd) address 0 pinstrapping of afe-x address for sci access 14 n.c. addr1 i (pd) address 1 pinstrapping of afe-x address for sci access 45 n.c. addr2 i (pd) address 2 pinstrapping of afe-x address for sci access
peb 24902 pef 24902 external signals data sheet 14 rev. 1, 2004-05-28 2.3.3 pin description: complete list 4 n.c. test i (pd) test 0: inactive 1: iec-4-afe-x version 3.2 test mode note: pin test must be kept low. 1n.c.res. i (pd) reserved reserved for future use. leave open. 48 n.c. res. i (pd) reserved reserved for future use. leave open. table 3 pin definitions and functions pin no. symbol input (i) output (o) description power supply pins 37 vdd d1 5 v 5% digital supply voltage 11 vdd d2 34 vdd a0 5 v 5% analog supply voltage 15 vdd a1 46 vdd a2 3vdd a3 42 gnd d1 0 v digital 6gnd d2 32 gnd a0 0 v analog 17 gnd a1 49 gnd a2 64 gnd a3 30 v ref0 n.c. reference voltage no function, a capacitor, 100 nf, may be connected to gnd to maintain compatibility with previous versions table 2 address pins and test mode (cont?d) pin no. old new i/o function
peb 24902 pef 24902 external signals data sheet 15 rev. 1, 2004-05-28 19 v ref1 n.c. reference voltage no function, a capacitor, 100 nf, may be connected to gnd to maintain compatibility with previous versions 51 v ref2 n.c. reference voltage no function, a capacitor, 100 nf, may be connected to gnd to maintain compatibility with previous versions 62 v ref3 n.c. reference voltage no function, a capacitor, 100 nf, may be connected to gnd to maintain compatibility with previous versions jtag boundary scan 57 tck i test clock 58 tms i (pu) test mode select 55 tdi i (pu) test data input 56 tdo o test data output 59 tdiss i (pu) jtag boundary scan disable active low, internal pullup (i tdiss = -100 a (typ.)) note: case of jtag interface disabled (tdiss = 0), pin tck should be pulled down on board (e.g. pull-down of 47 k ? ). line port pins 29 ain0 i differential u interface input line port 0 28 bin0 i differential u interface input line port 0 33 aout0 o differential u interface output line port 0 36 bout0 o differential u interface output line port 0 20 ain1 i differential u interface input line port 1 21 bin1 i differential u interface input line port 1 table 3 pin definitions and functions (cont?d) pin no. symbol input (i) output (o) description
peb 24902 pef 24902 external signals data sheet 16 rev. 1, 2004-05-28 16 aout1 o differential u interface output line port 1 13 bout1 o differential u interface output line port 1 52 ain2 i differential u interface input line port 2 53 bin2 i differential u interface input line port 2 47 aout2 o differential u interface output line port 2 44 bout2 o differential u interface output line port 2 61 ain3 i differential u interface input line port 3 60 bin3 i differential u interface input line port 3 2aout3o differential u interface output line port 3 5bout3o differential u interface output line port 3 digital interface 7 cl15 i/o master clock 15.36 mhz all operations and the data exchange on the digital interface are based on this clock. cl 15 is set to an input at power-on. if a 15.36 mhz clock is generated by the internal pll/oscillator or if an external clock is provided at xin then cl15 becomes an output and issues this clock. if the pin xin is clamped to low or high then cl15 remains an input and an other device has to provide the 15.36 mhz clock. 38 pdm0 o pulse density modulated output of the second-order sigma-delta adc of line port 0 39 pdm1 o pulse density modulated output of the second-order sigma-delta adc of line port 1 table 3 pin definitions and functions (cont?d) pin no. symbol input (i) output (o) description
peb 24902 pef 24902 external signals data sheet 17 rev. 1, 2004-05-28 40 pdm2 o pulse density modulated output of the second-order sigma-delta adc of line port 2 8pdm3o pulse density modulated output of the second-order sigma-delta adc of line port 3 31 xdn0 n.c. for future use, leave pin open 18 xdn1 n.c. for future use, leave pin open 50 xdn2 n.c. for future use, leave pin open 63 xdn3 n.c. for future use, leave pin open 24 sdx i serial data transmit interface for the transmit and control data. up to eight 1) lines can be multiplexed on sdx. transmission and sampling is based on clock cl15 (15.36 mbit/s). 41 sdr o serial data receive level information for the detection of the awake tone. the four lines are multiplexed on sdr. 23 code i select 2b1q or 4b3t code code = low sets 2b1q code. 25 res i reset reset and power down of the entire afe-x including pll and all four line ports. asynchronous signal, active low. note: while res =low, the pll is not reset statically, but only during the fallig edge at pin res . pll 9xouto crystal out 15.36 mhz crystal is connected. leave open if not used. 10 xin i crystal in a synchronous 15.36 mhz clock signal or 15.36 mhz crystal is connected. clamping xin to either low or high sets cl15 to input. table 3 pin definitions and functions (cont?d) pin no. symbol input (i) output (o) description
peb 24902 pef 24902 external signals data sheet 18 rev. 1, 2004-05-28 26 clock i clock 8 khz or 2048 khz clock as a time base of the 15.36 mhz clock. connect to gnd if not used. 22 pllf i (pu) pll frequency select corner frequency of pll jitter transfer function. internal pullup resistor (i pllf = -100 a (typ.)). serial control interface 12 scs i (pd) tie to ?1? 43 sclk i (pd) serial clock clock signal of the sci 27 din i (pd) serial data receive receive data line of the sci 54 dout od serial data transmit transmit data line of the sci address pins and test mode 35 addr0 i (pd) address 0 pinstrapping of afe-x address for sci access 14 addr1 i (pd) address 1 pinstrapping of afe-x address for sci access 45 addr2 i (pd) address 2 pinstrapping of afe-x address for sci access 4 test i (pd) test 0: inactive 1: iec-4-afe-x version 3.2 test mode note: pin test must be kept low. 1res.i (pd) reserved reserved for future use. leave open. 48 res. i (pd) reserved reserved for future use. leave open. 1) only four lines are supported table 3 pin definitions and functions (cont?d) pin no. symbol input (i) output (o) description
peb 24902 pef 24902 functional description data sheet 19 rev. 1, 2004-05-28 3 functional description attention: any warranty, whether express or implied shall be subject to the use of the chips within the procedure as outlined in the respective data sheet. in case the chips are used incorrectly or not used within the logic or electrical specifications, any and all warranty or other claim based on any defect or malfunction whatsoever shall be excluded.
peb 24902 pef 24902 functional description data sheet 20 rev. 1, 2004-05-28 3.1 block diagram figure 4 block diagram afe-x afe-x_block_diagram common pll digital interface dfe interface boundary scan, tap control jtag interface tx - path fuse digital filter noise shaper ld / pofi dac serial control interface sci bus addr2-0 rx - path level detect prefi agc adc aout/bout ain/bin
peb 24902 pef 24902 functional description data sheet 21 rev. 1, 2004-05-28 3.2 clock generation all timing signals are derived from a 15.36 mhz system clock. the 15.36 mhz clock can be provided by the iec-4-afe-x version 3.2 by a crystal based pll, which is synchronized to either an 8 khz or a 2048 khz clock at pin clock. the frequency at pin clock is detected automatically. the pll is set to the nominal frequency either by a por or by a falling edge at the res pin. when the reference clock (clock) is applied, the pll starts to synchronize. the 15.36 mhz clock can also be provided externally at pin cl15 without making use of the internal pll. in this mode the pin xin must be tied to either vdd or gnd. an internal power-on-reset circuitry assures that the pin cl15 is an input until a 15.36 mhz clock is detected at the output of the pll/oscillator. to enable error-free data transport to/from the quad iec dfe-t/q, the clocks dcl and fsc from the iom ? -2-interface must be synchronous to the 15.36 mhz signal. therefore it is recommended to use the same signal for fsc and as input to clock pin at the iec- 4-afe-x version 3.2 when the internal pll is used to generate the 15.36 mhz clock. if another clock source is used for clock, e.g. the 2048 khz dcl, a common time base must be guaranteed. this is usually achieved if fsc is derived from dcl by dividing it directly by 256. any constant phase difference between the time bases of both clocks is possible, but the devices have currently been qualified and released only for using the same fsc signal for the quad iec dfe-t/q and for iec-4-afe-x version 3.2. 3.2.1 specification of the pll and the 15.36 mhz master clock (pin cl15) the pll is based on a crystal connected to the pins xin and xout. for synchronization of the 15.36 mhz clock up to 16 internal capacitances are connected to xin and xout. the loop filter of the pll is of second order, therefore a sinusoidal input jitter with the angular frequency = 2 f at clock is attenuated by the pll according to the following formula: h(j ) = [(2 / r )j + 1] / [(j / r ) 2 + ( 2 / r )j + 1] h(j ) is the complex jitter transfer factor r = 2 f r is the angular resonance frequency of the pll is the damping factor of the pll the maximum phase difference between the external clock and the internal reference, derived from the master clock, due to a sinusoidal input jitter with the angular frequency is given as 1 - h(j ). the magnitude of the jitter transfer function and of the phase difference are illustrated below:
peb 24902 pef 24902 functional description data sheet 22 rev. 1, 2004-05-28 figure 5 jitter transfer gain in db figure 6 maximum phase difference due to sinusoidal input jitter if the input signal at pin clock disappears being stuck to high or low, the pll continues to generate the cl15 clock. in this case the pll keeps the last setting. the accuracy of the frequency of cl15 degenerates in the long term only due to changes in temperature and ageing. the resonance frequency can be set to two different values using the pin pllf. pllf tied to low sets the pll to a low resonance frequency suited for applications in the 40 30 20 10 0 10 0.01 0.1 1 10 100 1000 10 40 h1 j h1max 1000 0.01 f j fn 80 60 40 20 0 20 0.01 0.1 1 10 100 1000 20 80 h1e j 1000 0.01 f j fn
peb 24902 pef 24902 functional description data sheet 23 rev. 1, 2004-05-28 access network. pllf tied to high or left open results in a higher resonance frequency for accelerated synchronization. the pllf pin has an internal pull-up resistor. the pll automatically determines whether the frequency at pin clock is 8 khz or 2048 khz. . table 4 pll characteristics parameter limit values unit min. typ. max. f r resonance frequency, pllf = low 1.7 2.0 2.3 hz f r resonance frequency, pllf = high 789hz damping factor 0.7 0.9 1.2 h max maximum jitter amplification 0.9 1.45 2.2 db synchronization time of the pll after power on and applying the reference at pin clock, pllf = low 8sec synchronization time of the pll after power on and applying the reference at pin clock, pllf = high 1sec output jitter at cl15 without any jitter in the clock signal (peak- to-peak); jitter frequency > 800 hz 2ns output jitter at cl15 without any jitter in the clock signal (peak- to-peak) jitter frequency < 20 hz 80 ns initial accuracy after the loss of the reference clock at clock 0.5 ppm initial accuracy after power on -50 50 ppm start-up time of the oscillator with the crystal suggested below. 0.5 1 ms
peb 24902 pef 24902 functional description data sheet 24 rev. 1, 2004-05-28 3.2.2 specification of the crystal a crystal (serial resonance) has to be connected to xin and xout which shall meet the following specification: output current at xout during start-up 0.5 1 ma output current at xout after synchronization 0.5 1 ma table 5 pll input requirements parameter limit values unit min. typ. max. accuracy of the reference at clock to enable synchronization -150 0 +150 ppm peak-to peak jitter of the clock signal during any 125 s period 70 ns peak-to-peak voltage of a sinusoidal external master clock provided at xin 3.3 v pp low time of the reference at clock 130 ns high time of the reference at clock 130 ns pulse width of the 15 mhz clock 26 39 ns table 6 specification of the crystal parameter limit values unit min. typ. max. nominal frequency 15.360000 mhz total frequency range -150 +150 ppm table 4 pll characteristics (cont?d) parameter limit values unit min. typ. max.
peb 24902 pef 24902 functional description data sheet 25 rev. 1, 2004-05-28 note that the load capacitors are integr ated in the iec-4-afe-x version 3.2. no additional capacitance has to be connected neither to xin nor to xout. the crystal specifications shall meet the requirements given in table 6 . a suitable type of crystal would be: vibrator: mode of vibration ds fundamental crystal cut ati application hint: parasitic capacitances at xin and xout pin, e.g. due to board capacitances should be below 3 pf. 3.3 analog line port the iec-4-afe-x version 3.2 chip gives access to four line ports. the signal to be transmitted is issued differentially at pins aout0..3 and bout0..3. the input is differentially sampled at ain0..3 and bin0..3. each line port consists of three main function blocks (see figure 4 ): the analog-to-digital converter in the receive path the digital-to-analog converter in the transmit path the output filter in the transmit path furthermore a line port contains some special functions. these are: analog test loop-back level detect function operating frequency c load = 15 pf c load = 7 pf 15.35770 15.36230 mhz mhz current 1 2 ma load capacitance 9.8 10.2 pf overall tolerance ? f/f 60 ppm resonance resistance r r 30 ? shunt capacitance c 0 7pf motional capacitance c 1 25 ff overall pullability 210 ppm table 6 specification of the crystal (cont?d) parameter limit values unit min. typ. max.
peb 24902 pef 24902 functional description data sheet 26 rev. 1, 2004-05-28 3.3.1 analog-to-digital converter a first order low-pass anti alias filter is provided at the input of the adc. the adc is a sigma-delta modulator of second order using a clock rate of 15.36 mhz. during normal operation the adc evaluates the signal at ainx and binx. the adc evaluates the signal at aoutx and boutx while the analog loop-back is activated. the maximum peak input voltage between ainx and binx is defined as the minimum input voltage that results in a continuous series of high or low at the pdmx pin. a larger input signal will be clipped. an increasing positive voltage at ainx - binx will result in an increasing number of high states at the pdmx pin. hence, the maximum positive voltage at ainx - binx results in a series of high whereas the maximum negative voltage results in a series of low. the average percentage of high states obtained with a given input voltage is referred to as gain of the adc. it is expressed in %/volt. the adc offset is the difference in % from the ideal 50 % high states with no input signal, transferred back to the input voltage using the adc gain. . table 7 specified data of the analog-to-digital converter parameter limit values unit test condition min. typ. max. signal/noise (sine wave 1.5 vpp between ainx/binx) 70 72 db range function deacti- vated, all line ports sending random 2b1q pattern into 98 ? load signal/(noise+ distortion) (sine wave 0.4 vpp between ainx/binx) 59.5 61.5 db range function deacti- vated, all line ports sending random 2b1q pattern into 98 ? load signal/(noise + distortion) (sine wave 1.5 vpp between ainx/binx) 65 68 db range function deactivated signal/(noise + distortion) (sine wave 2.0 vpp between ainx/binx) 60 db range function deactivated signal/(noise + distortion) (sine wave 3 vpp between ainx/ binx) 60 db range function activated signal/noise (sine wave 3 vpp between ainx/ binx) 65 68 db range function activated, all line ports sending random 2b1q pattern into 98 ? load
peb 24902 pef 24902 functional description data sheet 27 rev. 1, 2004-05-28 3.3.2 range function in case the signal input is too high (low attenuation on short loops), the range function can be activated. the range function attenuates the received signal internally by 6 db. the range function is activated by setting the range bit on sdx to one. signal/(noise + distortion) (sine wave 4 vpp between ainx/ binx) 50 db range function activated signal/(noise + distortion) (sine wave 4.6 vpp between ainx/binx) 35 db range function activated dc offset voltage 35 mv range function deactivated dc offset voltage 70 mv range function activated adc gain 28 33 38 %/v range function deactivated adc gain 14 16.5 19 %/v range function activated attenuation of the range function 5.45 6 6.25 db impedance between ainx and binx 100 k ? input capacitance at ainx and binx 3pf input voltage range at ainx and binx gnd vdd common mode rejection ratio 40 db f < 80 khz power supply rejection ratio 40 db f < 80 khz power supply rejection ratio 55 db 80 khz < f < 20 mhz anti alias filter corner frequency 1.1 1.6 2.3 mhz table 7 specified data of the analog-to-digital converter (cont?d) parameter limit values unit test condition min. typ. max.
peb 24902 pef 24902 functional description data sheet 28 rev. 1, 2004-05-28 3.3.3 digital low-pass filter the iec-4-afe-x version 3.2 implements a digital low-pass filter. the filter characteristic is optimized for high stop-band attenuation with a very steep transition from pass-band to stop-band. due to this filter characteristic and in connection with external circuitry as specified in chapter 5 as well as geminax max chip set, iec-4- afe-x version 3.2 psd at the lineport of the starpoint hybrid meets the adsl-friendly isdn-psd-mask requirements according to ref [3.] (see ref [9.] , chapter 5.2). therefore, adsl service based on geminax max chip set may be operated on the same pair as isdn service based on iec-4-afe-x version 3.2 / dfe-t v2.2 / dfe-q v2.2 without a discrete, passive splitter device. 3.3.4 digital-to-analog c onverter and linedriver the output pulse is transmitted by a special dac and a linedriver with high linearity. pulse mask no pulse mask is specified by ref [3.] ) 1) average transmit power 1) the pulse mask of afe-v2.1 may be not met by iec-4-afe-x version 3.2. table 8 average transmit power parameter limit values unit min. typ. max. average transmit power of a 4b3t signal derived from random data when measured at resistance 150 ? (connected to the starpoint) over the frequency band from 100 hz to 120 khz. 11 14 dbm average transmit power of a 2b1q signal derived from random data when measured at resistance 135 ? (connected to the starpoint) over the frequency band from 100 hz to 80 khz. 13 14 dbm
peb 24902 pef 24902 functional description data sheet 29 rev. 1, 2004-05-28 table 9 characteristics of the tx-path parameter symbol limit values unit test condition min. typ. max. signal / noise s/n 72.5 db driving sinusoidal signal at 20 khz/ 40 khz/60 khz/ 80 khz and full scale (8 vpp) into 98 ? (2b1q) / 172 ? (4b3t) signal / (noise and distortion) s/d 70.5 db common mode dc level 2.05 2.375 2.6 v offset between aoutx and boutx - 35.5 35.5 mv ratio between 1 and 3 symbols 0.3283 0.3333 0.3383 variation of the signal amplitude measured over a period of 1 min. 1% peak-to-peak output jitter measured with a high-pass filter of 30 hz cut-off frequency 1.3 nsec jitter free 15.36 mhz clock peak-to-peak output jitter measured without the high-pass filter 6.5 nsec corner frequency of the dac rc low- pass filter 350 khz output impedance aoutx/boutx 1 2 6 4 12 ? ? power up power down
peb 24902 pef 24902 functional description data sheet 30 rev. 1, 2004-05-28 3.3.5 analog loop-back function the loop-back bit (loop) set to one on sdx activates an internal analog loop-back. this loop-back is closed near the u interface. signals received on ainx / binx will neither be evaluated nor recognized by the adc. the output signal is attenuated by 17 db and fed to the inputs of the adc and level detect circuit instead. it is still available at aoutx / boutx. figure 7 shows a schematic of the loop-back function. figure 7 block diagram of special functions in the iec-4-afe-x version 3.2 3.3.6 level detect the level detect circuit evaluates the differential signal between ainx and binx. level detect is not affected by the range setting nor by the analog loop-back. it is also active during power down. the level detection is preceded by a first order low-pass filter. the detected level is communicated to the quad iec dfe-t/q on sdr. the detected level is updated every 12.5 s (2b1q) or every 8.33 s (4b3t). if the input signal exceeds the threshold once during this time, the level bit is set to one, otherwise it is set to zero. the level bit is repeated on sdr during the whole time slot associated with the corresponding line port. buffer - 17 db - 6db loop d d a a aoutx/boutx loop range range ainx/binx lowpass level detection itb07141.vsd
peb 24902 pef 24902 functional description data sheet 31 rev. 1, 2004-05-28 3.4 digital interface on the digital interface transmit and receive data is exchanged as well as control information for the start-up procedure. t he adc output is transferred to the quad iec dfe-t version 2.2 or quad iec dfe-q version 2.2 on the signals pdm0..pdm3. the timing of all signals in 2b1q mode as well as 4b3t mode is based on the 15.36 mhz clock which is provided by the iec-4-afe-x version 3.2. the transmit data, power up/down, range function and loopback are transferred on sdx, and the level status on sdr for all line ports. eight time slots contain the data for up to eight line ports. the iec-4-afe-x version 3.2 operates in slots 1, 3, 5, 7. the remaining slots are reserved for future use. the allocation of these time slots is done by the ninth time slot, a 24-bit synchronization word on sdx, that consists of all zeros. the other time slots with transmission data start with a one. therefore the first one after at least 24 subsequent zeros must be the first bit of time slot number 0. this information is also used to determine the status of synchronization of the digital interface after reset. the line code independent data on sdx: table 10 specified data of the level detection circuit parameter limit values unit min. typ. max. cut-off frequency of the input filter 90 160 230 khz threshold of level detect (2b1q) 4 20 mv threshold of level detect (4b3t) 10 30 mv dc level of level detect (common mode level) 0 3 v nop: the no-operation-bit is set to zero if none of the control bits (pdow, range and loop) shall be changed. the values of the control bits of the assigned line port is latched. the states of the control bits on sdx are ignored, they should be set to zero to reduce any digital cross-talk to the analog signals. the nop bit is set to one if at least one of the control bits shall be changed. in this case all control bits are transmitted with their current values. pdow: if the pdow bit is set to one, the assigned line port is switched to power down. otherwise it is switched to power up. range: range = one activates the range function, otherwise the range function is deactivated. "range function activated" refers to high input levels. loop: loop = one activates the loop function, i.e. the loop is closed. otherwise the line port is in normal operation.
peb 24902 pef 24902 functional description data sheet 32 rev. 1, 2004-05-28 3.4.1 frame structure on the digital interface in the 2b1q mode the 192 available bits during a 80 khz period (related to the 15.36 mhz clock) are divided into the 9 slots of which 8 slots are 21 bits long used for data transmission. the status on sdr is synchronized to sdx. each time slot on sdr carries the corresponding ld bit during the last 20 bits of the slot. figure 8 frame structure on sd x and sdr in 2b1q mode the 2b1q data is coded with the bits td2, td1, td0: 3.4.2 frame structure on the digital interface in the 4b3t mode the 128 available bits during a 120 khz period (related to the 15.36 mhz clock) are divided into 9 slots of which 8 slots are 13 bits long used for data transmission. the status on sdr is synchronized to sdx. each time slot on sdr carries the corresponding ld bit during the last 12 bits of the slot. sy: first bit of the time slots with transmission data. for synchronization and bit allocation on sdx and sdr, sy is set to one. "0": reserved bit. reserved bits are currently not defined and shall be set to zero. some of these bits may be used for test purposes or can be assigned a function in later versions. table 11 coding of the 2b1q data pulse (aoutx/boutx) 2b1q data td2 td1 td0 0 ?1? ?dont care? ?dont care? ? 3000 ? 1001 + 3010 + 1011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 sdx sdr sy=1 td 2 td 1 td 0 pdow loop range nt "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" 0ld nopq 0 21 42 63 84 105 126 147 168 191 slot 0 slot 1 slot 2 slot 3 slot 4 slot 5 slot 6 slot 7 synch. word 21 bit 21 bit 21 bit 21 bit 21 bit 21 bit 21 bit 21 bit 24 bit itd07142.vsd
peb 24902 pef 24902 functional description data sheet 33 rev. 1, 2004-05-28 figure 9 frame structure on sdx and sdr in 4b3t mode the 4b3t data is coded with the bits td1, td0: 3.4.3 propagation delay in transmit direction the delay in transmit direction depends on the slot x on sdx. the pulses on the four lines are equally spaced in time while the transmit bits on sdx are not. the delay is defined as the time from the end of last bit of the slot x on sdx until the start of the pulse at aoutx/boutx. the delay of iec-4-afe-x version 3.2 is slightly larger as compared to afe-v2.1 ((3x + 27) * 65 ns + approximately 4 s). 3.5 serial control interface (sci) 3.5.1 general sci is an interchip communication channel, which allows flexible exchange of information between chips of infineons chip family for linecard solutions. it is mandatory to connect iec-4-afe-x version 3.2 to the sci bus. 3.5.2 sci system configuration figure 10 shows the typical sci system configuration. table 12 coding of the 4b3t data pulse (aoutx/boutx) 4b3t data pulse td1 td0 000 + 1 1 0 ? 1 1 1
peb 24902 pef 24902 functional description data sheet 34 rev. 1, 2004-05-28 figure 10 sci bus the sci bus connects all those iec-4-afe-x version 3.2 and geminax max devices, whose lineports are connected to common twisted pairs. 3.5.3 sci physical interface note: it has to be guaranteed externally, that din and dout are high when inactive (for instance r pull-up = 3 k ? ). sclk: serial control clock (max. frequency < 2 mhz) din: serial control data in dout: serial control data out 3.5.4 iec-4-afe-x version 3.2 address each iec-4-afe-x version 3.2 connected to the same geminax-d max via sci shall be discriminated by an unique address by pinstrapping of addr2, addr1 and addr0. dfe-q/t (4-ch.) geminax-a0 max syst em_conf ig_sci gemi nax -d max ge mi na x -a 0 max afe-x v3.2 (4-ch.) afe-x v3.2 (4-ch.) dfe-q/t v2.2 (4-ch.) addr2 addr1 addr0 addr2 addr1 addr0 sci sci sci
peb 24902 pef 24902 functional description data sheet 35 rev. 1, 2004-05-28 3.6 boundary scan test controller the iec-4-afe-x version 3.2 provides a b oundary scan support for a cost effective board testing. it consists of: complete boundary scan for 11 signals (pins) according to ieee std. 1149.1 specification. test access port controller (tap) four dedicated pins (tck, tms, tdi, tdo) one 32-bit idcode register pin tdiss tied to low disables the complete boundary scan test controller boundary scan the following pins are included in the boundary scan: #27 din, #7 cl15, #26 clock, #23 code, #38 pdm0, #39 pdm1, #40 pdm2, #8 pdm3, # 25 res , #41 sdr, #24 sdx former n.c. pins: #12 scs, #43 sclk, #54 dout, #35 addr0, #14 addr1, and #45 addr2 are not included into boundary scan. depending on the pin functionality one, two or three boundary scan cells are provided. when the tap controller is in the appropriate mode data is shifted into or out of the boundary scan via the pins tdi/tdo using the 6.25 mhz clock on pin tck. table 13 pin types and boundary scan cells pin type number of boundary scan cells usage input 1 input output 2 output, enable i/o 3 input, output, enable table 14 sequence of pins in the boundary scan boundary scan number tdi ??> pin number pin name type number of scan cells default value tdi ??> 1 7 cl15 i/o 3 0 10 28pdm3o20 0 323codei10 424sdxi10 525res i10
peb 24902 pef 24902 functional description data sheet 36 rev. 1, 2004-05-28 tap controller the test access port (tap) controller implements the state machine defined in the jtag standard ieee std. 1149.1. transitions on the pin tms cause the tap controller to perform a state change. the following instructions are executable. extest is used to examine the board interconnections. when the tap controller is in the state "update dr", all output pins are updated with the falling edge of tck. when it has entered state "capture dr" the levels of all input pins are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. intest supports internal chip testing. when the tap controller is in the state "update dr", all inputs are updated internally with the falling edge of tck. when it has entered state "capture dr" the levels of all outputs are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. note: 001 (intest) is the default value of the instruction register. 626clocki10 727dini10 838pdm0o20 0 939pdm1o20 0 10 40 pdm2 o 2 1 0 11 41 sdr o 2 0 1 table 15 tap controller instructions code instruction function 000 extest external testing 001 intest internal testing 010 sample/preload snap-shot testing 011 idcode reading id code 11x bypass bypass operation table 14 sequence of pins in the boundary scan (cont?d) boundary scan number tdi ??> pin number pin name type number of scan cells default value tdi ??>
peb 24902 pef 24902 functional description data sheet 37 rev. 1, 2004-05-28 sample/preload provides a snap-shot of the pin level during normal operation or is used to preload (tdi) / shift out (tdo) the boundary scan with a test vector. both activities are transparent to the system functionality. idcode register the 32-bit identification register is serially read out via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). the lsb is fixed to "1". note: 1. update of idcode register: new version number is 4 h 2. in the state "test logic reset" the code "0100" is loaded into the instruction code register. bypass , a bit entering tdi is shifted to tdo after one tck clock cycle, e.g. to skip testing of selected ics on a printed circuit board. version device code manufacturer code output 0100 0000 0000 0010 0110 0000 1000 001 1 --> tdo
peb 24902 pef 24902 operational description data sheet 38 rev. 1, 2004-05-28 4 operational description attention: any warranty, whether express or implied shall be subject to the use of the chips within the procedure as outlined in the respective data sheet. in case the chips are used incorrectly or not used within the logic or electrical specifications, any and all warranty or other claim based on any defect or malfunction whatsoever shall be excluded. 4.1 reset the reset is activated by setting pin res to low. the following functions are reset: the reset activates the power down of all line ports. the data on sdx is ignored during reset. sdr is set to low the range and the loop functions of all line ports are deactivated on a falling edge at the res pin, the pll is reset to its nominal frequency and starts to resynchronize after 130 ns. note: a running 15.36 mhz cl15 clock is required for this function. the sci the digital low pass filter all settings are maintained until res is high and the digital interface is synchronized. note: the system must not activate the iec-4-afe-x version 3.2 for at least 20 s after rising edge on res . 4.2 power-on-reset (por) when applying power to the iec-4-afe-x version 3.2 an internal power-on-reset is generated to reset the pll/oscillator and to set cl15 to an input. if a 15.36 mhz clock is generated by the internal pll/oscillator or if an external clock is provided at xin then cl15 becomes an output and issues this clock. if the supply voltage starts from a vdd voltag e below 1.0v the iec-4-afe-x version 3.2 guarantees proper por function with the restriction that the rising v dd slope has to be minor 5v/4 s. the por function is enabled again if the supply voltage v dd drops below 1.0 v for a minimum period of 80 ns (see figure figure 11 and table table 16 ). note: the res pin must be at "1" level during por to enable the reset of the pll/ oscillator.
peb 24902 pef 24902 operational description data sheet 39 rev. 1, 2004-05-28 figure 11 power-on-reset behavior of the iec-4-afe-x after v dd collapse 4.3 power down transmit path, receive path and auxiliary functions of the analog line port are switched to a low power consuming mode when the power down function is activated. this implies the following: the adc: the relevant pin pdmx is tied to gnd. the dac and the output buffer: the pins aoutx boutx are tied to gnd. the internal dc voltage reference is switched off. the range and the loop functions are deactivated. the digital transmit filter is set to low power consuming mode. table 16 parameters for por activation parameter limit values unit min. typ. max. maximum v dd slope (rising or falling) 5/4 v/s por enable threshold 1.0 4.5 v v dd below 1v-time 80 ns v dd time 5v 1v 0v min 80ns por_behavi our .vsd
peb 24902 pef 24902 operational description data sheet 40 rev. 1, 2004-05-28 the digital interface, the pll, and the level detection are not affected by the power down. the sci is fully functional, when scs = 1 (independently on the power down function of any channel). 4.4 power consumption all measurements with random 2b+d data in active states 1) , 5 v (-40c to 85c). 4.5 initialization and operation the initilialization sequence and operational procedures are described in detail in ref [9.] 1) reference sequence of afe v2.1 table 17 power consumption (4b3t adsl-friendly) parameter symbol limit values unit comment min. typ. max. 172 ? load at aoutx/boutx 1000 1150 mw all line ports are in power up 172 ? load at aoutx/boutx 275 mw one line port is in power up all inputs are tied to v dd or gnd 90 110 mw all line ports are in power down table 18 power consumption (2b1q adsl-friendly) parameter symbol limit values unit comment min. typ. max. 98 ? load at aoutx/boutx 1050 1200 mw all line ports are in power up 98 ? load at aoutx/boutx 290 mw one line port is in power up all inputs are tied to v dd or gnd 90 110 mw all line ports are in power-down
peb 24902 pef 24902 external circuitry data sheet 41 rev. 1, 2004-05-28 5external circuitry external circuitry meets electrical characteristic requirements of ref [3.] . any deviation from infineons recommendations for external circuitry may significantly degrade either isdn and / or adsl performance. attention: any warranty, whether express or implied shall be subject to the use of the chips within the procedure as outlined in the respective data sheet. in case the chips are used incorrectly or not used within the logic or electrical specifications, any and all warranty or other claim based on any defect or malfunction whatsoever shall be excluded. note: no return loss requirement is specified by ref [3.] . 5.1 terminating impedance of the line port (informative) according to ref [3.] and ref [4.] . 5.2 terminating impedance of the adsl port (informative) according to ref [3.] and ref [4.] . figure 12 terminating impedance of the adsl port z_adsl-i table 19 terminating impedance of the isdn port z_isdn terminating impedance symbol value unit 2b1q z line (2b1q) 135 ? 4b3t z line (4b3t) 150 ? c = 41.8 nf l = 82 h r = 100 ? c = 41.8 nf z_adsl-i c b = 27 nf z_adsl-i c b = 27 nf
peb 24902 pef 24902 external circuitry data sheet 42 rev. 1, 2004-05-28 note: 1. the purpose of this model impedance is for splitter specification, it is not a requirement on the input impedance of the adsl transceiver. 2. z_adsl-i does not include the blocking capacitors c b , which are part of the starpoint hybrid (see figure 13 ). 5.3 starpoint hybrid figure 13 starpoint hybrid table 20 parameters of the starpoint hybrid starpoint hybrid parameter symbol value unit min. typ. max. main inductance of blocking coils for 4b3t adsl-friendly l -10% 220 +10% h main inductance of blocking coils for 2b1q adsl-friendly l -10% 220 +10% h integrated voice and data solution (ivd) c b c b l l afe-x dfe geminax max line lat laa starpoint st arpoint hybrid
peb 24902 pef 24902 external circuitry data sheet 43 rev. 1, 2004-05-28 the distances between starpoint - afe-x (lat) and starpoint - geminax max (laa) shall not exceed the order of magnitude of typical linecard dimensions. note: for testing purposes (for instance psd measurement), it may be desirable to measure using etsis terminating impedance (z_adsl, see figure 12 ) instead of geminax max impedance. nevertheless, in ivd configuration, the blocking capacitors c b may be combined with capacitors of the geminax max external circuitry. the value of the resulting capacitance must conform to recommendation on geminax max external circuitry (specified in geminax? prel. application note ?adsl transformer and low pass definition?). remote power feeding according to ref [2.] is required. dc characteristics of l / c b shall be accordingly. 5.4 external circuitry 4b3t adsl-friendly figure 14 external circuitry - 4b3t adsl-friendly table 21 external circuitry parameters - 4b3t adsl-friendly parameter symbol value unit u-transformer: ep13 (t60403-m6384-x002) u-transformer ratio; device side : line side n 1:1.32 main inductance of windings on the line side l h 7.9 mh leakage inductance of windings on the line side l s <50 h star poi nt hybrid aout bout ain bin n c1 r4 >1 r4 r t r t r3 r3 afe-x_ext circ_4b3t
peb 24902 pef 24902 external circuitry data sheet 44 rev. 1, 2004-05-28 5.5 external circuitry 2b1q adsl-friendly figure 15 isdn external circuitry - 2b1q resistors 1% tolerance caps 5% tolerance (mkt or cog) coupling capacitance between the windings on the device side and the windings on the line side c k <40 pf dc resistance of the windings on device side r b 4 ? dc resistance of the windings on line side r l 5 ? hybrid parameters resistor r t 36.5 ? resistor r 3 6.04 k ? resistor r 4 2.87 k ? capacitor c 1 15 nf table 21 external circuitry parameters - 4b3t adsl-friendly (cont?d) parameter symbol value unit loop aout bout ain bin n c1 r4 >1 r4 r t afe-x_extcirc_2b1q r t r3 r3 r1 r2 c2 r5 r5
peb 24902 pef 24902 external circuitry data sheet 45 rev. 1, 2004-05-28 table 22 external circuitry parameters -2b1q adsl-friendly parameter symbol value unit u-transformer ep13 for 2b1q trtep13s-u255c013 rev2 u-transformer ratio; device side : line side n 1:1.6 main inductance of windings on the line side l h 14.5 mh leakage inductance of windings on the line side l s <90 h coupling capacitance between the windings on the device side and the windings on the line side c k <100 pf dc resistance of the windings on device side r b 6.3 ? dc resistance of the windings on line side r l 10 ? hybrid parameters resistor r t 19.1 ? resistor r 1 604 ? resistor r 2 2.67 k ? resistor r 3 10 k ? resistor r 4 9.1 k ? resistor r 5 549 ? capacitor c 1 33 1) 1) note: for better ground referecing, c1 may be resembled by three 22 nf capacitors, two of which form a rf path from each transformer node towards 0 v (gnd). nf capacitor c 2 6.8 nf
peb 24902 pef 24902 electrical characteristics data sheet 46 rev. 1, 2004-05-28 6 electrical characteristics 6.1 absolute maximum ratings attention: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. line overload protection the maximum input current (under over-voltage conditions) is given as a function of the width of a rectangular input current pulse. for the destruction current limits refer to figure 16 . table 23 absolute maximum ratings parameter symbol values unit note/ test condition min. max. max. storage and transportation temperature t s -65 150 c without power supply max. junction temperature t j 125 c? supply voltage v dd 7.0 v ? voltage on any pin v max -0.3 vdd + 0.3 max. 7.0 v? voltage between gndx to any other gndx ? v ss 0.3 v voltage between vddx to any other vddx ? v dd 0.3 v esd robustness hbm: 1.5 k ? , 100 pf v esd, hbm 2000 v according to eia/ jesd22-a114-b esd robustness v esd, sdm 500 v according to esd association standard ds5.3.1 - 1993
peb 24902 pef 24902 electrical characteristics data sheet 47 rev. 1, 2004-05-28 figure 16 maximum line input current 6.2 operating ambient temperature the operating ambient temperature for standard and extended temperature versions shall be in the limits as follows: 6.3 supply voltages vdd d1 to gnd d1 = +5 v 0.25 v vdd d2 to gnd d2 = +5 v 0.25 v vdd a0 to gnd a0 = +5 v 0.25 v vdd a1 to gnd a1 = +5 v 0.25 v vdd a2 to gnd a2 = +5 v 0.25 v vdd a3 to gnd a3 = +5 v 0.25 v table 24 operating ambient temperature version symbol values unit note/ test condition min. max. peb 24902 t ambient 0+70 c standard temperature range pef 24902 t ambient -40 +85 c extended temperature range
peb 24902 pef 24902 electrical characteristics data sheet 48 rev. 1, 2004-05-28 the following blocking circuitry is suggested ( figure 17 ). figure 17 power supply blocking 6.4 dc characteristics table 25 dc characteristics parameter symbol limit values unit test condition min. typ. max. high level input voltage v ih 2.4 v dd + 0.3 v low level input voltage v il ? 0.3 0.8 v low level input leakage current v il ? 10 av in = gnd vdd d2 100nf 100nf 100nf 100nf 100nf 100nf gnd 5 v 1f these capacitors should be located as near to the pins as possible 1) 1) 1) 1) 1) 1) 1) blocking_caps_afe.vsd vdd d1 vdd a3 vdd a2 vdd a1 vdd a0 gnd d2 gnd d1 gnd a3 gnd a2 gnd a1 gnd a0
peb 24902 pef 24902 electrical characteristics data sheet 49 rev. 1, 2004-05-28 6.5 ac characteristics 6.5.1 digital interface timing the ac characteristics of the iec-4-afe-x version 3.2 interface pins are optimized to fit to dfe-q/t version 2.2 if the following loads are no exceeded. no intermediate circuitry shall be inserted when connecting the iec-4-afe-x version 3.2 to dfe-q/t version 2.2. high level input leakage current i ih 10 av in = vdd high level output voltage (pin cl15, pin dout) v oh 4.4 v i oh = 5 ma high level output voltage (all other outputs) v oh 4.0 v i oh = 1 ma low level output voltage v ol 0.33 v i ol = 1 ma input capacitance c in 10 pf output leakage current (pull-down) pin 1, 4, 12, 14, 27, 43, 45, 48, 54 i pd 16 30 55 a0v< v in < v dd table 26 interface signals of iec-4-afe-x and dfe-q/dfe-t pin signal driving device max. capacitive load cl15 iec-4-afe-x 50 pf sdr iec-4-afe-x 20 pf pdm0..3 iec-4-afe-x 20 pf sdx dfe-t/dfe-q 20 pf table 25 dc characteristics (cont?d) parameter symbol limit values unit test condition min. typ. max.
peb 24902 pef 24902 electrical characteristics data sheet 50 rev. 1, 2004-05-28 6.5.2 boundary scan timing figure 18 boundary scan timing table 27 boundary scan timing parameter symbol values unit note/ test condition min. typ. max. test clock period t tcp 160 - ns test clock period low t tcpl 70 - ns test clock period high t tcph 70 - ns tms set-up time to tck t mss 30 - ns tms hold time from tck t msh 30 - ns tdi set-up time to tck t dis 30 - ns tdi hold time from tck t dih 30 - ns tdo valid delay from tck t dod -60ns tdo tdi tms tck t tcp t tcph t tcpl t mss t msh t dod t dih itt07144.vsd t dis
peb 24902 pef 24902 package outlines data sheet 51 rev. 1, 2004-05-28 7 package outlines figure 19 p-mqfp-64-9 hs (plastic metric quad flat package) r th_ja = 28 k/w (fea, pcb 2s2p, t ambient = 85 c, natural convection and radiation). note: this r th_ja = 28 k/w is calculated for a jedec test board (2s2p). the r th_ja on customer pcb may differ significantly from this value, dependant on the specific layout. no green materials (lead/halogen-free). gpm09456 smd = surface mounted device dimensions in mm you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products .
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