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general description the MAX17525 adjustable overvoltage, undervoltage, and overcurrent protection device guards systems against overcurrent faults in addition to positive overvoltage and reverse-voltage faults. when used with an optional external pmosfet, the device also protects downstream circuitry from voltage faults up to 60v (for -60v external pfet rating. the device features a low, 31m, on-resistance integrated fet. during startup, the devices are designed to charge large capacitances on the output in a continuous mode for applications where large reservoir capacitors are used on the inputs to downstream devices. additionally, the devices feature a dual-stage, current-limit mode in which the current is continuously limited to 1x, 1.5x, and 2x the programmed limit, respectively, for a short time after startup. this enables faster charging of large loads during startup. the MAX17525 also feature reverse-current and overtemperature protection. the devices are available in a 20-pin (5mm x 5mm) tqfn package and operate over the -40oc to 125oc temperature range. applications industrial power systems control and automation motion system drives human machine interfaces high-power applications benefts and features robust, high-power protection reduces system downtime ? wide operating input range: +5.5v to +60v ? -60v negative input tolerance with external pfet (for -(60 + v out ) external pfet rating) ? low 31m (typ) r on ? reverse current-blocking protection with external pfet enables fast startup and brownout recovery ? thermal foldback current-limit protection flexible design enables reuse and less requalification ? adjustable ovlo and uvlo thresholds ? programmable forward current limit from 0.6a to 6a with 15% accuracy over full temperature range ? normal and high-voltage enable inputs (en and hven ) ? protected external pfet gate drive saves board space and reduces external bom count ? 20-pin 5mm x 5mm tqfn package ? integrated nfet ordering information appears at end of data sheet. 19-8572; rev 0; 6/16 u v l o ov l o c l ts 1 h ve n 1 0 k p r ot e c te d p ow e r c i n c o u t c i n _ i c h ve n gn d p ow e r * r 1 , r 2 , r 3 , a nd r 4 a r e on l y r e q ure d fo r a d j u s t ab l e u v l o / ov l o f unc ti on a l i ty . ot h e r w i s e , ti e th e p i n to g nd to u se th e i n te rn a l , p r e - p r og r a mme d t hr es h ol d . 22 0 k gp c l ts 2 x r 4 * v i n r 1 * r 2 * v i n gn d r 3 * v i n i n i n i n i n i n ou t ou t ou t ou t ou t se ti r i pe n fl a g e n sys te m c on tr oll e r a d c sys te m i n p u t e n b fa u l t e n m a x 17525 typical application circuit MAX17525 high-accuracy, adjustable power limiter evaluation kit available
(all voltages referenced to gnd.) in (note 1) ............................................................. -0.3v to +62v out .............................................................. -0.3v to v in + 0.3v hven (note 1) ............................................. -0.3v to v in + 0.3v gp ..................................... max (-0.3v, v in - 20v) to v in + 0.3v uvlo, ovlo ............................... -0.3v to min (v in + 0.3v, 20v) flag , en, ripen, clts1, clts2 ......................... -0.3v to +6v maximum current into in (dc) (note 2) ................................. 6a seti ............................................... -0.3v to min (v in + 0.3v, 6v) continuous power dissipation (t a = +70oc) tqfn (derate 34.5mw/oc above +70oc) .................. 2758mw operating temperature range .......................... -40oc to +125c junction temperature ...................................................... +150c storage temperature range ............................. -65oc to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c electrical characteristics (v in = 5.5v to 60v, t a = -40c to +125c, unless otherwise noted. typical values are at v in = 12v, t a = +25c) (note 4) note 1: an external pfet or diode is required to achieve negative input protection. note 2: dc current-limited by r seti , as well as by thermal design. parameter symbol conditions min typ max units power supply in voltage range v in 5.5 60 v shutdown in current i shdn v en = 0v, v hven = 5v, v in < 40v 4 15 a v en = 0v, v hven = 5v 4 150 supply current i in v in = v out = 24v, v hven = 0v 1.4 2.16 ma shutdown out current i off v en = 0v, v hven = 5v 50 100 a uvlo, ovlo internal uvlo trip level v uvlo v in falling, uvlo trip point 11.5 12 12.5 v v in rising 11.9 12.4 13.1 uvlo hysteresis % of typical uvlo 3 % internal ovlo trip level v ovlo v in falling 32.2 34.1 35.8 v v in rising, ovlo trip point 34.7 36.2 37.6 ovlo hysteresis % of typical ovlo 6 % external uvlo adjustment range (note 5) 5.5 24 v external uvlo select voltage v uvlo_sel 0.15 0.38 0.5 v external uvlo leakage current i uvlo_leak -250 +250 na external ovlo adjustment range (note 5) 6 40 v external ovlo select voltage v ovlo_sel 0.15 0.38 0.5 v external ovlo leakage current i ovlo_leak -250 +250 na external uvlo/ovlo set voltage v set 1.18 1.22 1.27 v maxim integrated 2 absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. tqfn junction-to-ambient thermal resistance ( ja ) ........... 29c/w junction-to-case thermal resistance ( jc ) ................. 2c/w (note 3) note 3: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . package thermal characteristics MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
electrical characteristics (continued) (v in = 5.5v to 60v, t a = -40c to +125c, unless otherwise noted. typical values are at v in = 12v, t a = +25c) (note 4) parameter symbol conditions min typ max units undervoltage trip level on out v uvlo_out v out falling, uvlo trip point 11.5 12 12.5 v v out rising 11.9 12.4 13 gp gate clamp voltage v gp 10 16.1 20 v gate active pullup 11 22 gate active pulldown v en = 5v 47 110 a shutdown gate active pullup v en = 0v, v hven = 5v 2.4 m internal fets internal fets on-resistance r on i load = 100ma, v in 10v, t a = +25oc 31 44 m current limit adjustment range i lim 0.6 6 a current limit accuracy i lim_acc 1a i lim 6a (t a = +25c) -10 +10 % 0.6a i lim 6a -15 +15 flag assertion drop voltage threshold v fa increase in (v in - v out ) drop until flag asserts, v in = 24v 490 mv slow reverse current-blocking threshold v rib_slow v in - v out -0.5 -5.4 -10.5 mv slow reverse current-blocking response time t rib_slow see the slow reverse-current fault timing diagram 17 30 s fast reverse current-blocking threshold v rib_fast v in - v out -85 -100 -115 mv fast reverse current-blocking response time t rib_fast (v in - v out ) changes from 0.2v to -0.3v in 100nsec, t rib is the interval between v in - v out = v rib_fast and v in-gp = 0.5v with c in-gp = 5nf 0.7 1 s reverse-blocking supply current i rbs v out = 24v 3280 5110 a logic input ( hven , clts1, clts2, en, ripen) hven threshold voltage v hven _th 1 2 3.1 v hven threshold hysteresis 5 % hven input leakage current i hven _leak v hven = 60v 51 72 a en, ripen, clts1, clts2 input logic-high v ih 1.4 v en, ripen, clts1, clts2 input logic-low v il 0.4 v en input leakage current i en_leak v en = 0v, 5v -1 +1 a clts_ leakage current clts_ = gnd 25 a ripen leakage current i riben_leak ripen = gnd 25 a maxim integrated 3 MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
electrical characteristics (continued) (v in = 5.5v to 60v, t a = -40c to +125c, unless otherwise noted. typical values are at v in = 12v, t a = +25c) (note 4) note 4: all devices are 100% production-tested at t a = +25c. specifications over the operating temperature range are guaranteed by design. note 5: not production-tested, user-adjustable. see the overvoltage lockout (ovlo) and undervoltage lockout (uvlo) sections. note 6: all timing is measured using 20% and 80% levels, unless otherwise specified. note 7: the autoretry time-to-blanking time ratio is fixed and is equal to 30. parameter symbol conditions min typ max units logic output ( flag ) logic-low voltage i sink = 1ma 0.4 v input leakage current v in = 5.5v, flag deasserted 1 a seti r seti x i lim v ri see the setting the current-limit threshold section 1.5 v current mirror output ratio c iratio see the setting the current-limit threshold section 25000 dynamic performance (note 6) switch turn-on time t on v in = 24v, switch off to on, r load = 240, i lim = 1a, c out = 4.7f, v out from 20% to 80% of v in 68 s fault recovery nfet turn-on time t on_nfet turn-on delay after fault timers expired 200 500 s fault recovery pfet turn-on time t on_pfet v out > v uvlo_out , turn-on delay of pfet after fault timers expired 1.08 1.2 1.32 ms reverse-current fault recovery time t rev_rec 0.4 0.45 0.5 ms ovp switch response time t ovp_res 3 s overcurrent switch response time t ocp_res i lim = 4a 3 s startup timeout t sto initial start current-limit foldback timeout (figure 1) 1090 1200 1320 ms startup initial time t sti current is continuously limited to 1x/1.5x/2x in this interval (figure 1) 21.8 24 26.4 ms in debounce time t deb additional turn-on delay if v out < v uvlo_out , see the timing diagrams 1.09 1.2 1.32 ms blanking time t blank (figures 3 and 4) 21.8 24 26.4 ms autoretry time t retry (figure 3, note 7) 554 720 792 ms thermal protection thermal foldback t j_fb 150 c thermal shutdown t j_max 170 c thermal-shutdown hysteresis 20 c maxim integrated 4 MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
figure 1. startup timing figure 2. debounce timing i out out in ovlo t deb + t on _ nfet t sto * thermally controlled current foldback v in i limit uvlo gnd t j t j_fb t sti not drawn to scale * if out does not reach v in - v fa within t sto , the device is latched off , and en , hven , or in must be toggled to resume normal operation . in uvlo t deb + t on _ nfet < t deb < t deb off on switch status ovlo not drawn to scale maxim integrated 5 timing diagrams MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
(v in = 12v, c in = 1f, c out = 4.7f, t a = +25c, unless otherwise noted.) 0.90 0.95 1.00 1.05 1.10 5 10 15 20 25 30 35 40 45 50 55 60 normalized on - resistance in voltage (v) normalized on - resistance vs. supply voltage toc04 normalized to v in = 12v i out = 1a v en = 5v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 5 10 15 20 25 30 35 40 45 50 55 60 quiescent current (ma) in voltage (v) quiescent in current vs. in voltage toc01 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -50 -25 0 25 50 75 100 125 150 quiescent current (ma) temperature ( c) quiescent in current vs. temperature toc02 v in = 13v v in = 24v v in = 34v 0 10 20 30 40 50 60 70 80 90 100 0 12 24 36 48 60 hven input current (a) v hven (v) hven input current vs. v hven toc03 t a = - 40 c t a = 25 c t a = 85 c t a = 125 c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -50 -25 0 25 50 75 100 125 150 normalized on - resistance temperature ( c) normalized on - resistance vs. temperature toc05 v in = 24v i out = 1a v en = 5v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 normalized on - resistance output current (a) normalized on - resistance vs. output current toc06 v en = 5v normalized to v in = 24v i out = 1a v en = 5v 0.95 0.96 0.97 0.98 0.99 1 1.01 1.02 1.03 1.04 1.05 5 10 15 20 25 30 35 40 45 50 55 60 normalized current limit in voltage (v) normalized current limit vs. supply voltage toc07 normalized to v in = 12v r ilim = 37.5k maxim integrated 6 typical operating characteristics MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
(v in = 12v, c in = 1f, c out = 4.7f, t a = +25c, unless otherwise noted.) 0.97 0.98 0.99 1 1.01 1.02 1.03 -50 -25 0 25 50 75 100 125 150 normalized current limit temperature ( c) normalized current limit vs. temperature toc08 normalized to t a = +25 o c v in = 24v r ilim = 37.5k 0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 150 shutdown in current (a) temperature ( c) shutdown in current vs. temperature toc09 60v in 34v in 24v in 12v in 5.5v in 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -50 -25 0 25 50 75 100 125 150 fet leakage current (a) temperature ( c) fet leakage current vs. temperature toc10 v in = +12v v in = +24v 0 20 40 60 80 100 120 140 160 180 200 -50 -25 0 25 50 75 100 125 150 turn - on time ( s) temperature ( c) switch turn - on time vs. temperature toc11 MAX17525 v in = +24v r l = 240 c l = 4.7 f 0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 150 turn - off time ( s) temperature ( c) switch turn - off time vs. temperature toc12 v in = +24v r l = 240 c l = 4.7 f po w er - u p r espo n se 20v / d i v 200 m s/ d i v v i n v o u t i o u t 20v / d i v 1a / d i v t oc 13 c l = 33 m f i l i m = 2.9 a p o w er - u p r esp o n se 20v / d i v 200 m s/ d i v v i n v o u t i o u t 20v / d i v 1a / d i v t oc 13 c l = 33 mf i l i m = 2 . 9 a reverse - blocking response 20v/div 10s/div v in v out i out 20v/div 5a/div maxim integrated 7 typical operating characteristics (continued) MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
(v in = 12v, c in = 1f, c out = 4.7f, t a = +25c, unless otherwise noted.) fl a g r esp o n se 20v / d i v 4 s/ d i v v i n v o u t v fl a g \ 20v / d i v 5v / d i v t oc 15 0 v 0 v curr e n t - l i m i t r esp o n se 20v / d i v 10 m s/ d i v v i n v o u t i o u t 20v / d i v 1a / d i v t oc 16 0 v 0 v i l i m = 1a i l = 100 m a t o s udd e n s h o r t app li e d curr e n t - l i m i t r espo n se 20v / d i v 10 m s/ d i v v i n v o u t i o u t 20v / d i v 1a / d i v t oc 17 0 v 0 v i l i m = 1a i l = 100 m a t o s h o r t o n o u t w it h 1 a /s bl a nk i n g t i m e 10 m s/ d i v i o u t 1a / d i v t oc 18 v o u t 20v / d i v a u to -r e t r y m o d e a u t o r e t r y t i m e 200 m s/ d i v i o u t 1a / d i v t oc 19 v o u t 20v / d i v a u t o r e t ry m o de au t o re t r y t i me 200 m s/ d i v i o u t 1a / d i v t oc 19 v o u t 20v / d i v a u t o r e t r y m o d e maxim integrated 8 typical operating characteristics MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
pin name function 1C5 in switch input. bypass in to ground with a 1f ceramic capacitor. in applications in which an external pfet is used, a 4.7f capacitor should be placed at the drain of the pfet and a reduced capacitor of 10nf to 100nf should be placed at in. the maximum slew rate allowed at in is 30v/s. in serves as the undervoltage/overvoltage sensed input when preprogrammed uvlo/ovlo is used. 6 gp gate driver output for external pfet. 7 seti overload current-limit adjust. connect a resistor from seti to gnd to program the overcurrent limit. seti must be connected to a resistor. if seti is connected to gnd during startup, then the switch does not turn on. do not connect more than 30pf to seti. 8 flag open-drain fault indicator output. flag asserts low when the v in - v out voltage exceeds v fa , reverse current is detected, thermal shutdown mode is active, ovlo or uvlo threshold is reached, or seti is connected to gnd. 9 ovlo externally-programmable overvoltage-lockout threshold. connect ovlo to gnd to use the default internal ovlo threshold. connect ovlo to an external resistor-divider to defne a threshold externally and override the preset internal ovlo threshold. 10 uvlo externally programmable undervoltage-lockout threshold. connect uvlo to gnd to use the default internal uvlo threshold. connect uvlo to an external resistor-divider to defne a threshold externally and override the preset internal uvlo threshold. 11C15 out switch output. bypass out to gnd with a 4.7f ceramic capacitor placed as close as possible to the device. 16 ripen reverse-current protection enable. connect ripen to gnd with 10k pulldown resistor to disable the reverse-current fow protection. leave ripen open or connect ripen to logic-high to activate the reverse-current fow protection. 17 hven 60v capable active-low enable input. see table 1. 18 clts2 current-limit type select 2. see table 2. 19 clts1 current-limit type select 1. see table 2. 20 en active-high enable input. see table 1. gnd/ep ground/exposed pad. connect to a large copper ground plane to maximize thermal performance. ma x 17525 tqfn ( 5 mm x 5 mm ) top view gnd / ep + in in in in out out out out clts 2 clts 1 en ovlo flag seti gp in out hven uvlo ripen 10 9 8 7 6 11 12 13 14 15 16 17 18 19 20 5 4 3 2 1 maxim integrated 9 pin description pin confgurations MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
c l ts 1 c l ts 2 o u t g n d r i p e n f l a g gp i n c h a r ge p u m p c o n t r ol c u r r e n t l i m i t c o n tr ol r e v e r s e c u r r e n t fl ow c on t r ol c o n tr ol l og i c v s e t 5 v 1 5 0 k v u v l o _ s e l v o v l o _s e l h v e n e n u ov l o v l o i n i n i n i n ou t ou t ou t ou t s e ti m a x 1 7 5 2 5 1 5 0 5 v k 1 5 0 k v s e t maxim integrated 10 functional diagram MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
detailed description the MAX17525 adjustable overvoltage, undervoltage, and overcurrent protection devices guard systems against overcurrent faults in addition to positive overvoltage and reverse-voltage faults. when used with an optional external pmosfet, the devices also protect downstream circuitry from voltage faults up to +60v, -60v (for -(60 + v out ) external pfet rating). the devices feature a low, 31m, on-resistance integrated fet. during startup, the devices are designed to charge large capacitances on the output in a continuous mode for applications where large reservoir capacitors are used on the inputs to downstream devices. additionally, the device features a dual-stage current-limit mode in which the current is continuously limited to 1x, 1.5x, and 2x the programmed limit, respectively, for a short time after startup. this enables faster charging of large loads during startup. the devices feature the option to set the overvoltage- lockout (ovlo) and undervoltage-lockout (uvlo) thresholds manually using external voltage-dividers or to use the fac - tory-preset internal thresholds by connecting the ovlo and/or uvlo pin(s) to gnd. the permitted external overvoltage setting range of the devices is 6v to 40v. therefore, the pfet and internal nfet must be kept off in the 40v to 60v range by appropriate ovlo resistor- divider. the devices programmable current-limit threshold can be set for currents up to 6a in autoretry, latchoff, or continuous-fault-response mode. when the device is set to autoretry mode and the current exceeds the threshold for more than 24ms (typ), both fets are turned off for 720ms (typ), then turned back on. if the fault is still present, the cycle repeats. in latchoff mode, if a fault is present for more than 24ms (typ), both fets are turned off until enable is toggled or the power is cycled. in continuous mode, the current is limited continuously to the programmed current-limit value. in all modes, flag asserts if v in - v out is greater than the flag assertion drop voltage threshold (v fa ). startup control the devices feature a dual-stage startup sequence that continuously limits the current to 1x/1.5x/2x the set current limit during the startup initial time (t sti ), allowing large capacitors present on the output of the switch to be rapidly charged. the MAX17525 limits the current to 1x the set limit during this period. if the tem - perature of any device rises to the thermal-foldback threshold (t j_fb ), the device enters power-limiting mode ( figure 1 ). in this mode, the device thermally regulates the current through the switch to protect itself while still delivering as much current as possible to the output regardless of the current-limit type selected. if the output is not charged within the startup timeout period (t sto ), the switch turns off and in, en, or hven must be toggled to resume nor - mal operation. the t sto timout period is also applied when there is a restart after a turn-off event caused by uvlo, ovlo, or reverse-current block event. if the output is not charged to (v in - v fa ) level during this time, the device turns off and in, en, or hven must be toggled to resume normal operation. overvoltage lockout (ovlo) the devices feature two methods for determining the ovlo threshold. by connecting the ovlo pin to gnd, the preset internal ovlo threshold of 36v (typ) is selected. if the voltage at ovlo rises above the ovlo select threshold (v ovlo_sel ), the device enters adjustable ovlo mode. connect an external voltage-divider to the ovlo pin, as shown in the typical application circuit to adjust the ovlo threshold. r3 = 2.2m is a good starting value for minimum current consumption. since v set is known, r3 has been chosen, and v ovlo is the target ovlo value, r4 can then be calculated by the following equation: set ovlo set r3 v r4 vv = ? undervoltage lockout (uvlo) the devices feature two methods for determining the uvlo threshold. by connecting the uvlo pin to gnd, the preset, internal uvlo threshold of 12v (typ) is selected. if the voltage at uvlo rises above the uvlo select threshold (v uvlo_sel ), the device enters adjustable uvlo mode. connect an external voltage-divider to the uvlo pin, as shown in the typical application circuit to adjust the uvlo threshold. r1 = 2.2m is a good starting value for minimum current consumption. since v set is known, r1 has been chosen, and v uvlo is the target value, r2 can then be calculated by the following equation: = ? set uvlo set r1 v r2 vv maxim integrated 11 MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
switch control there are two independent enable inputs on the devices: hven and en. hven is a high-voltage-capable input, accepting signals up to 60v. en is a low-voltage input, accepting a maximum voltage of 5v. in case of a fault condition, toggling hven or en resets the fault. the enable inputs control the state of the switch based on the truth table ( table 1 ). input debounce the devices feature a built-in input debounce time (t deb ). the debounce time is a delay between a por event and the switch being turned on. if the input voltage rises above the uvlo threshold voltage or if, with a voltage greater than v uvlo present on in, the enable pins toggle to the on state, the switch turns on after t deb . in cases where the voltage at in falls below v uvlo before t deb has passed, the switch remains off ( figure 2 ). if the voltage at out is already above v uvlo_out when the device is turned on through either enable pin or coming out of ovlo, there is no debounce interval. this is due to the device already being out of the por condition with out above v uvlo_out . current-limit type select the MAX17525 feature three selectable current-limiting modes. during power-up, all devices default to continuous mode and follow the procedure defined in the startup control section. once the part has been successfully powered on and t sto has expired, the device senses the condition of clts1 and clts2. the condition of clts1 and clts2 sets the current-limit mode type according to table 2 . clts1,2 are internally pulled up to an internal 5v supply. therefore, the device is in continuous current-limit mode when clts1 and 2 are open. to set clts_ state to low, connect a 10k resistor or below to ground. in addition to the selectable current-limiting modes, the device has a protection feature against a severe over load condition. if the output current exceeds 2 times the set current limit, the device will turn off the internal nfet and external pfet immediately and will attempt to restart to allow the overcurrent to last for t blank time. the off duration depends on fault condition occurred after the fets turn off, with the shortest duration of 420us (t on_fet ) if there is no fault. in lacthoff mode, the device will latch off if the overcurrent fault last longer than t blank . autoretry mode ( figure 3 ) in autoretry current-limit mode, when current through the device reaches the threshold, the t blank timer begins counting. the flag output asserts low when the voltage drop across the switch rises above v fa . if the overcurrent condition is present for t blank , the switch is turned off. the timer resets if the overcurrent condition disappears before t blank has elapsed. a retry time delay (t retry ) starts immediately once t blank has elapsed. during the retry time, the switch remains off and, once t retry has elapsed, the switch is turned back on. if the fault still exists, the cycle is repeated and flag remains low. if the fault has been removed, the switch stays on. the autoretry feature reduces system power in case of overcurrent or short-circuit conditions. when the switch is on during t blank time, the supply current is held at the current limit. when the switch is off during t retry time, there is no current through the switch. thus, the output current is much less than the programmed current limit. calculate the average output current using the following equation: blank sti load lim blank retry sti t tk i i ttt ?? + = ?? ++ ?? where k is the multiplication factor of the initial current limit (1x, 1.5x or 2x). with a 24ms (typ) t blank, 24ms t sti , k = 1 and 720ms (typ) t retry , the duty cycle is 3.1%, resulting in 97% power saving when compared to the switch being on the entire time. latchoff mode ( figure 4 ) in latchoff current-limit mode, when current through the device reaches the threshold, the t blank timer begins counting. flag asserts when the voltage drop across the switch rises above v fa . the timer resets if the overcurrent condition disappears before t blank has elapsed. the switch turns off if the overcurrent condition remains for the blanking time. the switch remains off until the control logic (en or hven ) is toggled or the input voltage is cycled. table 1. enable inputs hven en switch status 0 0 on 0 1 on 1 0 off 1 1 on table 2. current-limit type select clts2 clts1 current-limit type 0 0 latchoff mode 0 1 autoretry mode 1 0 continuous mode 1 1 continuous mode maxim integrated 12 MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
figure 3. autoretry fault diagram v out t retry v in flag i limit i out 1 x / 1 . 5 x / 2 x i limit not drawn to scale v uvlo < v in < v ovlo , hven = low , en = high v uvlo _ out t blank t blank t retry t sti t blank t deb + t on _ nfet t sti 1 x / 1 . 5 x / 2 x i limit v fb t on _ nfet 0 figure 4. latchoff fault diagram v out i out i limit v in t blank t blank hven en flag not drawn to scale v uvlo < v in < v ovlo v uvlo _ out t sti t deb + t on _ nfet 1 x / 1 . 5 x / 2 x i limit 1 x / 1 . 5 x / 2 x i limit t blank t sti v fb t on _ nfet 0 maxim integrated 13 MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
continuous mode ( figure 5 ) in continuous current-limit mode, when current through the device reaches the threshold, the device limits the current to the programmed limit. flag asserts when the voltage drop across the switch rises above v fa , and deasserts when it falls below v fa . reverse-current blocking ( figure 6 , figure 7 ) the devices feature current-blocking functionality to be used with external pfet. to enable the reverse-current blocking feature, pull ripen high or leave ripen unconnected as it is internally pulled high. with ripen high, if a reverse- current condition is detected (v in - v out < v rib_ ), the internal nfet and the external pfet are turned off for 450s (t rev_rec ). during and after this time, the device monitors the voltage difference between out and in pins to determine whether the reverse current is still present. once t rev_rec expired and the reverse-current condition has been removed, the nfet and pfet are turned back on after an additional time delay followed by the dual-stage startup control mechanism, defined in the startup control section above, is applied. the additional time delay will be 200s (t on_nfet ) for nfet and 1.2ms (t on_pfet ) for pfet if voltage at out is greater than or equal to v uvlo_ out falling at the end of t rev_rec delay, otherwise the delay will be 1.4ms (t deb + t on_nfet ) for nfet and 2.4ms (t deb + t on_pfet ) for pfet. after a reverse-current event, the device will attempt a restart regardless of the current- type select. the device contains two reverse-current thresholds with slow (< 30s) and fast (< 1s) response time for reverse current protection. this feature results in robust operation in a noisy environment, while still delivering fast protection for severe fault, such as input short circuit. figure 5. continuous fault diagram i out in v out hven en flag t j i limit uvlo ovlo t deb + t on _ nfet 1 x / 1 . 5 x / 2 x i limit t sto thermal current limit t sti v in t jmax not drawn to scale v out _ uvlo 1 x / 1 . 5 x / 2 x i limit t sti thermal current limit v fa t on _ nfet 0 maxim integrated 14 MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
figure 6. slow reverse-current fault timing diagram t rib_slow v rib_slow (v in -v out ) 0v t rib_slow t rev_rec v d_pfet v out t on_nfet v in -v gp 0v t on_pfet v uvlo_out i out 0a i load -(v rib_slow /r on ) nmos _off t rib_slow t rev_rec t deb t on_nfet t on_pfet 1 x/1.5x/2x i limit 1x/1.5x/2x i limit fault indicator ( flag) output flag is an open-drain fault-indicator output. it requires an external pullup resistor to a dc supply. flag asserts when any of the following conditions occur: v in - v out > v fa reverse-current protection is tripped die temperature exceeds +170c seti is connected to ground uvlo threshold has not been reached ovlo threshold is reached thermal shutdown protection thermal-shutdown circuitry protects the devices from overheating. the switch turns off and flag asserts when the junction temperature exceeds +170c (typ). the devices exit thermal shutdown and resume normal operation once the junction temperature cools by 20c (typ) when the device is in autoretry or continuous current-limiting mode. when in latchoff mode, the device remains latched off until the input voltage is cycled or one of the enable pins is toggled. the thermal shutdown technology built into the devices behave in accordance with the selected current-limit mode. while the devices are in autoretry mode, the thermal limit uses the autoretry timing when coming out of a fault condition. when the devices detect an overtemperature fault, the switch turns off. once the temperature of the junction falls below the falling thermal threshold, the device turns on after the time interval t retry . in latchoff mode, the device latches off until the input is cycled or one of the enable pins is toggled. in continuous current- limiting mode, the device turns off while the temperature is over the limit, then turns back on after t deb when the temperature reaches the falling threshold. there is no retry time for thermal protection. maxim integrated 15 MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
figure 7. fast reverse-current fault timing diagram t rib_slow v rib_slow (v in - v out ) 0v t rib_fast t rev_rec v d_pfet v out t on_nfet v in -v gp 0v t on_pfet v uvlo_out i out 0a i load -(v rib_slow /r on ) nmos _off t rev_rec t deb t on_nfet t on_pfet v rib_fast - (v rib_fast /r on ) t rib_fast 1x/1.5x/2x i limit 1x/1.5x/2x i limit figure 8. overvoltage fault timing diagram t deb t on_nfet t on_pfet 1x/1.5x/2x i limit 1x/1.5x/2x i limit ovlo v out v in - v gp 0v i out 0a i load nmos_off v in v uvlo_out maxim integrated 16 MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
applications information setting the current-limit threshold connect a resistor between seti and ground to program the current-limit threshold for the devices. leaving seti unconnected sets the current-limit threshold to 0a and, since connecting seti to ground is a fault condition, this causes the switch to remain off and flag to assert. use the following formula to calculate the current-limit threshold: ri seti iratio lim v ( a) r (k ) c i (ma) ? ?= do not use a r seti smaller than 6k. table 3 shows current- limit thresholds for different resistor values at seti. a current mirror with a ratio of c iratio is implemented with a current-sense auto-zero operational amplifier. the mirrored current of the in-out fet is provided on the seti pin. therefore, the voltage (v seti ) read on the seti pin should be interpreted as the current through the in-out fet, as shown below: seti in out seti iratio seti seti iratio lim ri v (v) i ic r (k ) v (v) ci v (v) ? == ? = in bypass capacitor in application in which an external pfet is not used, connect a minimum of 1f capacitor from in to gnd to limit the input voltage drop during momentary output short-circuit conditions. larger capacitor values further reduce the voltage droop at the input caused by load transients. in applications in which an external pfet is used a 4.7f capacitor is placed at the drain of the pfet, and capacitor at in is reduced to 10nf (100nf, max). hot plug-in in many power applications, an input filtering capacitor is required to lower the radiated emission and enhance the esd capability, etc. in hot-plug applications, parasitic cable inductance, along with the input capacitor, causes overshoot and ringing when a powered cable is suddenly connected to the input terminal. this effect causes the protection device to see almost twice the applied voltage. an input voltage of 24v can easily exceed 40v due to ringing. the devices contain internal protection against hot-plug input transient. on the in pins,with slew rate up to 30v/s. however, in the case where the harsh industrial emc test is required, use a transient voltage suppressor (tvs) placed close to the input terminal that is capable of limiting the input surge to 60v. out capacitance for stable operation over the full temperature range and over the entire programmable current-limit range, connect a 4.7f ceramic capacitor from out to ground. other circuits connected to the output of the device may introduce additional capacitance, but it should be noted that excessive output capacitance on the devices can cause faults. if the capacitance is too high, the devices may not be able to charge the capacitor before the startup timeout. calculate the maximum capacitive load (c max ) value that can be connected to out using the following formula: s t i s t o m a x l im in _ m a x ( m 1 ) t ( m s) t ( m s ) c ( m f ) i ( a ) v ( v ) ? ? ? + = ? ? ? ? ? ? m x t sti (ms) + t s t o (ms) where m is the multiplier (1x/1.5x/2x) applied to the current limit during startup. for example, when using MAX17525, if v in_max = 30v, t sto (min) = 1090ms, t sti (min) = 22ms, and i lim = 3a, c max results in the theoretical maximum of 111mf. in this case, any capacitance larger than 111mf will cause a fault condition because the capacitor cannot be charged to a sufficient voltage before t sto has expired. in practical applications, the output capacitor size is limited by the thermal performance of the pcb. poor thermal design can cause the thermal-foldback current-limiting function of the device to kick in too early, which may further limit the maximum capacitance that can be charged. therefore, good thermal pcb design is imperative to charge large capacitor banks. table 3. current-limit threshold vs. resistor values r seti (k) current limit (a) 62.5 0.6 37.5 1.0 25.0 1.5 18.75 2.0 15.0 2.5 12.5 3.0 10.7 3.5 9.375 4.0 8.3 4.5 7.5 5.0 6.82 5.5 6.25 6.0 maxim integrated 17 MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
out freewheeling diode for inductive hard short to ground in applications with a highly inductive load, a freewheeling diode is required between the out terminal and gnd. this protects the device from inductive kickback that occurs during short-to-ground events. pcb layout recommendations to optimize the switch response to output short-circuit conditions, it is important to reduce the effect of undesirable parasitic inductance by keeping all traces as short as possible. place input and output capacitors as close as possible to the device (no more than 5mm). in and out must be connected with wide short traces to the power bus. during steady-state operation, the power dissipation is typically low and the package temperature change is usually minimal. pcb layout designs need to meet two challenges: high-current input and output paths and important heat dissipation. heat dissipation maxim recommends the use of 2oz copper on fr4 isolator in a four-layer configuration. the layer stack needs to be top (routing), gnd (plane), power (plane, connected to v out ) and bottom (routing), in this order, from top to bottom. install the ic on an exposed pad landing of minimum 100 x 100 mils, with at least five through vias to the gnd plane. the vias should be 32mils in diameter, with a 16mils plated hole. the hole plating needs to be at least 0.5oz copper. provide a minimum of 1in x 1in area of copper plane on all four layers. it is important to remember that the inner planes do not contribute much to heat dissipation, due to fr4 isolation, but are important from an electrical point of view. if possible, keep the top and bottom copper areas clear of solder mask, as this will greatly improve heat dissipation. use a similarly large copper area connected directly to the out pins. a dimension of 1in x 1in is also recommended. this might look oversized for current path requirements, but is essential for heat dissipation. keep in mind that heat is generated at the drain junction of the internal nmos pass fet, which is then eliminated through the five out pins and needs to be dissipated on this same copper area. current path requirements connect all five in pins to a copper area that is at least 150mils wide. using 2oz copper may reduce this requirement to 100mils. remember to provide the same copper trace width on the source connection, when using the external pmos pass fet (with the source connected to the in pins). use extreme caution when placing the decoupling capacitors to the in and out pins. the tendency to go as close as possible to the ic pins might interfere with the minimum requirement of the trace width above. it is important to note that the return load current does not flow through the ic; therefore, it is important to provide an external ground trace of at least the same width as the input/output one. maxim recommends the use of a gnd plane. connect the input and output grounds to this plane using at least four plated vias each. the vias should be 84mils in diameter (or 60mils x 60mils, if square), with a 35mils plated hole. additional information for more information on heat dissipation, see the ic application section on http://www.maximintegrated. com . hbm esd protection figure 9 shows the human body model and figure 10 shows the current waveform it generates when discharged into low impedance. this model consists of a 100pf capacitor charged to the esd voltage of interest, which is then discharged into the device through a 1.5k resistor. maxim integrated 18 MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 20 tqfn-ep t2055+5c 21-0140 90-0010 ordering information part initial current limit temp range pin-package MAX17525atp+t 1.0x -40c to +125c 20 tqfn-ep* + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. * ep = exposed pad. figure 9. human body esd test model high - voltage dc source device under test charge - current - limit resistor storage capacitor discharge resistance r c 1 m? r d 1 . 5 k? figure 10. human body current waveform ip 100% 90% 36.8% 10% 0 amperes time t dl t rl current waveform i r maxim integrated 19 chip information process: bicmos MAX17525 high-accuracy, adjustable power limiter www.maximintegrated.com
revision history revision number revision date description pages changed 0 6/16 initial release ? 2016 maxim integrated products, inc. 20 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. MAX17525 high-accuracy, adjustable power limiter for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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