september 2011 doc id 18332 rev 1 1/10 10 USBULC6-2N4 ultralow capacitance esd protec tion for high speed interface features 2-line tvs diodes ultralow capacitance 0.6 pf typ. 1.0 x 0.8 mm package 0.4 mm pitch lead-free package benefits flow-through layout easy to implement low profile: 0.55mm height max very low pcb space: only 0.8 mm2 complies with following standards iec 61000-4-2 level 4: ? 15 kv (air discharge) ? 8 kv (contact discharge) applications where transient over-voltage protection in esd sensitive equipment is required, such as: computers printers communication systems cellular phone handsets and accessories video equipment description the USBULC6-2N4 is a monolithic application specific discrete device dedicated to esd protection of high speed data buses. the device is available in the qfn-4l package. figure 1. configuration (top view) figure 2. application diagram qfn-4l i/o1 nc gnd i/o2 nc mini - usb connector usbulc6 - 2n4 usb transceiver i/o1 nc i/o2 nc www.st.com
characteristics USBULC6-2N4 2/10 doc id 18332 rev 1 1 characteristics figure 3. junction capacitance versus frequency ( v r = 0 v, typical values) table 1. absolute maximum ratings t amb = 25 c symbol parameter value unit v pp esd discharge iec 61000-4-2, level 4 contact discharge air discharge 12 15 kv i pp peak pulse current (8/20 s) 4 a p pp peak pulse power dissipation (8/20 s) 50 w t j operating temperature range -40 to + 150 c t stg storage temperature range -65 to +150 c t l maximum lead temperature for soldering during 10 s 260 c table 2. electrical characteristics t amb = 25 c, otherwise specified symbol parameter test cond itions min. typ. max. unit v br lv diode breakdown voltage i r = 1 ma 6 v i rm lv diode leakage current v rm = 3 v 100 na c lv diode input capacitance v r = 0 v, f= 240 mhz to 3 ghz any i/o pin to ground 0.6 0.75 pf v cl lv diode clamping voltage i pp = 1 a, t p = 8/20 s any i/o pin to ground 10 v 0.00 0.25 0.50 0.75 1.00 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 c(pf) f=1mhz ? 3ghz v osc =30mv rms vr=0v t j =25 c a1/gnd a2/gnd f(mhz)
USBULC6-2N4 characteristics doc id 18332 rev 1 3/10 figure 4. variation of leakage current versus junction temperature (typical values) figure 5. attenuation measurement 0.01 1.00 100.00 25 50 75 100 125 150 i r (na) v r =v rm= 3v a1/gnd a2/gnd t j (c) 300k 1m 3m 10m 30m 100m 300m 1g 3g -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 io1 io2 s21 (db) f (hz) figure 6. eye diagram pcb only 400 mv amplitude, f = 480 mbps figure 7. eye diagram pcb + USBULC6-2N4 400 mv amplitude, f = 480 mbps
ordering information scheme USBULC6-2N4 4/10 doc id 18332 rev 1 2 ordering information scheme figure 10. ordering information scheme figure 8. esd response to iec 61000-4-2 (+8 kv contact discharge) on one output v (out) and one input v (in) figure 9. esd response to iec 61000-4-2 (-8 kv contact discharge) on one output v (out) and one input v (in) 20 v/div 20 ns/div 20 v/div 20 ns/div usb ulc 6 ?2 n4 usb protection ultra low capacitance breakdown voltage 6 = 6 v number of lines 2 = 2 lines package n4 = qfn-4l
USBULC6-2N4 package information doc id 18332 rev 1 5/10 3 package information epoxy meets ul94, v0 lead-free package in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. note: product marking may be rotated by 90 for assembly plant differentiation. in no case should this product marking be used to orient the component for its placement on a pcb. only pin 1 mark is to be used for this purpose. table 3. qfn- 4l dimensions ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.45 0.50 0.55 0.018 0.020 0.022 a1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 d 0.75 0.80 0.85 0.030 0.031 0.033 d2 0.55 0.6 0.65 0.022 0.024 0.026 e 0.35 0.40 0.45 0.014 0.016 0.018 e 0.95 1.00 1.05 0.037 0.039 0.041 e2 0.15 0.20 0.25 0.006 0.008 0.010 k 0.17 0.20 0.23 0.007 0.008 0.009 l 0.15 0.20 0.25 0.006 0.008 0.010 a a1 d e k d2 e e2 b l bottom view side view figure 11. footprint recommendations (dimensions in mm) figure 12. marking 0.4 0.4 0.2 0.2 0.6 0.6 1.4 pin 1 1
package information USBULC6-2N4 6/10 doc id 18332 rev 1 figure 13. qfn-4l tape and reel specifications dot identifying pin a1 location user direction of unreeling all dimensions are typical values in mm 4.0 2.0 2.0 8.0 1.75 3.5 ? 1.55 0.63 0.89 0.22 1.07 1 1 1 1 1 1 1
USBULC6-2N4 recommendation on pcb assembly doc id 18332 rev 1 7/10 4 recommendation on pcb assembly 4.1 stencil opening design 1. reference design a) stencil opening thickness: 100 m b) stencil opening for central exposed pad: opening to footprint ratio is 50%. c) stencil opening for leads: opening to footprint ratio is 90%. figure 14. recommended stencil window position 4.2 solder paste 1. halide-free flux qualification rol0 according to ansi/j-std-004. 2. ?no clean? solder paste is recommended. 3. offers a high tack force to resist component movement during high speed. 4. solder paste with fine particles: powder particle size is 20-45 m. 180 m footprint footprint t=100 m and opening ratio is 100% 580 m 200 m 430 m stencil windo w 0.4 0.4 0.2 0.2 0.6 0.6 1.4
recommendation on pcb assembly USBULC6-2N4 8/10 doc id 18332 rev 1 4.3 placement 1. manual positioning is not recommended. 2. it is recommended to use the lead recognition capabilities of the placemen t system, not the outline centering. 3. standard tolerance of 0.05 mm is recommended. 4. 3.5 n placement force is recommended. too much placement force can lead to squeezed out solder paste and cause solder joints to short. too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. to improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. for assembly, a perfect supporting of the pcb (all the more on flexible pcb) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 4.4 pcb design preference 1. to control the solder paste amount, the closed via is recommended instead of open vias. 2. the position of tracks and open vias in the solder area should be well balanced. the symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. 4.5 reflow profile figure 15. st ecopack? recommended soldering reflow profile for pcb mounting note: minimize air convection currents in the reflow oven to avoid component movement. 0 01234567 time (min) temperature (c) 2c/s recommended 6c/s max 220c 125 c 260c max 255c 180c 90 sec max 10-30 sec 90 to 150 sec 3c/s max 0 01234567 time (min) temperature (c) 2c/s recommended 6c/s max 220c 125 c 260c max 255c 180c 90 sec max 10-30 sec 90 to 150 sec 3c/s max
USBULC6-2N4 ordering information doc id 18332 rev 1 9/10 5 ordering information 6 revision history table 4. ordering information order code marking package weight base qty delivery mode USBULC6-2N4 1 (1) 1. the marking can be rotated by 90 to differentiate assembly location qfn 1.17 mg 10000 tape and reel (7?) table 5. document revision history date revision changes 14-sep-2011 1 initial release.
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