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1 features description applications ddc316 www.ti.com ......................................................................................................................................................... sbas370a ? march 2008 ? revised april 2009 16-channel, current-input analog-to-digital converter 2 single-chip solution to measure 16 the ddc316 is a 16-bit, 16-channel, current-input low-level currents analog-to-digital converter (adc). it combines both current-to-voltage and analog-to-digital (a/d) integrating i-to-v conversion conversion so that 16 separate low-level current front-end output devices (such as photodiodes) can be directly programmable full-scale : 3pc to 12pc connected to its inputs and digitized. adjustable speed: for each of the 16 inputs, the ddc316 provides a ? data rate up to 100ksps dual-switched integrator front-end. this configuration ? integration time down to 10 m s allows for continuous current integration: while one integrator is being digitized by the on-chip adc, the analog supply: +5v other is integrating the input current. adjustable digital supply: +3.3v integration times range from 10 m s to 1ms. the ddc316 provides a serial interface of the output data, either multiplexed onto a single data output pin ct scanner das or parallel on four output pins. the output mode can photodiode sensors be selected based on the available integration time. x-ray detection systems the ddc316 uses a +5v analog supply and a +3.3v protected by us patent #5841310 digital supply. operating over the temperature range of 0 c to +70 c, the ddc316 is offered in a bga-64 package. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2008 ? 2009, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. control clkconv din_cfg reset ddc316 adcs agnd dgnd avdd dvdd vref i to v in1 in2in3 in4 in16 i to v serial interface dvalid dindclk dout1 dout2 dout3 dout4 i to v i to v i to v
package/ordering information absolute maximum ratings (1) ddc316 sbas370a ? march 2008 ? revised april 2009 ......................................................................................................................................................... www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . avdd to agnd ? 0.3v to +6v dvdd to dgnd ? 0.3v to +3.6v agnd to dgnd 0.2v vref input to agnd 2.0v to avdd + 0.3v analog input to agnd ? 0.3v to +0.7v digital input voltage to dgnd ? 0.3v to dvdd + 0.3v digital output voltage to dgnd ? 0.3v to avdd + 0.3v operating temperature 0 c to +70 c storage temperature ? 60 c to +150 c junction temperature (t j ) +150 c (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 2 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder link(s): ddc316
electrical characteristics ddc316 www.ti.com ......................................................................................................................................................... sbas370a ? march 2008 ? revised april 2009 at t a = +25 c, avdd = +5v, dvdd = +3.3v, vref = +4.096v, t int = 20 m s, range = 12pc, format = 16 bits, clk = 40mhz, and hi_speed bit = 1, unless otherwise noted. ddc316 parameter test conditions min typ max unit analog input range range 1 2.4 3 3.6 pc range 2 4.8 6 7.2 pc range 3 9.6 12 14.4 pc negative full-scale range ? 1.786% of positive full-scale range pc dynamic characteristics data rate 100 ksps integration time, t int hi_speed bit = 1 20 1,000 m s hi_speed bit = 0 10 20 m s system clock input 1 40 mhz data clock (dclk) 40 mhz daisy-chain readback 20 mhz accuracy resolution 12 16 bits noise, low-level input (1) c sensor (2) = 10pf 3.5 6.0 lsb (3) integral linearity error (4) 8 16 lsb (3) input bias current t a = +25 c 2 10 pa range error match (5) 0.2 1 % of fsr (6) range sensitivity to vref vref = 4.096 0.1v 1:1 offset error 50 200 lsb (3) offset error match (5) 75 400 lsb (3) dc bias voltage (7) low-level input ( < 1% fsr) 2 10 mv power-supply rejection ratio at dc 40 lsb (3) /v performance over temperature offset drift 1 lsb/ c offset drift stability continuous readings over 1-minute < 1 lsb intervals after a 10-minute warm-up dc bias voltage drift (7) 10 m v/ c input bias current drift doubles every +10 c range drift (8) 25 ppm/ c range drift match (5) 10 ppm/ c reference voltage 4.000 4.096 4.200 v digital input/output logic levels v ih 0.8dvdd dvdd + 0.1 v v il ? 0.1 0.2dvdd v v oh i oh = ? 100 m a dvdd ? 0.4 v v ol i ol = 100 m a 0.4 v input current (i in ) 0 < v in < dvdd 10 m a data format (9) straight binary (1) input is less than 1% of full-scale. (2) c sensor is the capacitance seen at the ddc316 inputs from wiring, photodiode, etc. (3) lsb refers to 16-bit resolution. (4) a best-fit line is used in measuring nonlinearity. (5) matching between side a and side b of the same input. (6) fsr is full-scale range. (7) voltage produced by the ddc316 at its input that is applied to the sensor. (8) range drift does not include external reference drift. (9) data format is straight binary with a small offset. the number of bits in the output word is controlled by the format bit. copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 3 product folder link(s): ddc316
ddc316 sbas370a ? march 2008 ? revised april 2009 ......................................................................................................................................................... www.ti.com electrical characteristics (continued) at t a = +25 c, avdd = +5v, dvdd = +3.3v, vref = +4.096v, t int = 20 m s, range = 12pc, format = 16 bits, clk = 40mhz, and hi_speed bit = 1, unless otherwise noted. ddc316 parameter test conditions min typ max unit power-supply requirements analog power-supply voltage (avdd) 4.75 5.0 5.25 v digital power-supply voltage (dvdd) 3 3.3 3.6 v supply current analog current internal reference buffer bufdis bit = 0 95 ma external reference buffer bufdis bit = 1 85 ma digital current dvdd = +3.3v 5 ma total power dissipation internal reference buffer bufdis bit = 0, dvdd = +3.3v 540 mw external reference buffer bufdis bit = 1, dvdd = +3.3v 440 640 mw per channel power dissipation internal reference buffer bufdis bit = 0, dvdd = +3.3v 31 mw/channel external reference buffer bufdis bit = 1, dvdd = +3.3v 28 40 mw/channel 4 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder link(s): ddc316
pin configuration ddc316 www.ti.com ......................................................................................................................................................... sbas370a ? march 2008 ? revised april 2009 gxg and zxg packages bga-64 (top view) pin descriptions pin location function description in1 ? 16 1a-1h, 2a-2h analog input analog inputs for channels 1 to 16 agnd 3a-3h, 4c, 5a-5g, 6d, 7d analog analog ground vref 4a, 6a, 6b analog input voltage reference for internal reference buffer mode vref_in 4b analog input voltage reference for external reference buffer mode avdd 4d-4h, 6e, 6f, 6g, 6h analog analog power supply, +5v nominal qgnd 5h analog quiet analog ground dgnd 6c, 7c, 7f digital digital ground reset 7a digital input digital reset, active low dvdd 7b, 8b digital digital power supply, +3v nominal din 7e digital input serial data input for daisy-chain din_cfg 7g digital input configuration register data input dvalid 7h digital output data valid output, active low conv 8a digital input conversion control input; 0 = integrate on side b, 1 = integrate on side a clk 8c digital input master clock input dclk 8d digital input serial data clock input dout4-1 8e-8h digital output serial data output copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 5 product folder link(s): ddc316 reset columns f d b g h e c a in10 in6 in14 in4 in2 in11 in8 in16 2 agnd agnd agnd agnd agnd agnd agnd agnd 3 avdd avdd vref_in avdd avdd avdd agnd vref 4 agnd agnd agnd agnd qgnd agnd agnd agnd 5 avdd agnd vref avdd avdd avdd dgnd vref 6 dout3 dclk dvdd dout2 dout1 dout4 clk conv 8 in9 in5 in13 in3 in1 in12 in7 in15 1 rows dgnd agnd dvdd din_cfg dvalid din dgnd 7
timing diagrams timing requirements for figure 1 ddc316 sbas370a ? march 2008 ? revised april 2009 ......................................................................................................................................................... www.ti.com figure 1. serial interface timing at t a = 0 c to +70 c and dvdd = 3v to 3.6v, unless otherwise noted. symbol description min typ max unit t clk clk period (1/f clk ) 25 1000 ns t clkpw clk pulse width, positive or negative 0.4 t clk periods hi_speed bit = 0 400 1000 t clk periods hi_speed bit = 0, clk = 40mhz 10 25 m s t inta,b integration time for sides a and b hi_speed bit = 1 800 40,000 t clk periods hi_speed bit = 1, clk = 40mhz 20 1000 m s hi_speed bit = 0 274 t clk periods time required to perform t meas measurement hi_speed bit = 1 544 t clk periods t didc setup time from din to rising edge of dclk 2 ns t dcdi hold time for din after rising edge of dclk 0 ns t dvdo (1) falling edge of dvalid to valid dout 6 10 ns t dcdv (1) falling edge of first dclk to rising edge of dvalid 19 ns t dclk dclk period (1/f dclk ) 25 ns t dclkpw dclk pulse width, positive or negative 0.4 t dclk periods t dopd (1) propagation delay from the falling edge of dclk to valid dout1 21 ns hold time during which previous dout1 is valid after falling edge of t dohd (1) 5 ns dclk t cndc time between conv toggle and data retrieval 5 ns (1) output load = 100k ? || 10pf 6 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder link(s): ddc316 conv dvalid clk t clk t clkpw dclk dout (1) side b data side a data t clkpw t dohd t dopd t dclkpw t dclkpw t dcdv t dvdo t inta t dclk t cndc t cndc t meas t intb msb lsb note: (1) dout1 in tdm data output mode; dout1 through dout4 in parallel data output mode. din t didc t dcdi
timing requirements for figure 2 ddc316 www.ti.com ......................................................................................................................................................... sbas370a ? march 2008 ? revised april 2009 figure 2. configuration register read/write timing at t a = 0 c to +70 c and dvdd = 3.0v to 3.6v, unless otherwise noted. symbol description min typ max unit t sc valid din_cfg to clk falling edge; setup time 1 12 ns t hc valid din_cfg to clk falling edge; hold time 3 12 ns t dvc (1) delay of dvalid from falling edge of clk 18 ns t dcdv (1) falling edge of first dclk to rising edge of dvalid 19 ns t dvdo (1) delay from dvalid falling edge to valid cfg bit 15 on dout1 6 10 ns t dopd (1) propagation delay from the falling edge of dclk to valid dout1 21 ns hold time during which previous dout1 is valid after falling edge of t dohd (1) 5 ns dclk (1) output load = 100k ? || 10pf copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 7 product folder link(s): ddc316 clk din_cfg dclk dvalid dout1 0 1 1 0 cfg bit 15 t dvc t dcdv t dopd cfg bit 15 cfg bit 0 t sc t hc cfg bit 0 t dohd t dvdo
typical characteristics ddc316 sbas370a ? march 2008 ? revised april 2009 ......................................................................................................................................................... www.ti.com at t a = +25 c, unless otherwise indicated. noise vs c sensor noise vs c sensor figure 3. 8 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder link(s): ddc316 2520 15 10 50 c (pf) sensor noise (16-bit lsbs of fsr, rms) 0 5 10 15 20 30 25 range 1 range 2 range 3 hi_speed bit = 1 c sensor (pf) 0 1020 30 50 100 3.34.1 5.1 5.4 6.4 9.4 5.67.2 9.2 9.7 11.617.8 10.213.1 17.5 18.6 22.3 34.3 range 3 range 2 range 1 noise (16-bit lsbs of fsr, rms) note: bit = 1. hi_speed
theory of operation general description ddc316 www.ti.com ......................................................................................................................................................... sbas370a ? march 2008 ? revised april 2009 time. the 16 integrators from one side of the inputs the ddc316 contains 16 identical input channels that are digitized, while the other 16 are integrating to perform the function of current-to-voltage integration, achieve continuous charge collection. the results followed by a multiplexed a/d conversion. integration from the conversion are stored in a serial output shift time is directly controlled via the conv pin. each register. the dvalid output goes low when the shift input uses a dual-switched integrator so that the register contains valid data. a block diagram of the current-to-voltage integration can be continuous over ddc316 is shown in figure 4 . figure 4. ddc316 block diagram copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 9 product folder link(s): ddc316 adc 1 dout1dout2 dout3 dout4 dvalid dclk in2 in1 vref dgnd dvdd agnd avdd in4 in3 in14 in13 in16 in15 clkconv din_cfg reset din adc 4 vref_in configuration and control digital input/output dual switched integrator dual switched integrator dual switched integrator dual switched integrator dual switched integrator dual switched integrator dual switched integrator dual switched integrator
basic integration cycle ddc316 sbas370a ? march 2008 ? revised april 2009 ......................................................................................................................................................... www.ti.com the topology of the front-end of the ddc316 is an the timing relationships of all of the switches shown analog integrator, as shown in figure 5 . in this in figure 5 are illustrated in figure 6 . note that diagram, only input in1 is shown. the input stage figure 6 conceptualizes the operation of the consists of an operational amplifier, a selectable integrator input stage of the ddc316 and should not feedback capacitor network (c f ), and several be used as an exact timing tool for design. switches that implement the integration cycle. figure 5. basic integration configuration for input 1 figure 6. conceptual basic integration timing diagram of integrator a (as illustrated in figure 5 ) 10 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder link(s): ddc316 0.75pf 0.75pf vref to converter s reset s ref s adc1a s inta s ref s intb in1 esd protection diodes input current integrator a integrator b (same as a) photodiode 1.5pf range[1] range[0] s adc1a vref integrator a voltage output configuration of integrator a wait convert wait convert integrate s ref s inta s intb s reset conv clk w ait reset wait reset integrate on side b integrate on side a integrate on side b
ddc316 www.ti.com ......................................................................................................................................................... sbas370a ? march 2008 ? revised april 2009 figure 7 shows the block diagrams of the five states charge from the input signal is collected on the of the front end integrator. the conversion starts with integration capacitor, causing the voltage output of the integrator being configured as shown in the amplifier to decrease. the falling edge of conv figure 7 a. in this state, the adc converts the stops the integration by switching the input signal integrated value of side a of the previous phase. from side a to side b (s inta and s intb ). before the once the conversion is done, the integrator waits until falling edge of conv, the signal on side b was the adc finishes converting the other three integrated converted by the adc and reset during the time that values (figure 7 b). at the completion of all four a/d side a was integrating. with the falling edge of conversions, the charge on the integrator capacitor conv, side b starts integrating the input signal. at (c f ) is reset with s ref and s reset (see figure 7 c). in this point, the output voltage of the side a operational this manner, the selected capacitor is charged to the amplifier is presented to the input of the adc, and reference voltage, vref. once the integration the entire cycle repeats. capacitor is charged, s ref and s reset are switched this internal switching network is controlled externally so that vref is no longer connected to the amplifier with the convert pin (conv) and the system clock circuit while it waits to begin integrating (see (clk). for the best noise performance, conv must figure 7 d). with the rising edge of conv, s inta be synchronized with the rising edge of clk. it is closes, which begins the integration of side a. this recommended that conv toggle within 5ns of the process puts the integrator stage into integrate mode rising edge of clk. the noninverting inputs of the (see figure 7 e). integrators are connected to ground. consequently, the ddc316 analog ground should be as clean as possible. figure 7. diagrams for the five configurations of ddc316 front-end integrators copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 11 product folder link(s): ddc316 vref s reset s adc s ref s int in c f c) reset configuration s reset s adc vref s ref s int in c f e) integrate configuration s reset s adc vref s ref s int in c f a) convert configuration to converter s reset s ref s adc vref s ref s int in c f d) wait to integrate configuration to converter to converter to converter s reset s adc vref s ref s int in c f b) wait to reset configuration to converter s ref s ref s ref s ref
ranges frequency response resolution data format operation settings ddc316 sbas370a ? march 2008 ? revised april 2009 ......................................................................................................................................................... www.ti.com there are three different capacitors available on-chip the frequency response of the ddc316 is set by the for both sides of every channel in the ddc316. the front-end integrators and is consistent with a range control bits (range[1:0]) change the capacitor traditional continuous time integrator, as shown in value for all integrators. consequently, all inputs and figure 8 . by adjusting t int , the user can change the both sides of each input always have the same 3db bandwidth and the location of the notches in the full-scale (fs) range. table 1 shows the capacitor response. the frequency response of the adc that value selected for each range selection. follows the front-end integrator is of no consequence because the converter samples a held signal from the table 1. range selection integrators. that is, the input to the adc is always a dc signal. aliasing can occur because the output of range[1:0] c f input range the front-end integrators are sampled. whenever the range bits (pf, typ) (pc, typ) frequency of the input signal exceeds one-half of the 1 00 0.75 ? 0.0469 to 3 sampling rate, the signal folds back down to lower 2 01 1.5 ? 0.0938 to 6 frequencies. 3 10 3 ? 0.1876 to 12 the ddc316 provides three different resolutions for the convenience of the user. the user can select the resolution needed for the application and the time available for data retrieval. the three available resolutions are 16-bit, 14-bit, and 12-bit. the serial output data from the ddc316 are provided in an offset binary code, as shown in table 2 . the res bits in the configuration register select how many bits are used in the output word. when 12-bits are selected, the last four bits are truncated; when 14-bits are chosen, the last two bits are truncated. note that an offset is included in the output to allow slightly negative inputs (for example, from board leakages) from clipping the reading. the offset is approximately 1.8% of the positive full-scale. figure 8. ddc316 frequency response the ddc316 outputs 12 to 16 bits of data depending the ddc316 provides different settings of operation on the selected resolution. the format is straight to provide flexibility in terms of range, resolution, etc. binary with an offset to help prevent leakage currents the settings are programmable using an on-chip from the printed circuit board (pcb), or the sensors register and are described in the following sections. forcing a clipping on the negative full-scale. table 2 summarizes the ideal output codes for the different resolutions. table 2. ideal output code (1) vs input signal input ideal output code ideal output code ideal output code signal resolution = 16 bits resolution = 14 bits resolution = 12 bits 100% fs 1111 1111 1111 1111 1111 1111 1111 11 1111 1111 1111 0.07019% fs 0000 0100 1100 0000 0000 0100 1100 00 0000 0100 1100 0.02136% fs 0000 0100 1010 0000 0000 0100 1010 00 0000 0100 1010 0.00305% fs 0000 0100 1001 0100 0000 0100 1001 01 0000 0100 1001 0.001525% fs 0000 0100 1001 0011 0000 0100 1001 00 0000 0100 1001 0% fs 0000 0100 1001 0010 0000 0100 1001 00 0000 0100 1001 ? 1.7857% fs 0000 0000 0000 0000 0000 0000 0000 00 0000 0000 0000 (1) excludes the effects of noise, inl, offset, and gain errors. 12 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder link(s): ddc316 0 - 10 - 20 - 30 - 40 - 50 0.1 t int 100 t int 1 t int 10 t int frequency gain (db)
data output modes ddc316 www.ti.com ......................................................................................................................................................... sbas370a ? march 2008 ? revised april 2009 the ddc316 provides two data output modes: time in parallel output mode, as shown in figure 10 , four division multiplexed (tdm) and parallel. in tdm channels of data are output on the four dout lines, mode, data from all 16 channels are output on a dout1 thorough dout4. single data output line, dout1, as shown in figure 9 . in this mode, dout2 through dout4 are not used in either mode, the most significant bit (msb) is and forced to logic low. shifted out first. figure 9. tdm data output figure 10. parallel data output copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 13 product folder link(s): ddc316 dout2 dout3 dout4 64 dclks (16-bit resolution) conv dvalid dout1 dclk clk data for inputs 1, 2, 3, 4 data for inputs 5, 6, 7, 8 data for inputs 9, 10, 11, 12 data for inputs 13, 14, 15, 16 256 dclks (16-bit resolution) conv dvalid dout1 dout2 dout3 dout4 dclk clk tdm data for inputs 1, 2, 3, 4, 9, 10, 11, 12, 13, 14, 15, 16 5, 6, 7, 8,
minimum integration time data retrieval time ddc316 sbas370a ? march 2008 ? revised april 2009 ......................................................................................................................................................... www.ti.com the minimum integration time of the ddc316 is set the available time for retrieving the conversion data by the master clock (clk) and the hi_speed bit, as (t retrv ) from the ddc316 is the difference between shown in table 3 . the integration time specification the integration time (t int ) and the measurement time must always be met for both side a and side b (t meas ), as shown in figure 11 . retrieval begins after integrations (t inta and t intb ). failure to meet dvalid goes low, and must complete before conv integration time specifications gives invalid toggles, for optimal noise performance (see the t cndc conversion results. timing specification). sometimes, it is not possible to retrieve all of the data table 3. minimum integration times in time when using the tdm data output mode; for hi_speed valid minimum integration time example, when integration times are short and dclk bit resolutions (minimum t int ) is slow. in these cases, using the parallel data output 400 t clk 10 m s mode will help because the required time for retrieval 0 12-bit only periods (for clk = 40mhz) decreases by a factor of four. 800 t clk 20 m s 1 12-bit to 16-bit periods (for clk = 40mhz) when operating with the hi_speed bit set to 0, the ddc316 operates internally at a higher speed and the performance is reduced to fundamentally 12 bits. it is recommended, therefore, that the res[1:0] bits should be set to 12-bit resolution when hi_speed = 0. this will provide more flexibility in retrieving data, because the time required to read back the conversion results is shorter. figure 11. data retrieval time 14 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder link(s): ddc316 conv t int t meas t cndc t retrv dvalid dclk dout
configuration register bit descriptions ddc316 www.ti.com ......................................................................................................................................................... sbas370a ? march 2008 ? revised april 2009 the ddc316 configuration shown in table 4 is controlled by and configured with an on-chip, 16-bit configuration register. table 4. configuration register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 1 mode res[1] res[0] range[1] range[0] 0 hi_speed bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tm[1] tm[0] 0 bufdis 0 0 0 0 the following section gives a brief description of the programmable bits and the method to program the bits. note that in the event of an external reset or a power-on reset, all the configuration bits are set to default values. the bits need to be reprogrammed as needed after a reset. bit 15 unused bit. this bit must always be set to one. during a power-up or reset event, this bit is set to zero and must be programmed to one. bit 14 mode? data output mode. this bit selects between the parallel and serial data output (time division multiplexing, or tdm) modes, as shown in table 5 . table 5. data output mode mode data output mode parallel, using dout1, dout2, dout3, and dout4 0 (default) 1 serial, time division multiplexed (tdm) on dout1 bits 13-12 res[1:0]? output data resolution. these bits set the output data resolution. the value of the output resolution is the same for res[1:0] = '10' and res[1:0] = '11'. table 6. output data resolution res[1:0] output resolution 00 16 bits (default) 01 14 bits 10 12 bits 11 bits 11-10 range[1:0]? full-scale input range. these range bits set the value of the integration capacitors that are used in the dual-switched integrators. table 7 shows the three different capacitor values available. the value of the maximum input charge is the same for range = '10' and range = '11'. table 7. full-scale range range[1:0] maximum input charge 00 3pc (default) 01 6pc 10 12pc 11 copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 15 product folder link(s): ddc316
ddc316 sbas370a ? march 2008 ? revised april 2009 ......................................................................................................................................................... www.ti.com bit 9 unused bit. this bit is reset to zero and must always be set to zero. bit 8 hi_speed? high-speed operation selection. this bit sets which speed (normal or high) will be used. the default is normal speed, and is the generally recommended operating condition. however, if shorter integration times are needed than are supported during normal operation, then high-speed mode is available. note that performance reduces to the 12-bit level during high-speed mode. table 8. high-speed mode selection hi_speed speed 0 high speed 1 normal speed (default) bits 7-6 tm[1:0]? test mode selection. test mode (tm) bits allow for configuration of the device to operate in either normal mode or test modes for verification purposes, as shown in table 9 . the test modes are provided as a means of evaluating the ddc316 noise. in test mode 1, the inputs (in1 through in16) are disconnected from the ddc316 integrators to enable the user to measure a zero input signal, regardless of the current supplied to the ddc316 by the external sensor. in test mode 2, the inputs (in1 through in16) are disconnected from the ddc316 integrators and at the same time a 10pf capacitor is added to the input to emulate the sensor capacitance. in test mode 3, the inputs are disconnected from the ddc316 integrators. each time a new conversion begins (conv toggles), a fixed amount of charge (approximately 1.5pc) is dumped into the integrator. table 9. test mode decoding tm[1:0] test mode function 00 normal mode (default) 01 test mode 1 (inputs opened) test mode 2 (inputs opened and 10pf internal 10 capacitor connected to integrators) test mode 3 (inputs opened and 1.5pc charge 11 dumped into the integrators during each conversion) bit 5 unused bit. this bit is reset to zero and must always be set to zero. bit 4 bufdis? internal reference buffer disable. this bit is used to turn the internal reference buffer off, as shown in table 10 . see the voltage reference section for more details. table 10. internal reference buffer disable bufdis internal reference buffer status 0 internal buffer enabled 1 internal buffer disabled (default) bits 3-0 unused bits. these bits are reset to zero and must always be set to zero. 16 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder link(s): ddc316
writing and reading of the configuration register data valid ( dvalid) system and data clocks (clk and ddc316 www.ti.com ......................................................................................................................................................... sbas370a ? march 2008 ? revised april 2009 the integration and conversion process is fundamentally independent of the data retrieval figure 2 shows the timing diagram for writing to and process. consequently, the clk and dclk reading from the configuration register. writing and frequencies need not be the same, although for best reading must be done before or after conv toggles. performance, it is highly recommended that they be the data on pin din_cfg are latched on the falling derived from the same clocking source to keep their edge of clk. the first four bits are used as phase relationship constant. preamble; only when these bits equal '1010' are the contents of the following 16 bits loaded into the when using multiple ddc316s, pay close attention to configuration register. once the content is loaded, the the dclk distribution on the printed circuit board shift register immediately clears so that a new (pcb). in particular, make sure to minimize skew in configuration can be written, if needed. it is the dclk signal because the skew can lead to timing recommended to leave the din_cfg pin to logic '0' violations in the serial interface specifications. when not programming the register. once the configuration register updates, it is loaded into the data shift register to be output on dout1. the dvalid signal indicates that data are ready. when dvalid is goes low, the configuration register data retrieval may begin after dvalid goes low. this is available to be read. if the data are not read back, signal goes low on the rising edge of the system then the register is overwritten by the conversion data clock (clk), and goes high on the first falling edge of on the following conversion. data are shifted out on dclk during the data retrieval process. data retrieval the falling edge of dclk. from the ddc316 can be done either by polling the dvalid signal or by counting the number of clock cycles after a transition of the conv signal. while dclk) using the counting method, the number of clock cycles to wait depends on the mode of operation, the system clock is supplied to clk and the data either the low power or the high speed mode. the clock is supplied to dclk. make sure the clock exact number of clk cycles to wait for the two signals are clean; avoid overshoot or ringing. dclk different modes is given in table 3 . should be held low after the data have been shifted out, or while conv is transitioning; dclk should not be left free-running. copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 17 product folder link(s): ddc316
readback with multiple ddc316s ddc316 sbas370a ? march 2008 ? revised april 2009 ......................................................................................................................................................... www.ti.com the serial interface supports daisy-chaining to note that daisy-chaining is only supported in tdm simplify connections when using multiple ddc316s output mode, and will not work when using parallel together. figure 12 shows an example of a data output mode. when the daisy-chaining function 64-channel system. the din pin is used to shift data is not used, connect din to digital ground. into the ddc316s. additional dclk pulses must then be given during readback to ensure all the data have shifted through, as shown in figure 13 . figure 12. daisy-chain configuration of a 64-channel system figure 13. daisy-chain readback of four devices (64 channels) 18 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder link(s): ddc316 in16in15 in14 in13 in4 in3 in2 in1 in16in15 in14 in13 in4 in3 in2 in1 in16in15 in14 in13 in4 in3 in2 in1 in16in15 in14 in13 in4 in3 in2 in1 6463 62 61 52 51 50 49 4847 46 45 36 35 34 33 3231 30 29 20 19 18 17 1615 14 13 43 2 1 sensor din dout1 ddc316 data retrieval output data clock din dout1 ddc316 din dout1 ddc316 din dout1 ddc316 dv alid dclk dvalid dclk dv alid dclk dv alid dclk dvalid dclk din t stdidc t hddidc dout input 64 msb input 64 msb input 64 lsb input 63 msb input 3 lsb input 2 msb input 2 lsb input 1 msb input 1 lsb
voltage reference external vref buffer internal vref buffer ddc316 www.ti.com ......................................................................................................................................................... sbas370a ? march 2008 ? revised april 2009 quality capacitors with low esr ( < 1 ? ) are necessary for optimum performance. high esr capacitors will the reference voltage is used to reset the integration lead to oscillation of the internal buffer. ceramic capacitors before an integration cycle begins. it is capacitors with esr < 1 ? at 100khz are also used by the adcs when they measure the recommended. voltage stored on the integrators after an integration cycle ends. during this sampling, the external reference must supply the charge needed by the adcs. for an integration time of 20 m s, this charge translates to an average vref current of approximately 270 m a. the amount of charge needed by the adc is independent of the integration time; therefore, increasing the integration time lowers the average current. for example, an integration time of 40 m s lowers the average vref current to 135 m a. it is critical that vref be stable during the different modes of operation (see figure 7 ). the adc measures the voltage on the integrator with respect figure 14. recommended circuit when using the to vref. since the integrator capacitors are initially internal vref buffer reset to vref, any drop in vref, from the time the capacitors are reset to the time when the converter measures the integrator output, introduces an offset. it is also important that vref be stable over longer the internal buffer can be turned off using the control periods of time because changes in vref bits as explained in the configuring the modes correspond directly to changes in the full-scale range. section under bit 4 and table 10 . for this option, finally, vref should introduce as little additional configure the driving circuit as illustrated in figure 15 . noise as possible. for these reasons, it is strongly the voltage reference is generated by a +4.096v recommended that the external reference source be reference. a low-pass filter to reduce noise connects buffered with an operational amplifier. the reference to an operational amplifier configured as a buffer. the vref_in pin must be left the ddc316 offers two options for driving the disconnected. reference voltage: through an external buffer or through an internal buffer. in both the cases, the this amplifier used as buffer should have low noise reference voltage is generated external to the chip and input/output common-mode ranges that support using an accurate reference, such as the ref3140 . vref. even though the circuit in figure 15 might appear to be unstable as a result of the large output capacitors, it works well for most operational amplifiers. it is not recommended that series the ddc316 provides an internal vref buffer to resistance be placed in the output lead to improve drive the four on-chip adcs. the reference voltage stability because it can cause a drop in vref and must be provided at vref_in (pin 4b), as shown in produce large offsets. figure 14 . the external capacitors at the vref pins are necessary to stabilize the internal buffer. it is recommended that these capacitors be placed as close as possible to the device under test. also, good figure 15. recommended circuit when using an external vref buffer copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 19 product folder link(s): ddc316 10k w 10 f m 3 1 2 + 0.47 f m +5v vref (4a, 6a, 6b) ref3140 10 f m + vref_in (4b) 0.1 f m ddc316 0.1 f m opa350 0.1 f m +5v 10k w 10 f m 4 3 2 3 1 2 7 6 + 0.1 f m 10 f m + 0.47 f m +5v ref3140 vref (4a, 6a, 6b) vref_in (4b) 0.1 f m ddc316
reset ( reset) layout power supplies and grounding power-up sequencing shielding analog signal paths ddc316 sbas370a ? march 2008 ? revised april 2009 ......................................................................................................................................................... www.ti.com the ddc316 can be reset asynchronously by taking the reset input low. make sure the reset pulse is at least two clk cycles wide. once the reset signal is both avdd and dvdd should be as quiet as pulled high, the internal reset is released t rst later, possible. it is particularly important to eliminate noise after which the configuration register can be written. it from avdd that is nonsynchronous with the ddc316 is very important that reset is glitch-free to avoid operation. for this reason, switching-supplies are not unintentional resets. recommended. figure 18 illustrates how to supply power to the ddc316. each supply of the ddc316 should be bypassed with 10 m f solid ceramic capacitors. it is recommended that both the analog and digital grounds (agnd and dgnd) be connected to a single ground plane on the pcb. figure 16. reset timing figure 18. power-supply connections figure 17 shows the internal timing after the part powers up. once the digital supply is above the threshold voltage, the internal power-on reset circuit releases the por signal. the internal reset signal to as with any precision circuit, careful pcb layout the digital logic is released t por time after the ensures the best performance. it is essential to make por internal , after which the configuration register short, direct interconnections and avoid stray wiring can be written. capacitance, particularly at the analog input pins and qgnd. these analog input pins are high-impedance and extremely sensitive to extraneous noise. the qgnd pin should be treated as a sensitive analog signal and connected directly to the supply ground with proper shielding. leakage currents between the pcb traces can exceed the input bias current of the ddc316 if shielding is not implemented. digital signals should be kept as far as possible from the analog input signals on the pcb. figure 17. power-up timing table 11. timing figure 16 and figure 17 symbol description min typ max units t rst,pul reset pin low width 2 t clk periods t rst wait from reset high to beginning of configuration register write 20 t clk periods t por wait from power-up to power-on reset release 40,000 t clk periods 20 submit documentation feedback copyright ? 2008 ? 2009, texas instruments incorporated product folder link(s): ddc316 t rst,pul t rst clk reset din_cfg reset internal t clk period avdd dvdd agnd dgnd ddc316 10 f m va 10 f m vd clk por internal din_cfg t por reset internal
ddc316 www.ti.com ......................................................................................................................................................... sbas370a ? march 2008 ? revised april 2009 revision history note: page numbers for previous revisions may be differ from page numbers in the current version. changes from original (march 2008) to revision a ....................................................................................................... page changed test condition for offset drift stability specification ................................................................................................ 3 changed figure 1 ................................................................................................................................................................. 6 changed figure 2 ................................................................................................................................................................. 7 added missing text ................................................................................................................................................................. 9 deleted duplicate mechanical package drawing .................................................................................................................. 20 copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback 21 product folder link(s): ddc316
package option addendum www.ti.com 17-feb-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ddc316cgxgr active nfbga gxg 64 1000 tbd sn/pb level-3-240c-168 hr 0 to 70 ddc316 ddc316cgxgt active nfbga gxg 64 250 tbd sn/pb level-3-240c-168 hr 0 to 70 ddc316 ddc316czxgr active nfbga zxg 64 1000 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 70 ddc316 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 17-feb-2017 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ddc316cgxgr nfbga gxg 64 1000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 q1 ddc316cgxgt nfbga gxg 64 250 180.0 16.4 8.3 8.3 2.25 12.0 16.0 q1 ddc316czxgr nfbga zxg 64 1000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 q1 package materials information www.ti.com 11-feb-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ddc316cgxgr nfbga gxg 64 1000 336.6 336.6 28.6 ddc316cgxgt nfbga gxg 64 250 213.0 191.0 55.0 ddc316czxgr nfbga zxg 64 1000 336.6 336.6 28.6 package materials information www.ti.com 11-feb-2017 pack materials-page 2

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