sn74bct756 octal buffer/driver with open-collector outputs scbs056b october 1990 revised july 1997 1 post office box 655303 ? dallas, texas 75265 bicmos design significantly reduces i ccz esd protection exceeds 2000 v per mil-std-883, method 3015; exceeds 200 v using machine model (c = 200 pf, r = 0) open-collector outputs drive bus lines or buffer memory address registers package options include plastic small-outline packages (dw) and standard plastic 300-mil dips (n) description this octal buffer and line driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. the sn74bct756, sn74bct757, and sn74bct760 provide the choice of selected combinations of inverting outputs, symmetrical output-enable (oe ) inputs, and complementary oe and oe inputs. the sn74bct756 is characterized for operation from 0 c to 70 c. function table inputs output oe a y h x h l lh l h l logic symbol 2 2 1a1 4 1a2 6 1a3 8 1a4 en 1 1y1 18 1y2 16 1y3 14 1y4 12 11 2a1 13 2a2 15 2a3 17 2a4 en 19 2y1 9 2y2 7 2y3 5 2y4 3 1oe 2oe 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. copyright ? 1997, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 1oe 1a1 2y4 1a2 2y3 1a3 2y2 1a4 2y1 gnd v cc 2oe 1y1 2a4 1y2 2a3 1y3 2a2 1y4 2a1 dw or n package (top view)
sn74bct756 octal buffer/driver with open-collector outputs scbs056b october 1990 revised july 1997 2 post office box 655303 ? dallas, texas 75265 logic diagram (positive logic) 1 2 18 1oe 1a1 1y1 4 16 1a2 1y2 6 14 1a3 1y3 8 12 1a4 1y4 19 11 9 2oe 2a1 2y1 13 7 2a2 2y2 15 5 2a3 2y3 17 3 2a4 2y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v cc 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input current range, i i 30 ma to 5 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the disabled or power-off state, v o 0.5 v to 5.5 v . . . . . . . . . . . . . . . . voltage range applied to any output in the high state, v o 0.5 v to v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . current into any output in the low state 128 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, q ja (see note 1): dw package 97 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . n package 67 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: the package thermal impedance is calculated in accordance with jesd 51. recommended operating conditions min nom max unit v cc supply voltage 4.5 5 5.5 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v v oh high-level output voltage 5.5 v i ik input clamp current 18 ma i ol low-level output current 64 ma t a operating free-air temperature 0 70 c
sn74bct756 octal buffer/driver with open-collector outputs scbs056b october 1990 revised july 1997 3 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ 2 max unit v ik v cc = 4.5 v, i i = 18 ma 1.2 v i oh v cc = 4.5 v, v oh = 5.5 v 0.1 ma v ol v cc = 4.5 v, i ol = 64 ma 0.42 0.55 v i i v cc = 5.5 v, v i = 7 v 0.1 ma i ih v cc = 5.5 v, v i = 2.7 v 20 m a i il v cc = 5.5 v, v i = 0.5 v 1 ma outputs high 21 33 i cc v cc = 5.5 v, outputs open outputs low 55 86 ma oe disable 6 10 c i v cc = 5 v, v i = 2.5 v or 0.5 v 6 pf c o v cc = 5 v, v i = 2.5 v or 0.5 v 10 pf 2 all typical values are at v cc = 5 v, t a = 25 c. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, c l = 50 pf (unless otherwise noted) (see figure 1) parameter from (input) to (output) v cc = 5 v, c l = 50 pf, r1 = 500 w , r2 = 500 w , t a = 25 c v cc = 4.5 to 5.5 v, c l = 50 pf, r1 = 500 w , r2 = 500 w , t a = min to max 3 unit min typ max min max t plh a y 6.2 8.5 10.5 6.2 11.3 ns t phl a y 0.5 2 4.1 0.5 4.2 ns t plh oe y 8.2 12.5 14.8 8.2 16.5 ns t phl oe y 3.4 6.8 9.2 3.4 10.3 ns 3 for conditions as min or max, use the appropriate value specified under recommended operating conditions.
sn74bct756 octal buffer/driver with open-collector outputs scbs056b october 1990 revised july 1997 4 post office box 655303 ? dallas, texas 75265 parameter measurement information t plh t phl t phl t plh v oh v oh v ol v ol 3 v 0 v input out-of-phase output in-phase output voltage waveforms propagation delay times output control (low-level enable) high-level pulse output waveform 2 (see note b) v ol v oh t pzl t pzh t plz t phz 3.5 v 0 v 0 v 3 v voltage waveforms enable and disable times, 3-state outputs notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, t r =t f 2.5 ns, duty cycle = 50%. d. the outputs are measured one at a time with one input transition per measurement. 0.3 v 0.3 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 0 v 0 v t h t su voltage waveforms setup and hold times data input timing input 3 v 3 v 1.5 v 1.5 v 1.5 v c l (see note a) load circuit voltage waveforms pulse duration 3 v 0 v 1.5 v 1.5 v 3 v 0 v 1.5 v 1.5 v low-level pulse t w from output under test 7 v (t pzl , t plz , o.c.) open (all others) test point r2 r l = r1 = r2 s1 r1 output waveform 1 (see note b) figure 1. load circuit and voltage waveforms
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